58 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -aarch64-stack-hazard-size=0 | FileCheck %s --check-prefix=CHECK03; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -aarch64-stack-hazard-size=1024 | FileCheck %s --check-prefix=CHECK10244 5;; The following run lines check the default values for aarch64-stack-hazard-size/aarch64-streaming-hazard-size.6 7;; When +sme,+sve is set the hazard size should default to 1024.8; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -mattr=+sve | FileCheck %s --check-prefix=CHECK10249 10;; The hazard size can still be overridden/disabled when +sme,+sve is set.11; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -mattr=+sve -aarch64-stack-hazard-size=0 | FileCheck %s --check-prefix=CHECK012 13;; When +sme-fa64 is set alongside +sme,+sve the default hazard size should be 0.14; RUN: llc < %s -mtriple=aarch64 -mattr=+sme-fa64 -mattr=+sme -mattr=+sve | FileCheck %s --check-prefix=CHECK015 16;; When +sme is set (without +sve) the default hazard size should be 0.17; RUN: llc < %s -mtriple=aarch64 -mattr=+sme | FileCheck %s --check-prefix=CHECK018 19define i32 @spill_fpr_with_gpr_stack_object(i64 %d) "aarch64_pstate_sm_compatible" {20; CHECK0-LABEL: spill_fpr_with_gpr_stack_object:21; CHECK0: // %bb.0: // %entry22; CHECK0-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill23; CHECK0-NEXT: .cfi_def_cfa_offset 1624; CHECK0-NEXT: .cfi_offset b8, -1625; CHECK0-NEXT: mov x8, x026; CHECK0-NEXT: mov w0, wzr27; CHECK0-NEXT: //APP28; CHECK0-NEXT: //NO_APP29; CHECK0-NEXT: str x8, [sp, #8]30; CHECK0-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload31; CHECK0-NEXT: ret32;33; CHECK1024-LABEL: spill_fpr_with_gpr_stack_object:34; CHECK1024: // %bb.0: // %entry35; CHECK1024-NEXT: sub sp, sp, #104036; CHECK1024-NEXT: str d8, [sp] // 8-byte Spill37; CHECK1024-NEXT: str x29, [sp, #1032] // 8-byte Spill38; CHECK1024-NEXT: sub sp, sp, #104039; CHECK1024-NEXT: .cfi_def_cfa_offset 208040; CHECK1024-NEXT: .cfi_offset w29, -841; CHECK1024-NEXT: .cfi_offset b8, -104042; CHECK1024-NEXT: mov x8, x043; CHECK1024-NEXT: mov w0, wzr44; CHECK1024-NEXT: //APP45; CHECK1024-NEXT: //NO_APP46; CHECK1024-NEXT: str x8, [sp, #8]47; CHECK1024-NEXT: add sp, sp, #104048; CHECK1024-NEXT: ldr x29, [sp, #1032] // 8-byte Reload49; CHECK1024-NEXT: ldr d8, [sp] // 8-byte Reload50; CHECK1024-NEXT: add sp, sp, #104051; CHECK1024-NEXT: ret52entry:53 %a = alloca i6454 tail call void asm sideeffect "", "~{d8}"() #155 store i64 %d, ptr %a56 ret i32 057}58