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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i8 @i8(i8 %a, i8 %b) {6; CHECK-LABEL: i8:7; CHECK: // %bb.0: // %entry8; CHECK-NEXT: sub w0, w0, w19; CHECK-NEXT: ret10entry:11 %s = sub i8 %a, %b12 ret i8 %s13}14 15define i16 @i16(i16 %a, i16 %b) {16; CHECK-LABEL: i16:17; CHECK: // %bb.0: // %entry18; CHECK-NEXT: sub w0, w0, w119; CHECK-NEXT: ret20entry:21 %s = sub i16 %a, %b22 ret i16 %s23}24 25define i32 @i32(i32 %a, i32 %b) {26; CHECK-LABEL: i32:27; CHECK: // %bb.0: // %entry28; CHECK-NEXT: sub w0, w0, w129; CHECK-NEXT: ret30entry:31 %s = sub i32 %a, %b32 ret i32 %s33}34 35define i64 @i64(i64 %a, i64 %b) {36; CHECK-LABEL: i64:37; CHECK: // %bb.0: // %entry38; CHECK-NEXT: sub x0, x0, x139; CHECK-NEXT: ret40entry:41 %s = sub i64 %a, %b42 ret i64 %s43}44 45define i128 @i128(i128 %a, i128 %b) {46; CHECK-LABEL: i128:47; CHECK: // %bb.0: // %entry48; CHECK-NEXT: subs x0, x0, x249; CHECK-NEXT: sbc x1, x1, x350; CHECK-NEXT: ret51entry:52 %s = sub i128 %a, %b53 ret i128 %s54}55 56define void @v2i8(ptr %p1, ptr %p2) {57; CHECK-SD-LABEL: v2i8:58; CHECK-SD: // %bb.0: // %entry59; CHECK-SD-NEXT: ldr h0, [x0]60; CHECK-SD-NEXT: ldr h1, [x1]61; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #062; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #063; CHECK-SD-NEXT: usubl v0.4s, v0.4h, v1.4h64; CHECK-SD-NEXT: mov s1, v0.s[1]65; CHECK-SD-NEXT: str b0, [x0]66; CHECK-SD-NEXT: stur b1, [x0, #1]67; CHECK-SD-NEXT: ret68;69; CHECK-GI-LABEL: v2i8:70; CHECK-GI: // %bb.0: // %entry71; CHECK-GI-NEXT: ld1 { v0.b }[0], [x0]72; CHECK-GI-NEXT: ld1 { v1.b }[0], [x1]73; CHECK-GI-NEXT: ldr b2, [x0, #1]74; CHECK-GI-NEXT: ldr b3, [x1, #1]75; CHECK-GI-NEXT: mov v0.s[1], v2.s[0]76; CHECK-GI-NEXT: mov v1.s[1], v3.s[0]77; CHECK-GI-NEXT: sub v0.2s, v0.2s, v1.2s78; CHECK-GI-NEXT: mov s1, v0.s[1]79; CHECK-GI-NEXT: str b0, [x0]80; CHECK-GI-NEXT: str b1, [x0, #1]81; CHECK-GI-NEXT: ret82entry:83 %d = load <2 x i8>, ptr %p184 %e = load <2 x i8>, ptr %p285 %s = sub <2 x i8> %d, %e86 store <2 x i8> %s, ptr %p187 ret void88}89 90define void @v3i8(ptr %p1, ptr %p2) {91; CHECK-SD-LABEL: v3i8:92; CHECK-SD: // %bb.0: // %entry93; CHECK-SD-NEXT: sub sp, sp, #1694; CHECK-SD-NEXT: .cfi_def_cfa_offset 1695; CHECK-SD-NEXT: ldr s0, [x0]96; CHECK-SD-NEXT: ldr s1, [x1]97; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b98; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v0.8b99; CHECK-SD-NEXT: sub v0.4h, v0.4h, v1.4h100; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b101; CHECK-SD-NEXT: mov h0, v0.h[2]102; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0103; CHECK-SD-NEXT: stur b0, [x0, #2]104; CHECK-SD-NEXT: str h1, [x0]105; CHECK-SD-NEXT: add sp, sp, #16106; CHECK-SD-NEXT: ret107;108; CHECK-GI-LABEL: v3i8:109; CHECK-GI: // %bb.0: // %entry110; CHECK-GI-NEXT: ldr w8, [x0]111; CHECK-GI-NEXT: ldr w9, [x1]112; CHECK-GI-NEXT: fmov s0, w8113; CHECK-GI-NEXT: fmov s1, w9114; CHECK-GI-NEXT: mov b2, v0.b[1]115; CHECK-GI-NEXT: mov b3, v1.b[1]116; CHECK-GI-NEXT: mov b4, v0.b[2]117; CHECK-GI-NEXT: mov b5, v1.b[2]118; CHECK-GI-NEXT: fmov w8, s2119; CHECK-GI-NEXT: fmov w9, s3120; CHECK-GI-NEXT: mov v0.h[1], w8121; CHECK-GI-NEXT: mov v1.h[1], w9122; CHECK-GI-NEXT: fmov w8, s4123; CHECK-GI-NEXT: fmov w9, s5124; CHECK-GI-NEXT: mov v0.h[2], w8125; CHECK-GI-NEXT: mov v1.h[2], w9126; CHECK-GI-NEXT: sub v0.4h, v0.4h, v1.4h127; CHECK-GI-NEXT: mov h1, v0.h[1]128; CHECK-GI-NEXT: mov h2, v0.h[2]129; CHECK-GI-NEXT: str b0, [x0]130; CHECK-GI-NEXT: str b1, [x0, #1]131; CHECK-GI-NEXT: str b2, [x0, #2]132; CHECK-GI-NEXT: ret133entry:134 %d = load <3 x i8>, ptr %p1135 %e = load <3 x i8>, ptr %p2136 %s = sub <3 x i8> %d, %e137 store <3 x i8> %s, ptr %p1138 ret void139}140 141define void @v4i8(ptr %p1, ptr %p2) {142; CHECK-SD-LABEL: v4i8:143; CHECK-SD: // %bb.0: // %entry144; CHECK-SD-NEXT: ldr s0, [x0]145; CHECK-SD-NEXT: ldr s1, [x1]146; CHECK-SD-NEXT: usubl v0.8h, v0.8b, v1.8b147; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b148; CHECK-SD-NEXT: str s0, [x0]149; CHECK-SD-NEXT: ret150;151; CHECK-GI-LABEL: v4i8:152; CHECK-GI: // %bb.0: // %entry153; CHECK-GI-NEXT: ldr w8, [x0]154; CHECK-GI-NEXT: ldr w9, [x1]155; CHECK-GI-NEXT: fmov s0, w8156; CHECK-GI-NEXT: fmov s1, w9157; CHECK-GI-NEXT: mov b2, v0.b[1]158; CHECK-GI-NEXT: mov b3, v1.b[1]159; CHECK-GI-NEXT: mov b4, v0.b[2]160; CHECK-GI-NEXT: mov b5, v0.b[3]161; CHECK-GI-NEXT: fmov w8, s2162; CHECK-GI-NEXT: mov b2, v1.b[2]163; CHECK-GI-NEXT: fmov w9, s3164; CHECK-GI-NEXT: mov b3, v1.b[3]165; CHECK-GI-NEXT: mov v0.h[1], w8166; CHECK-GI-NEXT: mov v1.h[1], w9167; CHECK-GI-NEXT: fmov w8, s4168; CHECK-GI-NEXT: fmov w9, s2169; CHECK-GI-NEXT: mov v0.h[2], w8170; CHECK-GI-NEXT: mov v1.h[2], w9171; CHECK-GI-NEXT: fmov w8, s5172; CHECK-GI-NEXT: fmov w9, s3173; CHECK-GI-NEXT: mov v0.h[3], w8174; CHECK-GI-NEXT: mov v1.h[3], w9175; CHECK-GI-NEXT: sub v0.4h, v0.4h, v1.4h176; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b177; CHECK-GI-NEXT: fmov w8, s0178; CHECK-GI-NEXT: str w8, [x0]179; CHECK-GI-NEXT: ret180entry:181 %d = load <4 x i8>, ptr %p1182 %e = load <4 x i8>, ptr %p2183 %s = sub <4 x i8> %d, %e184 store <4 x i8> %s, ptr %p1185 ret void186}187 188define <8 x i8> @v8i8(<8 x i8> %d, <8 x i8> %e) {189; CHECK-LABEL: v8i8:190; CHECK: // %bb.0: // %entry191; CHECK-NEXT: sub v0.8b, v0.8b, v1.8b192; CHECK-NEXT: ret193entry:194 %s = sub <8 x i8> %d, %e195 ret <8 x i8> %s196}197 198define <16 x i8> @v16i8(<16 x i8> %d, <16 x i8> %e) {199; CHECK-LABEL: v16i8:200; CHECK: // %bb.0: // %entry201; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b202; CHECK-NEXT: ret203entry:204 %s = sub <16 x i8> %d, %e205 ret <16 x i8> %s206}207 208define <32 x i8> @v32i8(<32 x i8> %d, <32 x i8> %e) {209; CHECK-SD-LABEL: v32i8:210; CHECK-SD: // %bb.0: // %entry211; CHECK-SD-NEXT: sub v1.16b, v1.16b, v3.16b212; CHECK-SD-NEXT: sub v0.16b, v0.16b, v2.16b213; CHECK-SD-NEXT: ret214;215; CHECK-GI-LABEL: v32i8:216; CHECK-GI: // %bb.0: // %entry217; CHECK-GI-NEXT: sub v0.16b, v0.16b, v2.16b218; CHECK-GI-NEXT: sub v1.16b, v1.16b, v3.16b219; CHECK-GI-NEXT: ret220entry:221 %s = sub <32 x i8> %d, %e222 ret <32 x i8> %s223}224 225define void @v2i16(ptr %p1, ptr %p2) {226; CHECK-SD-LABEL: v2i16:227; CHECK-SD: // %bb.0: // %entry228; CHECK-SD-NEXT: ldr s0, [x0]229; CHECK-SD-NEXT: ldr s1, [x1]230; CHECK-SD-NEXT: usubl v0.4s, v0.4h, v1.4h231; CHECK-SD-NEXT: mov s1, v0.s[1]232; CHECK-SD-NEXT: str h0, [x0]233; CHECK-SD-NEXT: str h1, [x0, #2]234; CHECK-SD-NEXT: ret235;236; CHECK-GI-LABEL: v2i16:237; CHECK-GI: // %bb.0: // %entry238; CHECK-GI-NEXT: ld1 { v0.h }[0], [x0]239; CHECK-GI-NEXT: ld1 { v1.h }[0], [x1]240; CHECK-GI-NEXT: ldr h2, [x0, #2]241; CHECK-GI-NEXT: ldr h3, [x1, #2]242; CHECK-GI-NEXT: mov v0.s[1], v2.s[0]243; CHECK-GI-NEXT: mov v1.s[1], v3.s[0]244; CHECK-GI-NEXT: sub v0.2s, v0.2s, v1.2s245; CHECK-GI-NEXT: mov s1, v0.s[1]246; CHECK-GI-NEXT: str h0, [x0]247; CHECK-GI-NEXT: str h1, [x0, #2]248; CHECK-GI-NEXT: ret249entry:250 %d = load <2 x i16>, ptr %p1251 %e = load <2 x i16>, ptr %p2252 %s = sub <2 x i16> %d, %e253 store <2 x i16> %s, ptr %p1254 ret void255}256 257define void @v3i16(ptr %p1, ptr %p2) {258; CHECK-SD-LABEL: v3i16:259; CHECK-SD: // %bb.0: // %entry260; CHECK-SD-NEXT: ldr d0, [x0]261; CHECK-SD-NEXT: ldr d1, [x1]262; CHECK-SD-NEXT: sub v0.4h, v0.4h, v1.4h263; CHECK-SD-NEXT: mov h1, v0.h[2]264; CHECK-SD-NEXT: str s0, [x0]265; CHECK-SD-NEXT: str h1, [x0, #4]266; CHECK-SD-NEXT: ret267;268; CHECK-GI-LABEL: v3i16:269; CHECK-GI: // %bb.0: // %entry270; CHECK-GI-NEXT: ldr d0, [x0]271; CHECK-GI-NEXT: ldr d1, [x1]272; CHECK-GI-NEXT: add x8, x0, #2273; CHECK-GI-NEXT: add x9, x0, #4274; CHECK-GI-NEXT: sub v0.4h, v0.4h, v1.4h275; CHECK-GI-NEXT: str h0, [x0]276; CHECK-GI-NEXT: st1 { v0.h }[1], [x8]277; CHECK-GI-NEXT: st1 { v0.h }[2], [x9]278; CHECK-GI-NEXT: ret279entry:280 %d = load <3 x i16>, ptr %p1281 %e = load <3 x i16>, ptr %p2282 %s = sub <3 x i16> %d, %e283 store <3 x i16> %s, ptr %p1284 ret void285}286 287define <4 x i16> @v4i16(<4 x i16> %d, <4 x i16> %e) {288; CHECK-LABEL: v4i16:289; CHECK: // %bb.0: // %entry290; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h291; CHECK-NEXT: ret292entry:293 %s = sub <4 x i16> %d, %e294 ret <4 x i16> %s295}296 297define <8 x i16> @v8i16(<8 x i16> %d, <8 x i16> %e) {298; CHECK-LABEL: v8i16:299; CHECK: // %bb.0: // %entry300; CHECK-NEXT: sub v0.8h, v0.8h, v1.8h301; CHECK-NEXT: ret302entry:303 %s = sub <8 x i16> %d, %e304 ret <8 x i16> %s305}306 307define <16 x i16> @v16i16(<16 x i16> %d, <16 x i16> %e) {308; CHECK-SD-LABEL: v16i16:309; CHECK-SD: // %bb.0: // %entry310; CHECK-SD-NEXT: sub v1.8h, v1.8h, v3.8h311; CHECK-SD-NEXT: sub v0.8h, v0.8h, v2.8h312; CHECK-SD-NEXT: ret313;314; CHECK-GI-LABEL: v16i16:315; CHECK-GI: // %bb.0: // %entry316; CHECK-GI-NEXT: sub v0.8h, v0.8h, v2.8h317; CHECK-GI-NEXT: sub v1.8h, v1.8h, v3.8h318; CHECK-GI-NEXT: ret319entry:320 %s = sub <16 x i16> %d, %e321 ret <16 x i16> %s322}323 324define <2 x i32> @v2i32(<2 x i32> %d, <2 x i32> %e) {325; CHECK-LABEL: v2i32:326; CHECK: // %bb.0: // %entry327; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s328; CHECK-NEXT: ret329entry:330 %s = sub <2 x i32> %d, %e331 ret <2 x i32> %s332}333 334define <3 x i32> @v3i32(<3 x i32> %d, <3 x i32> %e) {335; CHECK-LABEL: v3i32:336; CHECK: // %bb.0: // %entry337; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s338; CHECK-NEXT: ret339entry:340 %s = sub <3 x i32> %d, %e341 ret <3 x i32> %s342}343 344define <4 x i32> @v4i32(<4 x i32> %d, <4 x i32> %e) {345; CHECK-LABEL: v4i32:346; CHECK: // %bb.0: // %entry347; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s348; CHECK-NEXT: ret349entry:350 %s = sub <4 x i32> %d, %e351 ret <4 x i32> %s352}353 354define <8 x i32> @v8i32(<8 x i32> %d, <8 x i32> %e) {355; CHECK-SD-LABEL: v8i32:356; CHECK-SD: // %bb.0: // %entry357; CHECK-SD-NEXT: sub v1.4s, v1.4s, v3.4s358; CHECK-SD-NEXT: sub v0.4s, v0.4s, v2.4s359; CHECK-SD-NEXT: ret360;361; CHECK-GI-LABEL: v8i32:362; CHECK-GI: // %bb.0: // %entry363; CHECK-GI-NEXT: sub v0.4s, v0.4s, v2.4s364; CHECK-GI-NEXT: sub v1.4s, v1.4s, v3.4s365; CHECK-GI-NEXT: ret366entry:367 %s = sub <8 x i32> %d, %e368 ret <8 x i32> %s369}370 371define <2 x i64> @v2i64(<2 x i64> %d, <2 x i64> %e) {372; CHECK-LABEL: v2i64:373; CHECK: // %bb.0: // %entry374; CHECK-NEXT: sub v0.2d, v0.2d, v1.2d375; CHECK-NEXT: ret376entry:377 %s = sub <2 x i64> %d, %e378 ret <2 x i64> %s379}380 381define <3 x i64> @v3i64(<3 x i64> %d, <3 x i64> %e) {382; CHECK-SD-LABEL: v3i64:383; CHECK-SD: // %bb.0: // %entry384; CHECK-SD-NEXT: sub d0, d0, d3385; CHECK-SD-NEXT: sub d1, d1, d4386; CHECK-SD-NEXT: sub d2, d2, d5387; CHECK-SD-NEXT: ret388;389; CHECK-GI-LABEL: v3i64:390; CHECK-GI: // %bb.0: // %entry391; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0392; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q3393; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1394; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q4395; CHECK-GI-NEXT: fmov x8, d2396; CHECK-GI-NEXT: fmov x9, d5397; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]398; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]399; CHECK-GI-NEXT: sub x8, x8, x9400; CHECK-GI-NEXT: fmov d2, x8401; CHECK-GI-NEXT: sub v0.2d, v0.2d, v3.2d402; CHECK-GI-NEXT: mov d1, v0.d[1]403; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0404; CHECK-GI-NEXT: ret405entry:406 %s = sub <3 x i64> %d, %e407 ret <3 x i64> %s408}409 410define <4 x i64> @v4i64(<4 x i64> %d, <4 x i64> %e) {411; CHECK-SD-LABEL: v4i64:412; CHECK-SD: // %bb.0: // %entry413; CHECK-SD-NEXT: sub v1.2d, v1.2d, v3.2d414; CHECK-SD-NEXT: sub v0.2d, v0.2d, v2.2d415; CHECK-SD-NEXT: ret416;417; CHECK-GI-LABEL: v4i64:418; CHECK-GI: // %bb.0: // %entry419; CHECK-GI-NEXT: sub v0.2d, v0.2d, v2.2d420; CHECK-GI-NEXT: sub v1.2d, v1.2d, v3.2d421; CHECK-GI-NEXT: ret422entry:423 %s = sub <4 x i64> %d, %e424 ret <4 x i64> %s425}426 427define <2 x i128> @v2i128(<2 x i128> %d, <2 x i128> %e) {428; CHECK-LABEL: v2i128:429; CHECK: // %bb.0: // %entry430; CHECK-NEXT: subs x0, x0, x4431; CHECK-NEXT: sbc x1, x1, x5432; CHECK-NEXT: subs x2, x2, x6433; CHECK-NEXT: sbc x3, x3, x7434; CHECK-NEXT: ret435entry:436 %s = sub <2 x i128> %d, %e437 ret <2 x i128> %s438}439 440define <3 x i128> @v3i128(<3 x i128> %d, <3 x i128> %e) {441; CHECK-LABEL: v3i128:442; CHECK: // %bb.0: // %entry443; CHECK-NEXT: ldp x8, x9, [sp]444; CHECK-NEXT: subs x0, x0, x6445; CHECK-NEXT: ldp x10, x11, [sp, #16]446; CHECK-NEXT: sbc x1, x1, x7447; CHECK-NEXT: subs x2, x2, x8448; CHECK-NEXT: sbc x3, x3, x9449; CHECK-NEXT: subs x4, x4, x10450; CHECK-NEXT: sbc x5, x5, x11451; CHECK-NEXT: ret452entry:453 %s = sub <3 x i128> %d, %e454 ret <3 x i128> %s455}456 457define <4 x i128> @v4i128(<4 x i128> %d, <4 x i128> %e) {458; CHECK-SD-LABEL: v4i128:459; CHECK-SD: // %bb.0: // %entry460; CHECK-SD-NEXT: ldp x8, x9, [sp]461; CHECK-SD-NEXT: ldp x11, x10, [sp, #16]462; CHECK-SD-NEXT: ldp x13, x12, [sp, #32]463; CHECK-SD-NEXT: subs x0, x0, x8464; CHECK-SD-NEXT: sbc x1, x1, x9465; CHECK-SD-NEXT: ldp x8, x9, [sp, #48]466; CHECK-SD-NEXT: subs x2, x2, x11467; CHECK-SD-NEXT: sbc x3, x3, x10468; CHECK-SD-NEXT: subs x4, x4, x13469; CHECK-SD-NEXT: sbc x5, x5, x12470; CHECK-SD-NEXT: subs x6, x6, x8471; CHECK-SD-NEXT: sbc x7, x7, x9472; CHECK-SD-NEXT: ret473;474; CHECK-GI-LABEL: v4i128:475; CHECK-GI: // %bb.0: // %entry476; CHECK-GI-NEXT: ldp x8, x9, [sp]477; CHECK-GI-NEXT: ldp x10, x11, [sp, #16]478; CHECK-GI-NEXT: ldp x12, x13, [sp, #32]479; CHECK-GI-NEXT: subs x0, x0, x8480; CHECK-GI-NEXT: sbc x1, x1, x9481; CHECK-GI-NEXT: ldp x8, x9, [sp, #48]482; CHECK-GI-NEXT: subs x2, x2, x10483; CHECK-GI-NEXT: sbc x3, x3, x11484; CHECK-GI-NEXT: subs x4, x4, x12485; CHECK-GI-NEXT: sbc x5, x5, x13486; CHECK-GI-NEXT: subs x6, x6, x8487; CHECK-GI-NEXT: sbc x7, x7, x9488; CHECK-GI-NEXT: ret489entry:490 %s = sub <4 x i128> %d, %e491 ret <4 x i128> %s492}493