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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i64 @sub1_disguised_constant(i64 %x) {6; CHECK-SD-LABEL: sub1_disguised_constant:7; CHECK-SD: // %bb.0:8; CHECK-SD-NEXT: sub w8, w0, #19; CHECK-SD-NEXT: and w8, w0, w810; CHECK-SD-NEXT: and x0, x8, #0xffff11; CHECK-SD-NEXT: ret12;13; CHECK-GI-LABEL: sub1_disguised_constant:14; CHECK-GI: // %bb.0:15; CHECK-GI-NEXT: mov w8, #65535 // =0xffff16; CHECK-GI-NEXT: and x9, x0, #0xffff17; CHECK-GI-NEXT: add x8, x0, x818; CHECK-GI-NEXT: and x0, x9, x819; CHECK-GI-NEXT: ret20 %a1 = and i64 %x, 6553521 %a2 = add i64 %x, 6553522 %r = and i64 %a1, %a223 ret i64 %r24}25 26define i8 @masked_sub_i8(i8 %x) {27; CHECK-SD-LABEL: masked_sub_i8:28; CHECK-SD: // %bb.0:29; CHECK-SD-NEXT: mov w8, #5 // =0x530; CHECK-SD-NEXT: and w8, w0, w831; CHECK-SD-NEXT: eor w0, w8, #0x732; CHECK-SD-NEXT: ret33;34; CHECK-GI-LABEL: masked_sub_i8:35; CHECK-GI: // %bb.0:36; CHECK-GI-NEXT: mov w8, #5 // =0x537; CHECK-GI-NEXT: mov w9, #7 // =0x738; CHECK-GI-NEXT: and w8, w0, w839; CHECK-GI-NEXT: sub w0, w9, w840; CHECK-GI-NEXT: ret41 %a = and i8 %x, 542 %m = sub i8 7, %a43 ret i8 %m44}45 46; Borrow from the MSB is ok.47 48define i8 @masked_sub_high_bit_mask_i8(i8 %x) {49; CHECK-SD-LABEL: masked_sub_high_bit_mask_i8:50; CHECK-SD: // %bb.0:51; CHECK-SD-NEXT: mov w8, #-96 // =0xffffffa052; CHECK-SD-NEXT: and w8, w0, w853; CHECK-SD-NEXT: eor w0, w8, #0x3c54; CHECK-SD-NEXT: ret55;56; CHECK-GI-LABEL: masked_sub_high_bit_mask_i8:57; CHECK-GI: // %bb.0:58; CHECK-GI-NEXT: mov w8, #-96 // =0xffffffa059; CHECK-GI-NEXT: mov w9, #60 // =0x3c60; CHECK-GI-NEXT: and w8, w0, w861; CHECK-GI-NEXT: sub w0, w9, w862; CHECK-GI-NEXT: ret63 %maskx = and i8 %x, 160 ; 0b1010000064 %s = sub i8 60, %maskx ; 0b0011110065 ret i8 %s66}67 68define i8 @not_masked_sub_i8(i8 %x) {69; CHECK-LABEL: not_masked_sub_i8:70; CHECK: // %bb.0:71; CHECK-NEXT: mov w8, #7 // =0x772; CHECK-NEXT: and w9, w0, #0x873; CHECK-NEXT: sub w0, w8, w974; CHECK-NEXT: ret75 %a = and i8 %x, 876 %m = sub i8 7, %a77 ret i8 %m78}79 80define i32 @masked_sub_i32(i32 %x) {81; CHECK-SD-LABEL: masked_sub_i32:82; CHECK-SD: // %bb.0:83; CHECK-SD-NEXT: mov w8, #9 // =0x984; CHECK-SD-NEXT: and w8, w0, w885; CHECK-SD-NEXT: eor w0, w8, #0x1f86; CHECK-SD-NEXT: ret87;88; CHECK-GI-LABEL: masked_sub_i32:89; CHECK-GI: // %bb.0:90; CHECK-GI-NEXT: mov w8, #9 // =0x991; CHECK-GI-NEXT: mov w9, #31 // =0x1f92; CHECK-GI-NEXT: and w8, w0, w893; CHECK-GI-NEXT: sub w0, w9, w894; CHECK-GI-NEXT: ret95 %a = and i32 %x, 996 %m = sub i32 31, %a97 ret i32 %m98}99 100define <4 x i32> @masked_sub_v4i32(<4 x i32> %x) {101; CHECK-SD-LABEL: masked_sub_v4i32:102; CHECK-SD: // %bb.0:103; CHECK-SD-NEXT: movi v1.4s, #42104; CHECK-SD-NEXT: movi v2.4s, #1, msl #8105; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b106; CHECK-SD-NEXT: eor v0.16b, v0.16b, v2.16b107; CHECK-SD-NEXT: ret108;109; CHECK-GI-LABEL: masked_sub_v4i32:110; CHECK-GI: // %bb.0:111; CHECK-GI-NEXT: movi v1.4s, #42112; CHECK-GI-NEXT: movi v2.4s, #1, msl #8113; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b114; CHECK-GI-NEXT: sub v0.4s, v2.4s, v0.4s115; CHECK-GI-NEXT: ret116 %a = and <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>117 %m = sub <4 x i32> <i32 511, i32 511, i32 511, i32 511>, %a118 ret <4 x i32> %m119}120 121define i32 @pr137254(i32 %0) {122; CHECK-LABEL: pr137254:123; CHECK: // %bb.0:124; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000125; CHECK-NEXT: add w8, w0, w8126; CHECK-NEXT: cmp w8, #0127; CHECK-NEXT: cset w0, gt128; CHECK-NEXT: ret129 %2 = sub nsw i32 %0, -2147483648130 %3 = icmp sgt i32 %2, 0131 %4 = select i1 %3, i32 1, i32 0132 ret i32 %4133}134