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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6;7; SABA8;9 10define <vscale x 16 x i8> @saba_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {11; CHECK-LABEL: saba_b:12; CHECK: // %bb.0:13; CHECK-NEXT: saba z0.b, z1.b, z2.b14; CHECK-NEXT: ret15 %b.sext = sext <vscale x 16 x i8> %b to <vscale x 16 x i16>16 %c.sext = sext <vscale x 16 x i8> %c to <vscale x 16 x i16>17 %sub = sub <vscale x 16 x i16> %b.sext, %c.sext18 %abs = call <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16> %sub, i1 true)19 %trunc = trunc <vscale x 16 x i16> %abs to <vscale x 16 x i8>20 %add = add <vscale x 16 x i8> %a, %trunc21 ret <vscale x 16 x i8> %add22}23 24define <vscale x 16 x i8> @saba_b_promoted_ops(<vscale x 16 x i8> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c) #0 {25; CHECK-LABEL: saba_b_promoted_ops:26; CHECK: // %bb.0:27; CHECK-NEXT: ptrue p2.b28; CHECK-NEXT: mov z1.b, #1 // =0x129; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b30; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b31; CHECK-NEXT: ret32 %b.sext = sext <vscale x 16 x i1> %b to <vscale x 16 x i8>33 %c.sext = sext <vscale x 16 x i1> %c to <vscale x 16 x i8>34 %sub = sub <vscale x 16 x i8> %b.sext, %c.sext35 %abs = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %sub, i1 true)36 %add = add <vscale x 16 x i8> %a, %abs37 ret <vscale x 16 x i8> %add38}39 40define <vscale x 16 x i8> @saba_b_from_sabd(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {41; CHECK-LABEL: saba_b_from_sabd:42; CHECK: // %bb.0:43; CHECK-NEXT: saba z0.b, z1.b, z2.b44; CHECK-NEXT: ret45 %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)46 %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sabd.u.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)47 %3 = add <vscale x 16 x i8> %2, %a48 ret <vscale x 16 x i8> %349}50 51define <vscale x 16 x i8> @saba_b_from_sabd_u(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {52; CHECK-LABEL: saba_b_from_sabd_u:53; CHECK: // %bb.0:54; CHECK-NEXT: saba z0.b, z1.b, z2.b55; CHECK-NEXT: ret56 %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.sabd.u.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)57 %2 = add <vscale x 16 x i8> %1, %a58 ret <vscale x 16 x i8> %259}60 61define <vscale x 8 x i16> @saba_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) #0 {62; CHECK-LABEL: saba_h:63; CHECK: // %bb.0:64; CHECK-NEXT: saba z0.h, z1.h, z2.h65; CHECK-NEXT: ret66 %b.sext = sext <vscale x 8 x i16> %b to <vscale x 8 x i32>67 %c.sext = sext <vscale x 8 x i16> %c to <vscale x 8 x i32>68 %sub = sub <vscale x 8 x i32> %b.sext, %c.sext69 %abs = call <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32> %sub, i1 true)70 %trunc = trunc <vscale x 8 x i32> %abs to <vscale x 8 x i16>71 %add = add <vscale x 8 x i16> %a, %trunc72 ret <vscale x 8 x i16> %add73}74 75define <vscale x 8 x i16> @saba_h_promoted_ops(<vscale x 8 x i16> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c) #0 {76; CHECK-LABEL: saba_h_promoted_ops:77; CHECK: // %bb.0:78; CHECK-NEXT: ptrue p0.h79; CHECK-NEXT: sxtb z2.h, p0/m, z2.h80; CHECK-NEXT: sxtb z1.h, p0/m, z1.h81; CHECK-NEXT: saba z0.h, z1.h, z2.h82; CHECK-NEXT: ret83 %b.sext = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>84 %c.sext = sext <vscale x 8 x i8> %c to <vscale x 8 x i16>85 %sub = sub <vscale x 8 x i16> %b.sext, %c.sext86 %abs = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %sub, i1 true)87 %add = add <vscale x 8 x i16> %a, %abs88 ret <vscale x 8 x i16> %add89}90 91define <vscale x 8 x i16> @saba_h_from_sabd(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) #0 {92; CHECK-LABEL: saba_h_from_sabd:93; CHECK: // %bb.0:94; CHECK-NEXT: saba z0.h, z1.h, z2.h95; CHECK-NEXT: ret96 %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)97 %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sabd.u.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)98 %3 = add <vscale x 8 x i16> %2, %a99 ret <vscale x 8 x i16> %3100}101 102define <vscale x 8 x i16> @saba_h_from_sabd_u(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) #0 {103; CHECK-LABEL: saba_h_from_sabd_u:104; CHECK: // %bb.0:105; CHECK-NEXT: saba z0.h, z1.h, z2.h106; CHECK-NEXT: ret107 %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sabd.u.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)108 %2 = add <vscale x 8 x i16> %1, %a109 ret <vscale x 8 x i16> %2110}111 112define <vscale x 4 x i32> @saba_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {113; CHECK-LABEL: saba_s:114; CHECK: // %bb.0:115; CHECK-NEXT: saba z0.s, z1.s, z2.s116; CHECK-NEXT: ret117 %b.sext = sext <vscale x 4 x i32> %b to <vscale x 4 x i64>118 %c.sext = sext <vscale x 4 x i32> %c to <vscale x 4 x i64>119 %sub = sub <vscale x 4 x i64> %b.sext, %c.sext120 %abs = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %sub, i1 true)121 %trunc = trunc <vscale x 4 x i64> %abs to <vscale x 4 x i32>122 %add = add <vscale x 4 x i32> %a, %trunc123 ret <vscale x 4 x i32> %add124}125 126define <vscale x 4 x i32> @saba_s_promoted_ops(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c) #0 {127; CHECK-LABEL: saba_s_promoted_ops:128; CHECK: // %bb.0:129; CHECK-NEXT: ptrue p0.s130; CHECK-NEXT: sxth z2.s, p0/m, z2.s131; CHECK-NEXT: sxth z1.s, p0/m, z1.s132; CHECK-NEXT: saba z0.s, z1.s, z2.s133; CHECK-NEXT: ret134 %b.sext = sext <vscale x 4 x i16> %b to <vscale x 4 x i32>135 %c.sext = sext <vscale x 4 x i16> %c to <vscale x 4 x i32>136 %sub = sub <vscale x 4 x i32> %b.sext, %c.sext137 %abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)138 %add = add <vscale x 4 x i32> %a, %abs139 ret <vscale x 4 x i32> %add140}141 142define <vscale x 4 x i32> @saba_s_from_sabd(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {143; CHECK-LABEL: saba_s_from_sabd:144; CHECK: // %bb.0:145; CHECK-NEXT: saba z0.s, z1.s, z2.s146; CHECK-NEXT: ret147 %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)148 %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.u.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)149 %3 = add <vscale x 4 x i32> %2, %a150 ret <vscale x 4 x i32> %3151}152 153define <vscale x 4 x i32> @saba_s_from_sabd_u(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {154; CHECK-LABEL: saba_s_from_sabd_u:155; CHECK: // %bb.0:156; CHECK-NEXT: saba z0.s, z1.s, z2.s157; CHECK-NEXT: ret158 %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)159 %2 = add <vscale x 4 x i32> %1, %a160 ret <vscale x 4 x i32> %2161}162 163define <vscale x 2 x i64> @saba_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) #0 {164; CHECK-LABEL: saba_d:165; CHECK: // %bb.0:166; CHECK-NEXT: saba z0.d, z1.d, z2.d167; CHECK-NEXT: ret168 %b.sext = sext <vscale x 2 x i64> %b to <vscale x 2 x i128>169 %c.sext = sext <vscale x 2 x i64> %c to <vscale x 2 x i128>170 %sub = sub <vscale x 2 x i128> %b.sext, %c.sext171 %abs = call <vscale x 2 x i128> @llvm.abs.nxv2i128(<vscale x 2 x i128> %sub, i1 true)172 %trunc = trunc <vscale x 2 x i128> %abs to <vscale x 2 x i64>173 %add = add <vscale x 2 x i64> %a, %trunc174 ret <vscale x 2 x i64> %add175}176 177define <vscale x 2 x i64> @saba_d_promoted_ops(<vscale x 2 x i64> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c) #0 {178; CHECK-LABEL: saba_d_promoted_ops:179; CHECK: // %bb.0:180; CHECK-NEXT: ptrue p0.d181; CHECK-NEXT: sxtw z2.d, p0/m, z2.d182; CHECK-NEXT: sxtw z1.d, p0/m, z1.d183; CHECK-NEXT: saba z0.d, z1.d, z2.d184; CHECK-NEXT: ret185 %b.sext = sext <vscale x 2 x i32> %b to <vscale x 2 x i64>186 %c.sext = sext <vscale x 2 x i32> %c to <vscale x 2 x i64>187 %sub = sub <vscale x 2 x i64> %b.sext, %c.sext188 %abs = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %sub, i1 true)189 %add = add <vscale x 2 x i64> %a, %abs190 ret <vscale x 2 x i64> %add191}192 193define <vscale x 2 x i64> @saba_d_from_sabd(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) #0 {194; CHECK-LABEL: saba_d_from_sabd:195; CHECK: // %bb.0:196; CHECK-NEXT: saba z0.d, z1.d, z2.d197; CHECK-NEXT: ret198 %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)199 %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sabd.u.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)200 %3 = add <vscale x 2 x i64> %2, %a201 ret <vscale x 2 x i64> %3202}203 204define <vscale x 2 x i64> @saba_d_from_sabd_u(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) #0 {205; CHECK-LABEL: saba_d_from_sabd_u:206; CHECK: // %bb.0:207; CHECK-NEXT: saba z0.d, z1.d, z2.d208; CHECK-NEXT: ret209 %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sabd.u.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)210 %2 = add <vscale x 2 x i64> %1, %a211 ret <vscale x 2 x i64> %2212}213 214;215; UABA216;217 218define <vscale x 16 x i8> @uaba_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {219; CHECK-LABEL: uaba_b:220; CHECK: // %bb.0:221; CHECK-NEXT: uaba z0.b, z1.b, z2.b222; CHECK-NEXT: ret223 %b.zext = zext <vscale x 16 x i8> %b to <vscale x 16 x i16>224 %c.zext = zext <vscale x 16 x i8> %c to <vscale x 16 x i16>225 %sub = sub <vscale x 16 x i16> %b.zext, %c.zext226 %abs = call <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16> %sub, i1 true)227 %trunc = trunc <vscale x 16 x i16> %abs to <vscale x 16 x i8>228 %add = add <vscale x 16 x i8> %a, %trunc229 ret <vscale x 16 x i8> %add230}231 232define <vscale x 16 x i8> @uaba_b_promoted_ops(<vscale x 16 x i8> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c) #0 {233; CHECK-LABEL: uaba_b_promoted_ops:234; CHECK: // %bb.0:235; CHECK-NEXT: ptrue p2.b236; CHECK-NEXT: mov z1.b, #1 // =0x1237; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b238; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b239; CHECK-NEXT: ret240 %b.zext = zext <vscale x 16 x i1> %b to <vscale x 16 x i8>241 %c.zext = zext <vscale x 16 x i1> %c to <vscale x 16 x i8>242 %sub = sub <vscale x 16 x i8> %b.zext, %c.zext243 %abs = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %sub, i1 true)244 %add = add <vscale x 16 x i8> %a, %abs245 ret <vscale x 16 x i8> %add246}247 248define <vscale x 16 x i8> @uaba_b_from_uabd(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {249; CHECK-LABEL: uaba_b_from_uabd:250; CHECK: // %bb.0:251; CHECK-NEXT: uaba z0.b, z1.b, z2.b252; CHECK-NEXT: ret253 %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)254 %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uabd.u.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)255 %3 = add <vscale x 16 x i8> %2, %a256 ret <vscale x 16 x i8> %3257}258 259define <vscale x 16 x i8> @uaba_b_from_uabd_u(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {260; CHECK-LABEL: uaba_b_from_uabd_u:261; CHECK: // %bb.0:262; CHECK-NEXT: uaba z0.b, z1.b, z2.b263; CHECK-NEXT: ret264 %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.uabd.u.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)265 %2 = add <vscale x 16 x i8> %1, %a266 ret <vscale x 16 x i8> %2267}268 269define <vscale x 8 x i16> @uaba_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) #0 {270; CHECK-LABEL: uaba_h:271; CHECK: // %bb.0:272; CHECK-NEXT: uaba z0.h, z1.h, z2.h273; CHECK-NEXT: ret274 %b.zext = zext <vscale x 8 x i16> %b to <vscale x 8 x i32>275 %c.zext = zext <vscale x 8 x i16> %c to <vscale x 8 x i32>276 %sub = sub <vscale x 8 x i32> %b.zext, %c.zext277 %abs = call <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32> %sub, i1 true)278 %trunc = trunc <vscale x 8 x i32> %abs to <vscale x 8 x i16>279 %add = add <vscale x 8 x i16> %a, %trunc280 ret <vscale x 8 x i16> %add281}282 283define <vscale x 8 x i16> @uaba_h_promoted_ops(<vscale x 8 x i16> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c) #0 {284; CHECK-LABEL: uaba_h_promoted_ops:285; CHECK: // %bb.0:286; CHECK-NEXT: and z2.h, z2.h, #0xff287; CHECK-NEXT: and z1.h, z1.h, #0xff288; CHECK-NEXT: uaba z0.h, z1.h, z2.h289; CHECK-NEXT: ret290 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>291 %c.zext = zext <vscale x 8 x i8> %c to <vscale x 8 x i16>292 %sub = sub <vscale x 8 x i16> %b.zext, %c.zext293 %abs = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %sub, i1 true)294 %add = add <vscale x 8 x i16> %a, %abs295 ret <vscale x 8 x i16> %add296}297 298define <vscale x 8 x i16> @uaba_h_from_uabd(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) #0 {299; CHECK-LABEL: uaba_h_from_uabd:300; CHECK: // %bb.0:301; CHECK-NEXT: uaba z0.h, z1.h, z2.h302; CHECK-NEXT: ret303 %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)304 %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uabd.u.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)305 %3 = add <vscale x 8 x i16> %2, %a306 ret <vscale x 8 x i16> %3307}308 309define <vscale x 8 x i16> @uaba_h_from_uabd_u(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) #0 {310; CHECK-LABEL: uaba_h_from_uabd_u:311; CHECK: // %bb.0:312; CHECK-NEXT: uaba z0.h, z1.h, z2.h313; CHECK-NEXT: ret314 %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uabd.u.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)315 %2 = add <vscale x 8 x i16> %1, %a316 ret <vscale x 8 x i16> %2317}318 319define <vscale x 4 x i32> @uaba_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {320; CHECK-LABEL: uaba_s:321; CHECK: // %bb.0:322; CHECK-NEXT: uaba z0.s, z1.s, z2.s323; CHECK-NEXT: ret324 %b.zext = zext <vscale x 4 x i32> %b to <vscale x 4 x i64>325 %c.zext = zext <vscale x 4 x i32> %c to <vscale x 4 x i64>326 %sub = sub <vscale x 4 x i64> %b.zext, %c.zext327 %abs = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %sub, i1 true)328 %trunc = trunc <vscale x 4 x i64> %abs to <vscale x 4 x i32>329 %add = add <vscale x 4 x i32> %a, %trunc330 ret <vscale x 4 x i32> %add331}332 333define <vscale x 4 x i32> @uaba_s_promoted_ops(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c) #0 {334; CHECK-LABEL: uaba_s_promoted_ops:335; CHECK: // %bb.0:336; CHECK-NEXT: and z2.s, z2.s, #0xffff337; CHECK-NEXT: and z1.s, z1.s, #0xffff338; CHECK-NEXT: uaba z0.s, z1.s, z2.s339; CHECK-NEXT: ret340 %b.zext = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>341 %c.zext = zext <vscale x 4 x i16> %c to <vscale x 4 x i32>342 %sub = sub <vscale x 4 x i32> %b.zext, %c.zext343 %abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)344 %add = add <vscale x 4 x i32> %a, %abs345 ret <vscale x 4 x i32> %add346}347 348define <vscale x 4 x i32> @uaba_s_from_uabd(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {349; CHECK-LABEL: uaba_s_from_uabd:350; CHECK: // %bb.0:351; CHECK-NEXT: uaba z0.s, z1.s, z2.s352; CHECK-NEXT: ret353 %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)354 %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.u.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)355 %3 = add <vscale x 4 x i32> %2, %a356 ret <vscale x 4 x i32> %3357}358 359define <vscale x 4 x i32> @uaba_s_from_uabd_u(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {360; CHECK-LABEL: uaba_s_from_uabd_u:361; CHECK: // %bb.0:362; CHECK-NEXT: uaba z0.s, z1.s, z2.s363; CHECK-NEXT: ret364 %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)365 %2 = add <vscale x 4 x i32> %1, %a366 ret <vscale x 4 x i32> %2367}368 369define <vscale x 2 x i64> @uaba_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) #0 {370; CHECK-LABEL: uaba_d:371; CHECK: // %bb.0:372; CHECK-NEXT: uaba z0.d, z1.d, z2.d373; CHECK-NEXT: ret374 %b.zext = zext <vscale x 2 x i64> %b to <vscale x 2 x i128>375 %c.zext = zext <vscale x 2 x i64> %c to <vscale x 2 x i128>376 %sub = sub <vscale x 2 x i128> %b.zext, %c.zext377 %abs = call <vscale x 2 x i128> @llvm.abs.nxv2i128(<vscale x 2 x i128> %sub, i1 true)378 %trunc = trunc <vscale x 2 x i128> %abs to <vscale x 2 x i64>379 %add = add <vscale x 2 x i64> %a, %trunc380 ret <vscale x 2 x i64> %add381}382 383define <vscale x 2 x i64> @uaba_d_promoted_ops(<vscale x 2 x i64> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c) #0 {384; CHECK-LABEL: uaba_d_promoted_ops:385; CHECK: // %bb.0:386; CHECK-NEXT: and z2.d, z2.d, #0xffffffff387; CHECK-NEXT: and z1.d, z1.d, #0xffffffff388; CHECK-NEXT: uaba z0.d, z1.d, z2.d389; CHECK-NEXT: ret390 %b.zext = zext <vscale x 2 x i32> %b to <vscale x 2 x i64>391 %c.zext = zext <vscale x 2 x i32> %c to <vscale x 2 x i64>392 %sub = sub <vscale x 2 x i64> %b.zext, %c.zext393 %abs = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %sub, i1 true)394 %add = add <vscale x 2 x i64> %a, %abs395 ret <vscale x 2 x i64> %add396}397 398define <vscale x 2 x i64> @uaba_d_from_uabd(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) #0 {399; CHECK-LABEL: uaba_d_from_uabd:400; CHECK: // %bb.0:401; CHECK-NEXT: uaba z0.d, z1.d, z2.d402; CHECK-NEXT: ret403 %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)404 %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uabd.u.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)405 %3 = add <vscale x 2 x i64> %2, %a406 ret <vscale x 2 x i64> %3407}408 409define <vscale x 2 x i64> @uaba_d_from_uabd_u(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) #0 {410; CHECK-LABEL: uaba_d_from_uabd_u:411; CHECK: // %bb.0:412; CHECK-NEXT: uaba z0.d, z1.d, z2.d413; CHECK-NEXT: ret414 %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uabd.u.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)415 %2 = add <vscale x 2 x i64> %1, %a416 ret <vscale x 2 x i64> %2417}418 419; A variant of uaba_s but with the add operands switched.420define <vscale x 4 x i32> @uaba_s_commutative(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {421; CHECK-LABEL: uaba_s_commutative:422; CHECK: // %bb.0:423; CHECK-NEXT: uaba z0.s, z1.s, z2.s424; CHECK-NEXT: ret425 %b.zext = zext <vscale x 4 x i32> %b to <vscale x 4 x i64>426 %c.zext = zext <vscale x 4 x i32> %c to <vscale x 4 x i64>427 %sub = sub <vscale x 4 x i64> %b.zext, %c.zext428 %abs = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %sub, i1 true)429 %trunc = trunc <vscale x 4 x i64> %abs to <vscale x 4 x i32>430 %add = add <vscale x 4 x i32> %trunc, %a431 ret <vscale x 4 x i32> %add432}433 434declare <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8>, i1)435declare <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16>, i1)436declare <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16>, i1)437declare <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32>, i1)438declare <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32>, i1)439declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)440declare <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64>, i1)441declare <vscale x 2 x i128> @llvm.abs.nxv2i128(<vscale x 2 x i128>, i1)442 443declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)444declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)445declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)446declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)447 448declare <vscale x 16 x i8> @llvm.aarch64.sve.sabd.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)449declare <vscale x 8 x i16> @llvm.aarch64.sve.sabd.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)450declare <vscale x 4 x i32> @llvm.aarch64.sve.sabd.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)451declare <vscale x 2 x i64> @llvm.aarch64.sve.sabd.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)452 453declare <vscale x 16 x i8> @llvm.aarch64.sve.uabd.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)454declare <vscale x 8 x i16> @llvm.aarch64.sve.uabd.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)455declare <vscale x 4 x i32> @llvm.aarch64.sve.uabd.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)456declare <vscale x 2 x i64> @llvm.aarch64.sve.uabd.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)457 458attributes #0 = { "target-features"="+neon,+sve,+sve2" }459