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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6;7; ADR8; Tests adr z0.s, [z0.s, z0.s, lsl #<1,2,3>]9; Other formats are tested in llvm/test/CodeGen/AArch64/sve-gep.ll10;11 12define <vscale x 4 x i32> @adr_32bit_lsl1(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {13; CHECK-LABEL: adr_32bit_lsl1:14; CHECK: // %bb.0:15; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #1]16; CHECK-NEXT: ret17 %offset = shl <vscale x 4 x i32> %idx, splat (i32 1)18 %address = add <vscale x 4 x i32> %base, %offset19 ret <vscale x 4 x i32> %address20}21 22define <vscale x 4 x i32> @adr_32bit_lsl2(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {23; CHECK-LABEL: adr_32bit_lsl2:24; CHECK: // %bb.0:25; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #2]26; CHECK-NEXT: ret27 %offset = shl <vscale x 4 x i32> %idx, splat (i32 2)28 %address = add <vscale x 4 x i32> %base, %offset29 ret <vscale x 4 x i32> %address30}31 32define <vscale x 4 x i32> @adr_32bit_lsl3(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {33; CHECK-LABEL: adr_32bit_lsl3:34; CHECK: // %bb.0:35; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #3]36; CHECK-NEXT: ret37 %offset = shl <vscale x 4 x i32> %idx, splat (i32 3)38 %address = add <vscale x 4 x i32> %base, %offset39 ret <vscale x 4 x i32> %address40}41 42attributes #0 = { "target-features"="+sve" }43