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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mattr=+sve -combiner-disabled < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; Ensure we don't try to represent sdiv-by-one using ARSD.7define <16 x i16> @sdiv_by_one_v16i16(<16 x i16> %a) vscale_range(2,2) {8; CHECK-LABEL: sdiv_by_one_v16i16:9; CHECK: // %bb.0:10; CHECK-NEXT: ptrue p0.h11; CHECK-NEXT: adrp x8, .LCPI0_012; CHECK-NEXT: add x8, x8, :lo12:.LCPI0_013; CHECK-NEXT: // kill: def $q1 killed $q1 def $z114; CHECK-NEXT: // kill: def $q0 killed $q0 def $z015; CHECK-NEXT: ld1h { z2.h }, p0/z, [x8]16; CHECK-NEXT: sunpklo z0.s, z0.h17; CHECK-NEXT: sunpklo z1.s, z1.h18; CHECK-NEXT: ptrue p0.s19; CHECK-NEXT: sunpklo z3.s, z2.h20; CHECK-NEXT: ext z2.b, z2.b, z2.b, #1621; CHECK-NEXT: sunpklo z2.s, z2.h22; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z3.s23; CHECK-NEXT: sdiv z1.s, p0/m, z1.s, z2.s24; CHECK-NEXT: ptrue p0.h, vl825; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h26; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h27; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h28; CHECK-NEXT: movprfx z1, z029; CHECK-NEXT: ext z1.b, z1.b, z0.b, #1630; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z031; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z132; CHECK-NEXT: ret33 %res = sdiv <16 x i16> %a, splat(i16 1)34 ret <16 x i16> %res35}36 37; Ensure we don't try to represent sdiv-by-one using ARSD.38define <vscale x 8 x i16> @sdiv_by_one_nxv8i16(<vscale x 8 x i16> %a) {39; CHECK-LABEL: sdiv_by_one_nxv8i16:40; CHECK: // %bb.0:41; CHECK-NEXT: mov z1.h, #1 // =0x142; CHECK-NEXT: sunpkhi z2.s, z0.h43; CHECK-NEXT: sunpklo z0.s, z0.h44; CHECK-NEXT: ptrue p0.s45; CHECK-NEXT: sunpkhi z3.s, z1.h46; CHECK-NEXT: sunpklo z1.s, z1.h47; CHECK-NEXT: sdiv z2.s, p0/m, z2.s, z3.s48; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s49; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h50; CHECK-NEXT: ret51 %res = sdiv <vscale x 8 x i16> %a, splat(i16 1)52 ret <vscale x 8 x i16> %res53}54