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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+sve | FileCheck %s3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5target triple = "aarch64-unknown-linux-gnu"6 7; Make sure callers set up the arguments correctly - tests AArch64ISelLowering::LowerCALL8 9define float @foo1(ptr %x0, ptr %x1, ptr %x2) nounwind {10; CHECK-LABEL: foo1:11; CHECK: // %bb.0: // %entry12; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill13; CHECK-NEXT: addvl sp, sp, #-414; CHECK-NEXT: ptrue p0.b15; CHECK-NEXT: fmov s0, #1.0000000016; CHECK-NEXT: ld4d { z1.d - z4.d }, p0/z, [x0]17; CHECK-NEXT: mov x0, sp18; CHECK-NEXT: ld4d { z16.d - z19.d }, p0/z, [x1]19; CHECK-NEXT: ld1d { z5.d }, p0/z, [x2]20; CHECK-NEXT: str z19, [sp, #3, mul vl]21; CHECK-NEXT: str z18, [sp, #2, mul vl]22; CHECK-NEXT: str z17, [sp, #1, mul vl]23; CHECK-NEXT: str z16, [sp]24; CHECK-NEXT: bl callee125; CHECK-NEXT: addvl sp, sp, #426; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload27; CHECK-NEXT: ret28entry:29 %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)30 %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)31 %2 = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1> %1, ptr %x0)32 %3 = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1> %1, ptr %x1)33 %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1> %1, ptr %x2)34 %5 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 035 %6 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 136 %7 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 237 %8 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 338 %9 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> poison, <vscale x 2 x double> %5, i64 0)39 %10 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %9, <vscale x 2 x double> %6, i64 2)40 %11 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %10, <vscale x 2 x double> %7, i64 4)41 %12 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %11, <vscale x 2 x double> %8, i64 6)42 %13 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %3, 043 %14 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %3, 144 %15 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %3, 245 %16 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %3, 346 %17 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> poison, <vscale x 2 x double> %13, i64 0)47 %18 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %17, <vscale x 2 x double> %14, i64 2)48 %19 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %18, <vscale x 2 x double> %15, i64 4)49 %20 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %19, <vscale x 2 x double> %16, i64 6)50 %call = call float @callee1(float 1.000000e+00, <vscale x 8 x double> %12, <vscale x 8 x double> %20, <vscale x 2 x double> %4)51 ret float %call52}53 54define float @foo2(ptr %x0, ptr %x1) nounwind {55; CHECK-LABEL: foo2:56; CHECK: // %bb.0: // %entry57; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill58; CHECK-NEXT: sub sp, sp, #1659; CHECK-NEXT: addvl sp, sp, #-460; CHECK-NEXT: ptrue p0.b61; CHECK-NEXT: fmov s0, #1.0000000062; CHECK-NEXT: add x8, sp, #1663; CHECK-NEXT: mov w2, #2 // =0x264; CHECK-NEXT: mov w3, #3 // =0x365; CHECK-NEXT: mov w4, #4 // =0x466; CHECK-NEXT: ld4d { z1.d - z4.d }, p0/z, [x0]67; CHECK-NEXT: mov w0, wzr68; CHECK-NEXT: mov w5, #5 // =0x569; CHECK-NEXT: mov w6, #6 // =0x670; CHECK-NEXT: mov w7, #7 // =0x771; CHECK-NEXT: ld4d { z16.d - z19.d }, p0/z, [x1]72; CHECK-NEXT: mov w1, #1 // =0x173; CHECK-NEXT: str x8, [sp]74; CHECK-NEXT: str z19, [x8, #3, mul vl]75; CHECK-NEXT: str z18, [x8, #2, mul vl]76; CHECK-NEXT: str z17, [x8, #1, mul vl]77; CHECK-NEXT: str z16, [x8]78; CHECK-NEXT: bl callee279; CHECK-NEXT: addvl sp, sp, #480; CHECK-NEXT: add sp, sp, #1681; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload82; CHECK-NEXT: ret83entry:84 %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)85 %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)86 %2 = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1> %1, ptr %x0)87 %3 = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1> %1, ptr %x1)88 %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 089 %5 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 190 %6 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 291 %7 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 392 %8 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> poison, <vscale x 2 x double> %4, i64 0)93 %9 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %8, <vscale x 2 x double> %5, i64 2)94 %10 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %9, <vscale x 2 x double> %6, i64 4)95 %11 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %10, <vscale x 2 x double> %7, i64 6)96 %12 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %3, 097 %13 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %3, 198 %14 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %3, 299 %15 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %3, 3100 %16 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> poison, <vscale x 2 x double> %12, i64 0)101 %17 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %16, <vscale x 2 x double> %13, i64 2)102 %18 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %17, <vscale x 2 x double> %14, i64 4)103 %19 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %18, <vscale x 2 x double> %15, i64 6)104 %call = call float @callee2(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, float 1.000000e+00, <vscale x 8 x double> %11, <vscale x 8 x double> %19)105 ret float %call106}107 108define float @foo3(ptr %x0, ptr %x1, ptr %x2) nounwind {109; CHECK-LABEL: foo3:110; CHECK: // %bb.0: // %entry111; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill112; CHECK-NEXT: addvl sp, sp, #-3113; CHECK-NEXT: ptrue p0.b114; CHECK-NEXT: fmov s0, #1.00000000115; CHECK-NEXT: fmov s1, #2.00000000116; CHECK-NEXT: ld4d { z2.d - z5.d }, p0/z, [x0]117; CHECK-NEXT: mov x0, sp118; CHECK-NEXT: ld3d { z16.d - z18.d }, p0/z, [x1]119; CHECK-NEXT: ld1d { z6.d }, p0/z, [x2]120; CHECK-NEXT: str z18, [sp, #2, mul vl]121; CHECK-NEXT: str z17, [sp, #1, mul vl]122; CHECK-NEXT: str z16, [sp]123; CHECK-NEXT: bl callee3124; CHECK-NEXT: addvl sp, sp, #3125; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload126; CHECK-NEXT: ret127entry:128 %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)129 %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)130 %2 = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1> %1, ptr %x0)131 %3 = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.aarch64.sve.ld3.sret.nxv2f64(<vscale x 2 x i1> %1, ptr %x1)132 %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1> %1, ptr %x2)133 %5 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 0134 %6 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 1135 %7 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 2136 %8 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %2, 3137 %9 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> poison, <vscale x 2 x double> %5, i64 0)138 %10 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %9, <vscale x 2 x double> %6, i64 2)139 %11 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %10, <vscale x 2 x double> %7, i64 4)140 %12 = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double> %11, <vscale x 2 x double> %8, i64 6)141 %13 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} %3, 0142 %14 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %3, 1143 %15 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %3, 2144 %16 = call <vscale x 6 x double> @llvm.vector.insert.nxv6f64.nx2f64(<vscale x 6 x double> poison, <vscale x 2 x double> %13, i64 0)145 %17 = call <vscale x 6 x double> @llvm.vector.insert.nxv6f64.nx2f64(<vscale x 6 x double> %16 , <vscale x 2 x double> %14, i64 2)146 %18 = call <vscale x 6 x double> @llvm.vector.insert.nxv6f64.nx2f64(<vscale x 6 x double> %17 , <vscale x 2 x double> %15, i64 4)147 %call = call float @callee3(float 1.000000e+00, float 2.000000e+00, <vscale x 8 x double> %12, <vscale x 6 x double> %18, <vscale x 2 x double> %4)148 ret float %call149}150 151; Make sure callees read the arguments correctly - tests AArch64ISelLowering::LowerFormalArguments152 153define double @foo4(double %x0, ptr %ptr1, ptr %ptr2, ptr %ptr3, <vscale x 8 x double> %x1, <vscale x 8 x double> %x2, <vscale x 2 x double> %x3) nounwind {154; CHECK-LABEL: foo4:155; CHECK: // %bb.0: // %entry156; CHECK-NEXT: ldr z6, [x3, #1, mul vl]157; CHECK-NEXT: ldr z7, [x3]158; CHECK-NEXT: ldr z24, [x3, #3, mul vl]159; CHECK-NEXT: ldr z25, [x3, #2, mul vl]160; CHECK-NEXT: str z4, [x0, #3, mul vl]161; CHECK-NEXT: str z3, [x0, #2, mul vl]162; CHECK-NEXT: str z2, [x0, #1, mul vl]163; CHECK-NEXT: str z1, [x0]164; CHECK-NEXT: str z25, [x1, #2, mul vl]165; CHECK-NEXT: str z24, [x1, #3, mul vl]166; CHECK-NEXT: str z7, [x1]167; CHECK-NEXT: str z6, [x1, #1, mul vl]168; CHECK-NEXT: str z5, [x2]169; CHECK-NEXT: ret170entry:171 store volatile <vscale x 8 x double> %x1, ptr %ptr1172 store volatile <vscale x 8 x double> %x2, ptr %ptr2173 store volatile <vscale x 2 x double> %x3, ptr %ptr3174 ret double %x0175}176 177define double @foo5(i32 %i0, i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, ptr %ptr1, ptr %ptr2, double %x0, <vscale x 8 x double> %x1, <vscale x 8 x double> %x2) nounwind {178; CHECK-LABEL: foo5:179; CHECK: // %bb.0: // %entry180; CHECK-NEXT: ldr x8, [sp]181; CHECK-NEXT: ldr z5, [x8, #1, mul vl]182; CHECK-NEXT: ldr z6, [x8]183; CHECK-NEXT: ldr z7, [x8, #3, mul vl]184; CHECK-NEXT: ldr z24, [x8, #2, mul vl]185; CHECK-NEXT: str z4, [x6, #3, mul vl]186; CHECK-NEXT: str z3, [x6, #2, mul vl]187; CHECK-NEXT: str z2, [x6, #1, mul vl]188; CHECK-NEXT: str z1, [x6]189; CHECK-NEXT: str z24, [x7, #2, mul vl]190; CHECK-NEXT: str z7, [x7, #3, mul vl]191; CHECK-NEXT: str z6, [x7]192; CHECK-NEXT: str z5, [x7, #1, mul vl]193; CHECK-NEXT: ret194entry:195 store volatile <vscale x 8 x double> %x1, ptr %ptr1196 store volatile <vscale x 8 x double> %x2, ptr %ptr2197 ret double %x0198}199 200define double @foo6(double %x0, double %x1, ptr %ptr1, ptr %ptr2, <vscale x 8 x double> %x2, <vscale x 6 x double> %x3) nounwind {201; CHECK-LABEL: foo6:202; CHECK: // %bb.0: // %entry203; CHECK-NEXT: ldr z1, [x2]204; CHECK-NEXT: ldr z6, [x2, #2, mul vl]205; CHECK-NEXT: ldr z7, [x2, #1, mul vl]206; CHECK-NEXT: str z5, [x0, #3, mul vl]207; CHECK-NEXT: str z4, [x0, #2, mul vl]208; CHECK-NEXT: str z3, [x0, #1, mul vl]209; CHECK-NEXT: str z2, [x0]210; CHECK-NEXT: str z7, [x1, #1, mul vl]211; CHECK-NEXT: str z6, [x1, #2, mul vl]212; CHECK-NEXT: str z1, [x1]213; CHECK-NEXT: ret214entry:215 store volatile <vscale x 8 x double> %x2, ptr %ptr1216 store volatile <vscale x 6 x double> %x3, ptr %ptr2217 ret double %x0218}219 220; Use AAVPCS, SVE register in z0 - z7 used221 222define void @aavpcs1(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32 %s6, <vscale x 4 x i32> %s7, <vscale x 4 x i32> %s8, <vscale x 4 x i32> %s9, <vscale x 4 x i32> %s10, <vscale x 4 x i32> %s11, <vscale x 4 x i32> %s12, <vscale x 4 x i32> %s13, <vscale x 4 x i32> %s14, <vscale x 4 x i32> %s15, <vscale x 4 x i32> %s16, ptr %ptr) nounwind {223; CHECK-LABEL: aavpcs1:224; CHECK: // %bb.0: // %entry225; CHECK-NEXT: ldp x8, x9, [sp]226; CHECK-NEXT: ldr z24, [x7]227; CHECK-NEXT: ldr z3, [x8]228; CHECK-NEXT: str z0, [x9]229; CHECK-NEXT: str z1, [x9]230; CHECK-NEXT: str z2, [x9]231; CHECK-NEXT: str z4, [x9]232; CHECK-NEXT: str z5, [x9]233; CHECK-NEXT: str z6, [x9]234; CHECK-NEXT: str z7, [x9]235; CHECK-NEXT: str z24, [x9]236; CHECK-NEXT: str z3, [x9]237; CHECK-NEXT: ret238entry:239 store volatile <vscale x 4 x i32> %s7, ptr %ptr240 store volatile <vscale x 4 x i32> %s8, ptr %ptr241 store volatile <vscale x 4 x i32> %s9, ptr %ptr242 store volatile <vscale x 4 x i32> %s11, ptr %ptr243 store volatile <vscale x 4 x i32> %s12, ptr %ptr244 store volatile <vscale x 4 x i32> %s13, ptr %ptr245 store volatile <vscale x 4 x i32> %s14, ptr %ptr246 store volatile <vscale x 4 x i32> %s15, ptr %ptr247 store volatile <vscale x 4 x i32> %s16, ptr %ptr248 ret void249}250 251; Use AAVPCS, SVE register in z0 - z7 used252 253define void @aavpcs2(float %s0, float %s1, float %s2, float %s3, float %s4, float %s5, float %s6, <vscale x 4 x float> %s7, <vscale x 4 x float> %s8, <vscale x 4 x float> %s9, <vscale x 4 x float> %s10, <vscale x 4 x float> %s11, <vscale x 4 x float> %s12,<vscale x 4 x float> %s13,<vscale x 4 x float> %s14,<vscale x 4 x float> %s15,<vscale x 4 x float> %s16,ptr %ptr) nounwind {254; CHECK-LABEL: aavpcs2:255; CHECK: // %bb.0: // %entry256; CHECK-NEXT: ldp x8, x9, [sp]257; CHECK-NEXT: ldr z1, [x7]258; CHECK-NEXT: ldr z2, [x0]259; CHECK-NEXT: ldr z3, [x6]260; CHECK-NEXT: ldr z4, [x5]261; CHECK-NEXT: ldr z5, [x1]262; CHECK-NEXT: ldr z6, [x4]263; CHECK-NEXT: ldr z24, [x3]264; CHECK-NEXT: ldr z0, [x8]265; CHECK-NEXT: str z7, [x9]266; CHECK-NEXT: str z2, [x9]267; CHECK-NEXT: str z5, [x9]268; CHECK-NEXT: str z24, [x9]269; CHECK-NEXT: str z6, [x9]270; CHECK-NEXT: str z4, [x9]271; CHECK-NEXT: str z3, [x9]272; CHECK-NEXT: str z1, [x9]273; CHECK-NEXT: str z0, [x9]274; CHECK-NEXT: ret275entry:276 store volatile <vscale x 4 x float> %s7, ptr %ptr277 store volatile <vscale x 4 x float> %s8, ptr %ptr278 store volatile <vscale x 4 x float> %s9, ptr %ptr279 store volatile <vscale x 4 x float> %s11, ptr %ptr280 store volatile <vscale x 4 x float> %s12, ptr %ptr281 store volatile <vscale x 4 x float> %s13, ptr %ptr282 store volatile <vscale x 4 x float> %s14, ptr %ptr283 store volatile <vscale x 4 x float> %s15, ptr %ptr284 store volatile <vscale x 4 x float> %s16, ptr %ptr285 ret void286}287 288; Use AAVPCS, no SVE register in z0 - z7 used (floats occupy z0 - z7) but predicate arg is used289 290define void @aavpcs3(float %s0, float %s1, float %s2, float %s3, float %s4, float %s5, float %s6, float %s7, <vscale x 4 x float> %s8, <vscale x 4 x float> %s9, <vscale x 4 x float> %s10, <vscale x 4 x float> %s11, <vscale x 4 x float> %s12, <vscale x 4 x float> %s13, <vscale x 4 x float> %s14, <vscale x 4 x float> %s15, <vscale x 4 x float> %s16, <vscale x 4 x float> %s17, <vscale x 16 x i1> %p0, ptr %ptr) nounwind {291; CHECK-LABEL: aavpcs3:292; CHECK: // %bb.0: // %entry293; CHECK-NEXT: ldr x8, [sp]294; CHECK-NEXT: ldr z0, [x0]295; CHECK-NEXT: ldr z2, [x7]296; CHECK-NEXT: ldr z3, [x1]297; CHECK-NEXT: ldr z4, [x6]298; CHECK-NEXT: ldr z5, [x5]299; CHECK-NEXT: ldr z1, [x8]300; CHECK-NEXT: ldr z6, [x2]301; CHECK-NEXT: ldr z7, [x4]302; CHECK-NEXT: ldr z24, [x3]303; CHECK-NEXT: ldr x8, [sp, #16]304; CHECK-NEXT: str z0, [x8]305; CHECK-NEXT: str z3, [x8]306; CHECK-NEXT: str z6, [x8]307; CHECK-NEXT: str z24, [x8]308; CHECK-NEXT: str z7, [x8]309; CHECK-NEXT: str z5, [x8]310; CHECK-NEXT: str z4, [x8]311; CHECK-NEXT: str z2, [x8]312; CHECK-NEXT: str z1, [x8]313; CHECK-NEXT: ret314entry:315 store volatile <vscale x 4 x float> %s8, ptr %ptr316 store volatile <vscale x 4 x float> %s9, ptr %ptr317 store volatile <vscale x 4 x float> %s10, ptr %ptr318 store volatile <vscale x 4 x float> %s11, ptr %ptr319 store volatile <vscale x 4 x float> %s12, ptr %ptr320 store volatile <vscale x 4 x float> %s13, ptr %ptr321 store volatile <vscale x 4 x float> %s14, ptr %ptr322 store volatile <vscale x 4 x float> %s15, ptr %ptr323 store volatile <vscale x 4 x float> %s16, ptr %ptr324 ret void325}326 327; use AAVPCS, SVE register in z0 - z7 used (i32s dont occupy z0 - z7)328 329define void @aavpcs4(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32 %s6, i32 %s7, <vscale x 4 x i32> %s8, <vscale x 4 x i32> %s9, <vscale x 4 x i32> %s10, <vscale x 4 x i32> %s11, <vscale x 4 x i32> %s12, <vscale x 4 x i32> %s13, <vscale x 4 x i32> %s14, <vscale x 4 x i32> %s15, <vscale x 4 x i32> %s16, <vscale x 4 x i32> %s17, ptr %ptr) nounwind {330; CHECK-LABEL: aavpcs4:331; CHECK: // %bb.0: // %entry332; CHECK-NEXT: ldr x8, [sp]333; CHECK-NEXT: ldr x9, [sp, #16]334; CHECK-NEXT: ldr z24, [x8]335; CHECK-NEXT: str z0, [x9]336; CHECK-NEXT: str z1, [x9]337; CHECK-NEXT: str z2, [x9]338; CHECK-NEXT: str z3, [x9]339; CHECK-NEXT: str z4, [x9]340; CHECK-NEXT: str z5, [x9]341; CHECK-NEXT: str z6, [x9]342; CHECK-NEXT: str z7, [x9]343; CHECK-NEXT: str z24, [x9]344; CHECK-NEXT: ret345entry:346 store volatile <vscale x 4 x i32> %s8, ptr %ptr347 store volatile <vscale x 4 x i32> %s9, ptr %ptr348 store volatile <vscale x 4 x i32> %s10, ptr %ptr349 store volatile <vscale x 4 x i32> %s11, ptr %ptr350 store volatile <vscale x 4 x i32> %s12, ptr %ptr351 store volatile <vscale x 4 x i32> %s13, ptr %ptr352 store volatile <vscale x 4 x i32> %s14, ptr %ptr353 store volatile <vscale x 4 x i32> %s15, ptr %ptr354 store volatile <vscale x 4 x i32> %s16, ptr %ptr355 ret void356}357 358; Use AAVPCS, SVE register used in return359 360define <vscale x 4 x float> @aavpcs5(float %s0, float %s1, float %s2, float %s3, float %s4, float %s5, float %s6, float %s7, <vscale x 4 x float> %s8, <vscale x 4 x float> %s9, <vscale x 4 x float> %s10, <vscale x 4 x float> %s11, <vscale x 4 x float> %s12, <vscale x 4 x float> %s13, <vscale x 4 x float> %s14, <vscale x 4 x float> %s15, <vscale x 4 x float> %s16, <vscale x 4 x float> %s17, ptr %ptr) nounwind {361; CHECK-LABEL: aavpcs5:362; CHECK: // %bb.0: // %entry363; CHECK-NEXT: ldr x8, [sp]364; CHECK-NEXT: ldr z0, [x0]365; CHECK-NEXT: ldr z2, [x7]366; CHECK-NEXT: ldr z3, [x1]367; CHECK-NEXT: ldr z4, [x6]368; CHECK-NEXT: ldr z5, [x5]369; CHECK-NEXT: ldr z1, [x8]370; CHECK-NEXT: ldr z6, [x2]371; CHECK-NEXT: ldr z7, [x4]372; CHECK-NEXT: ldr z24, [x3]373; CHECK-NEXT: ldr x8, [sp, #16]374; CHECK-NEXT: str z0, [x8]375; CHECK-NEXT: str z3, [x8]376; CHECK-NEXT: str z6, [x8]377; CHECK-NEXT: str z24, [x8]378; CHECK-NEXT: str z7, [x8]379; CHECK-NEXT: str z5, [x8]380; CHECK-NEXT: str z4, [x8]381; CHECK-NEXT: str z2, [x8]382; CHECK-NEXT: str z1, [x8]383; CHECK-NEXT: ret384entry:385 store volatile <vscale x 4 x float> %s8, ptr %ptr386 store volatile <vscale x 4 x float> %s9, ptr %ptr387 store volatile <vscale x 4 x float> %s10, ptr %ptr388 store volatile <vscale x 4 x float> %s11, ptr %ptr389 store volatile <vscale x 4 x float> %s12, ptr %ptr390 store volatile <vscale x 4 x float> %s13, ptr %ptr391 store volatile <vscale x 4 x float> %s14, ptr %ptr392 store volatile <vscale x 4 x float> %s15, ptr %ptr393 store volatile <vscale x 4 x float> %s16, ptr %ptr394 ret <vscale x 4 x float> %s8395}396 397define void @aapcs1(float %s0, float %s1, float %s2, float %s3, float %s4, float %s5, float %s6, float %s7, <vscale x 4 x float> %s8, <vscale x 4 x float> %s9, <vscale x 4 x float> %s10, <vscale x 4 x float> %s11, <vscale x 4 x float> %s12, <vscale x 4 x float> %s13, <vscale x 4 x float> %s14, <vscale x 4 x float> %s15, <vscale x 4 x float> %s16, <vscale x 4 x float> %s17, ptr %ptr) nounwind {398; CHECK-LABEL: aapcs1:399; CHECK: // %bb.0: // %entry400; CHECK-NEXT: ldr x8, [sp]401; CHECK-NEXT: ldr z0, [x0]402; CHECK-NEXT: ldr z2, [x7]403; CHECK-NEXT: ldr z3, [x1]404; CHECK-NEXT: ldr z4, [x6]405; CHECK-NEXT: ldr z5, [x5]406; CHECK-NEXT: ldr z1, [x8]407; CHECK-NEXT: ldr z6, [x2]408; CHECK-NEXT: ldr z7, [x4]409; CHECK-NEXT: ldr z16, [x3]410; CHECK-NEXT: ldr x8, [sp, #16]411; CHECK-NEXT: str z0, [x8]412; CHECK-NEXT: str z3, [x8]413; CHECK-NEXT: str z6, [x8]414; CHECK-NEXT: str z16, [x8]415; CHECK-NEXT: str z7, [x8]416; CHECK-NEXT: str z5, [x8]417; CHECK-NEXT: str z4, [x8]418; CHECK-NEXT: str z2, [x8]419; CHECK-NEXT: str z1, [x8]420; CHECK-NEXT: ret421entry:422 store volatile <vscale x 4 x float> %s8, ptr %ptr423 store volatile <vscale x 4 x float> %s9, ptr %ptr424 store volatile <vscale x 4 x float> %s10, ptr %ptr425 store volatile <vscale x 4 x float> %s11, ptr %ptr426 store volatile <vscale x 4 x float> %s12, ptr %ptr427 store volatile <vscale x 4 x float> %s13, ptr %ptr428 store volatile <vscale x 4 x float> %s14, ptr %ptr429 store volatile <vscale x 4 x float> %s15, ptr %ptr430 store volatile <vscale x 4 x float> %s16, ptr %ptr431 ret void432}433 434declare void @non_sve_callee_high_range(float %f0, float %f1, float %f2, float %f3, float %f4, float %f5, float %f6, float %f7, <vscale x 4 x float> %v0, <vscale x 4 x float> %v1)435 436define void @non_sve_caller_non_sve_callee_high_range() {437; CHECK-LABEL: non_sve_caller_non_sve_callee_high_range:438; CHECK: // %bb.0:439; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill440; CHECK-NEXT: addvl sp, sp, #-2441; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x40, 0x1e, 0x22 // sp + 16 + 16 * VG442; CHECK-NEXT: .cfi_offset w30, -8443; CHECK-NEXT: .cfi_offset w29, -16444; CHECK-NEXT: movi d0, #0000000000000000445; CHECK-NEXT: fmov s1, #1.00000000446; CHECK-NEXT: addvl x0, sp, #1447; CHECK-NEXT: fmov s2, #2.00000000448; CHECK-NEXT: fmov s3, #3.00000000449; CHECK-NEXT: mov x1, sp450; CHECK-NEXT: fmov s4, #4.00000000451; CHECK-NEXT: fmov s5, #5.00000000452; CHECK-NEXT: fmov s6, #6.00000000453; CHECK-NEXT: fmov s7, #7.00000000454; CHECK-NEXT: bl non_sve_callee_high_range455; CHECK-NEXT: addvl sp, sp, #2456; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload457; CHECK-NEXT: ret458 call void @non_sve_callee_high_range(float 0.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, <vscale x 4 x float> undef, <vscale x 4 x float> undef)459 ret void460}461 462define void @non_sve_caller_high_range_non_sve_callee_high_range(float %f0, float %f1, float %f2, float %f3, float %f4, float %f5, float %f6, float %f7, <vscale x 4 x float> %v0, <vscale x 4 x float> %v1) {463; CHECK-LABEL: non_sve_caller_high_range_non_sve_callee_high_range:464; CHECK: // %bb.0:465; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill466; CHECK-NEXT: addvl sp, sp, #-2467; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x40, 0x1e, 0x22 // sp + 16 + 16 * VG468; CHECK-NEXT: .cfi_offset w30, -8469; CHECK-NEXT: .cfi_offset w29, -16470; CHECK-NEXT: movi d0, #0000000000000000471; CHECK-NEXT: ldr z16, [x0]472; CHECK-NEXT: ldr z17, [x1]473; CHECK-NEXT: fmov s1, #1.00000000474; CHECK-NEXT: fmov s2, #2.00000000475; CHECK-NEXT: fmov s3, #3.00000000476; CHECK-NEXT: fmov s4, #4.00000000477; CHECK-NEXT: fmov s5, #5.00000000478; CHECK-NEXT: addvl x0, sp, #1479; CHECK-NEXT: fmov s6, #6.00000000480; CHECK-NEXT: fmov s7, #7.00000000481; CHECK-NEXT: mov x1, sp482; CHECK-NEXT: str z17, [sp]483; CHECK-NEXT: str z16, [sp, #1, mul vl]484; CHECK-NEXT: bl non_sve_callee_high_range485; CHECK-NEXT: addvl sp, sp, #2486; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload487; CHECK-NEXT: ret488 call void @non_sve_callee_high_range(float 0.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, <vscale x 4 x float> %v0, <vscale x 4 x float> %v1)489 ret void490}491 492define <vscale x 4 x float> @sve_caller_non_sve_callee_high_range(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1) {493; CHECK-LABEL: sve_caller_non_sve_callee_high_range:494; CHECK: // %bb.0:495; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill496; CHECK-NEXT: addvl sp, sp, #-18497; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Spill498; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Spill499; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Spill500; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill501; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill502; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill503; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill504; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill505; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill506; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill507; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill508; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill509; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill510; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill511; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill512; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill513; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill514; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill515; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill516; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill517; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill518; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill519; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill520; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill521; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill522; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill523; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill524; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill525; CHECK-NEXT: addvl sp, sp, #-3526; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0xa8, 0x01, 0x1e, 0x22 // sp + 16 + 168 * VG527; CHECK-NEXT: .cfi_offset w30, -8528; CHECK-NEXT: .cfi_offset w29, -16529; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16530; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16531; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16532; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16533; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16534; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16535; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16536; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16537; CHECK-NEXT: mov z25.d, z0.d538; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill539; CHECK-NEXT: movi d0, #0000000000000000540; CHECK-NEXT: mov z24.d, z1.d541; CHECK-NEXT: fmov s1, #1.00000000542; CHECK-NEXT: addvl x0, sp, #2543; CHECK-NEXT: fmov s2, #2.00000000544; CHECK-NEXT: fmov s3, #3.00000000545; CHECK-NEXT: addvl x1, sp, #1546; CHECK-NEXT: fmov s4, #4.00000000547; CHECK-NEXT: fmov s5, #5.00000000548; CHECK-NEXT: str z25, [sp, #2, mul vl]549; CHECK-NEXT: fmov s6, #6.00000000550; CHECK-NEXT: fmov s7, #7.00000000551; CHECK-NEXT: str z24, [sp, #1, mul vl]552; CHECK-NEXT: bl non_sve_callee_high_range553; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload554; CHECK-NEXT: addvl sp, sp, #3555; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload556; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload557; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload558; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload559; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload560; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload561; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload562; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload563; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload564; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload565; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload566; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload567; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload568; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload569; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload570; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload571; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Reload572; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Reload573; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Reload574; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload575; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload576; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload577; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload578; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload579; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload580; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload581; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload582; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload583; CHECK-NEXT: addvl sp, sp, #18584; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload585; CHECK-NEXT: ret586 call void @non_sve_callee_high_range(float 0.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, <vscale x 4 x float> %v0, <vscale x 4 x float> %v1)587 ret <vscale x 4 x float> %v0588}589 590define <vscale x 4 x float> @sve_ret_caller_non_sve_callee_high_range() {591; CHECK-LABEL: sve_ret_caller_non_sve_callee_high_range:592; CHECK: // %bb.0:593; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill594; CHECK-NEXT: addvl sp, sp, #-18595; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Spill596; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Spill597; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Spill598; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill599; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill600; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill601; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill602; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill603; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill604; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill605; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill606; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill607; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill608; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill609; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill610; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill611; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill612; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill613; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill614; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill615; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill616; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill617; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill618; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill619; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill620; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill621; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill622; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill623; CHECK-NEXT: addvl sp, sp, #-2624; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0xa0, 0x01, 0x1e, 0x22 // sp + 16 + 160 * VG625; CHECK-NEXT: .cfi_offset w30, -8626; CHECK-NEXT: .cfi_offset w29, -16627; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16628; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16629; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16630; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16631; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16632; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16633; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16634; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16635; CHECK-NEXT: movi d0, #0000000000000000636; CHECK-NEXT: fmov s1, #1.00000000637; CHECK-NEXT: addvl x0, sp, #1638; CHECK-NEXT: fmov s2, #2.00000000639; CHECK-NEXT: fmov s3, #3.00000000640; CHECK-NEXT: mov x1, sp641; CHECK-NEXT: fmov s4, #4.00000000642; CHECK-NEXT: fmov s5, #5.00000000643; CHECK-NEXT: fmov s6, #6.00000000644; CHECK-NEXT: fmov s7, #7.00000000645; CHECK-NEXT: bl non_sve_callee_high_range646; CHECK-NEXT: addvl sp, sp, #2647; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload648; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload649; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload650; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload651; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload652; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload653; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload654; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload655; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload656; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload657; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload658; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload659; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload660; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload661; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload662; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload663; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Reload664; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Reload665; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Reload666; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload667; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload668; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload669; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload670; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload671; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload672; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload673; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload674; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload675; CHECK-NEXT: addvl sp, sp, #18676; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload677; CHECK-NEXT: ret678 call void @non_sve_callee_high_range(float 0.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, <vscale x 4 x float> undef, <vscale x 4 x float> undef)679 ret <vscale x 4 x float> undef680}681 682declare void @func_f8_and_v0_passed_via_memory(float %f0, float %f1, float %f2, float %f3, float %f4, float %f5, float %f6, float %f7, float %f8, <vscale x 4 x float> %v0)683define void @verify_all_operands_are_initialised() {684; CHECK-LABEL: verify_all_operands_are_initialised:685; CHECK: // %bb.0:686; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill687; CHECK-NEXT: sub sp, sp, #16688; CHECK-NEXT: addvl sp, sp, #-1689; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x20, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 32 + 8 * VG690; CHECK-NEXT: .cfi_offset w30, -8691; CHECK-NEXT: .cfi_offset w29, -16692; CHECK-NEXT: movi d0, #0000000000000000693; CHECK-NEXT: fmov z16.s, #9.00000000694; CHECK-NEXT: mov w8, #1090519040 // =0x41000000695; CHECK-NEXT: fmov s1, #1.00000000696; CHECK-NEXT: fmov s2, #2.00000000697; CHECK-NEXT: str w8, [sp]698; CHECK-NEXT: fmov s3, #3.00000000699; CHECK-NEXT: fmov s4, #4.00000000700; CHECK-NEXT: add x0, sp, #16701; CHECK-NEXT: fmov s5, #5.00000000702; CHECK-NEXT: fmov s6, #6.00000000703; CHECK-NEXT: add x8, sp, #16704; CHECK-NEXT: fmov s7, #7.00000000705; CHECK-NEXT: str z16, [x8]706; CHECK-NEXT: bl func_f8_and_v0_passed_via_memory707; CHECK-NEXT: addvl sp, sp, #1708; CHECK-NEXT: add sp, sp, #16709; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload710; CHECK-NEXT: ret711 call void @func_f8_and_v0_passed_via_memory(float 0.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, <vscale x 4 x float> splat (float 9.000000e+00))712 ret void713}714 715declare float @callee1(float, <vscale x 8 x double>, <vscale x 8 x double>, <vscale x 2 x double>)716declare float @callee2(i32, i32, i32, i32, i32, i32, i32, i32, float, <vscale x 8 x double>, <vscale x 8 x double>)717declare float @callee3(float, float, <vscale x 8 x double>, <vscale x 6 x double>, <vscale x 2 x double>)718 719declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)720declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)721declare {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1>, ptr)722declare {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.aarch64.sve.ld3.sret.nxv2f64(<vscale x 2 x i1>, ptr)723declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1>, ptr)724declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)725declare <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nx2f64(<vscale x 8 x double>, <vscale x 2 x double>, i64)726declare <vscale x 6 x double> @llvm.vector.insert.nxv6f64.nx2f64(<vscale x 6 x double>, <vscale x 2 x double>, i64)727