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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s2; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s --check-prefix=DARWIN3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=prologepilog < %s | FileCheck %s --check-prefix=CHECKCSR4; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+sve -stop-after=prologepilog < %s | FileCheck %s --check-prefix=CHECKCSR5 6; CHECK-LABEL: name: nosve_signature7; DARWIN-LABEL: name: nosve_signature8define i32 @nosve_signature() nounwind {9 ret i32 4210}11 12; CHECK-LABEL: name: sve_signature_ret_vec13; DARWIN-LABEL: name: sve_signature_ret_vec14define <vscale x 4 x i32> @sve_signature_ret_vec() nounwind {15 ret <vscale x 4 x i32> undef16}17 18; CHECK-LABEL: name: sve_signature_ret_pred19; DARWIN-LABEL: name: sve_signature_ret_pred20define <vscale x 4 x i1> @sve_signature_ret_pred() nounwind {21 ret <vscale x 4 x i1> undef22}23 24; CHECK-LABEL: name: sve_signature_arg_vec25; DARWIN-LABEL: name: sve_signature_arg_vec26define void @sve_signature_arg_vec(<vscale x 4 x i32> %arg) nounwind {27 ret void28}29 30; CHECK-LABEL: name: sve_signature_arg_pred31; DARWIN-LABEL: name: sve_signature_arg_pred32define void @sve_signature_arg_pred(<vscale x 4 x i1> %arg) nounwind {33 ret void34}35 36; CHECK-LABEL: name: caller_nosve_signature37; CHECK: BL @nosve_signature, csr_aarch64_aapcs38; DARWIN-LABEL: name: caller_nosve_signature39; DARWIN: BL @nosve_signature, csr_darwin_aarch64_aapcs40define i32 @caller_nosve_signature() nounwind {41 %res = call i32 @nosve_signature()42 ret i32 %res43}44 45; CHECK-LABEL: name: caller_nosve_signature_fastcc46; CHECK: BL @nosve_signature, csr_aarch64_aapcs47; DARWIN-LABEL: name: caller_nosve_signature_fastcc48; DARWIN: BL @nosve_signature, csr_darwin_aarch64_aapcs49define i32 @caller_nosve_signature_fastcc() nounwind {50 %res = call fastcc i32 @nosve_signature()51 ret i32 %res52}53 54; CHECK-LABEL: name: sve_signature_ret_vec_caller55; CHECK: BL @sve_signature_ret_vec, csr_aarch64_sve_aapcs56; DARWIN-LABEL: name: sve_signature_ret_vec_caller57; DARWIN: BL @sve_signature_ret_vec, csr_darwin_aarch64_sve_aapcs58define <vscale x 4 x i32> @sve_signature_ret_vec_caller() nounwind {59 %res = call <vscale x 4 x i32> @sve_signature_ret_vec()60 ret <vscale x 4 x i32> %res61}62 63; CHECK-LABEL: name: sve_signature_ret_vec_caller_fastcc64; CHECK: BL @sve_signature_ret_vec, csr_aarch64_sve_aapcs65; DARWIN-LABEL: name: sve_signature_ret_vec_caller_fastcc66; DARWIN: BL @sve_signature_ret_vec, csr_darwin_aarch64_sve_aapcs67define <vscale x 4 x i32> @sve_signature_ret_vec_caller_fastcc() nounwind {68 %res = call fastcc <vscale x 4 x i32> @sve_signature_ret_vec()69 ret <vscale x 4 x i32> %res70}71 72; CHECK-LABEL: name: sve_signature_ret_pred_caller73; CHECK: BL @sve_signature_ret_pred, csr_aarch64_sve_aapcs74; DARWIN-LABEL: name: sve_signature_ret_pred_caller75; DARWIN: BL @sve_signature_ret_pred, csr_darwin_aarch64_sve_aapcs76define <vscale x 4 x i1> @sve_signature_ret_pred_caller() nounwind {77 %res = call <vscale x 4 x i1> @sve_signature_ret_pred()78 ret <vscale x 4 x i1> %res79}80 81; CHECK-LABEL: name: sve_signature_ret_pred_caller_fastcc82; CHECK: BL @sve_signature_ret_pred, csr_aarch64_sve_aapcs83; DARWIN-LABEL: name: sve_signature_ret_pred_caller_fastcc84; DARWIN: BL @sve_signature_ret_pred, csr_darwin_aarch64_sve_aapcs85define <vscale x 4 x i1> @sve_signature_ret_pred_caller_fastcc() nounwind {86 %res = call fastcc <vscale x 4 x i1> @sve_signature_ret_pred()87 ret <vscale x 4 x i1> %res88}89 90; CHECK-LABEL: name: sve_signature_arg_vec_caller91; CHECK: BL @sve_signature_arg_vec, csr_aarch64_sve_aapcs92; DARWIN-LABEL: name: sve_signature_arg_vec_caller93; DARWIN: BL @sve_signature_arg_vec, csr_darwin_aarch64_sve_aapcs94define void @sve_signature_arg_vec_caller(<vscale x 4 x i32> %arg) nounwind {95 call void @sve_signature_arg_vec(<vscale x 4 x i32> %arg)96 ret void97}98 99; CHECK-LABEL: name: sve_signature_arg_vec_caller_fastcc100; CHECK: BL @sve_signature_arg_vec, csr_aarch64_sve_aapcs101; DARWIN-LABEL: name: sve_signature_arg_vec_caller_fastcc102; DARWIN: BL @sve_signature_arg_vec, csr_darwin_aarch64_sve_aapcs103define void @sve_signature_arg_vec_caller_fastcc(<vscale x 4 x i32> %arg) nounwind {104 call fastcc void @sve_signature_arg_vec(<vscale x 4 x i32> %arg)105 ret void106}107 108; CHECK-LABEL: name: sve_signature_arg_pred_caller109; CHECK: BL @sve_signature_arg_pred, csr_aarch64_sve_aapcs110; DARWIN-LABEL: name: sve_signature_arg_pred_caller111; DARWIN: BL @sve_signature_arg_pred, csr_darwin_aarch64_sve_aapcs112define void @sve_signature_arg_pred_caller(<vscale x 4 x i1> %arg) nounwind {113 call void @sve_signature_arg_pred(<vscale x 4 x i1> %arg)114 ret void115}116 117; CHECK-LABEL: name: sve_signature_arg_pred_caller_fastcc118; CHECK: BL @sve_signature_arg_pred, csr_aarch64_sve_aapcs119; DARWIN-LABEL: name: sve_signature_arg_pred_caller_fastcc120; DARWIN: BL @sve_signature_arg_pred, csr_darwin_aarch64_sve_aapcs121define void @sve_signature_arg_pred_caller_fastcc(<vscale x 4 x i1> %arg) nounwind {122 call fastcc void @sve_signature_arg_pred(<vscale x 4 x i1> %arg)123 ret void124}125 126; CHECK-LABEL: name: sve_signature_many_arg_vec127; CHECK: [[RES:%[0-9]+]]:zpr = COPY $z7128; CHECK: $z0 = COPY [[RES]]129; CHECK: RET_ReallyLR implicit $z0130; DARWIN-LABEL: name: sve_signature_many_arg_vec131; DARWIN: [[RES:%[0-9]+]]:zpr = COPY $z7132; DARWIN: $z0 = COPY [[RES]]133; DARWIN: RET_ReallyLR implicit $z0134define <vscale x 4 x i32> @sve_signature_many_arg_vec(<vscale x 4 x i32> %arg1, <vscale x 4 x i32> %arg2, <vscale x 4 x i32> %arg3, <vscale x 4 x i32> %arg4, <vscale x 4 x i32> %arg5, <vscale x 4 x i32> %arg6, <vscale x 4 x i32> %arg7, <vscale x 4 x i32> %arg8) nounwind {135 ret <vscale x 4 x i32> %arg8136}137 138; CHECK-LABEL: name: sve_signature_many_arg_pred139; CHECK: [[RES:%[0-9]+]]:ppr = COPY $p3140; CHECK: $p0 = COPY [[RES]]141; CHECK: RET_ReallyLR implicit $p0142; DARWIN-LABEL: name: sve_signature_many_arg_pred143; DARWIN: [[RES:%[0-9]+]]:ppr = COPY $p3144; DARWIN: $p0 = COPY [[RES]]145; DARWIN: RET_ReallyLR implicit $p0146define <vscale x 4 x i1> @sve_signature_many_arg_pred(<vscale x 4 x i1> %arg1, <vscale x 4 x i1> %arg2, <vscale x 4 x i1> %arg3, <vscale x 4 x i1> %arg4) nounwind {147 ret <vscale x 4 x i1> %arg4148}149 150; CHECK-LABEL: name: sve_signature_vec151; CHECK: [[RES:%[0-9]+]]:zpr = COPY $z1152; CHECK: $z0 = COPY [[RES]]153; CHECK: RET_ReallyLR implicit $z0154; DARWIN-LABEL: name: sve_signature_vec155; DARWIN: [[RES:%[0-9]+]]:zpr = COPY $z1156; DARWIN: $z0 = COPY [[RES]]157; DARWIN: RET_ReallyLR implicit $z0158define <vscale x 4 x i32> @sve_signature_vec(<vscale x 4 x i32> %arg1, <vscale x 4 x i32> %arg2) nounwind {159 ret <vscale x 4 x i32> %arg2160}161 162; CHECK-LABEL: name: sve_signature_pred163; CHECK: [[RES:%[0-9]+]]:ppr = COPY $p1164; CHECK: $p0 = COPY [[RES]]165; CHECK: RET_ReallyLR implicit $p0166; DARWIN-LABEL: name: sve_signature_pred167; DARWIN: [[RES:%[0-9]+]]:ppr = COPY $p1168; DARWIN: $p0 = COPY [[RES]]169; DARWIN: RET_ReallyLR implicit $p0170define <vscale x 4 x i1> @sve_signature_pred(<vscale x 4 x i1> %arg1, <vscale x 4 x i1> %arg2) nounwind {171 ret <vscale x 4 x i1> %arg2172}173 174; Test that scalable predicate argument in [1 x <vscale x 4 x i1>] type are properly assigned to P registers.175; CHECK-LABEL: name: sve_signature_pred_1xv4i1176; CHECK: [[RES:%[0-9]+]]:ppr = COPY $p1177; CHECK: $p0 = COPY [[RES]]178; CHECK: RET_ReallyLR implicit $p0179define [1 x <vscale x 4 x i1>] @sve_signature_pred_1xv4i1([1 x <vscale x 4 x i1>] %arg1, [1 x <vscale x 4 x i1>] %arg2) nounwind {180 ret [1 x <vscale x 4 x i1>] %arg2181}182 183; Test that upto to two scalable predicate arguments in [2 x <vscale x 4 x i1>] type can be assigned to P registers.184; CHECK-LABEL: name: sve_signature_pred_2xv4i1185; CHECK: [[RES1:%[0-9]+]]:ppr = COPY $p3186; CHECK: [[RES0:%[0-9]+]]:ppr = COPY $p2187; CHECK: $p0 = COPY [[RES0]]188; CHECK: $p1 = COPY [[RES1]]189; CHECK: RET_ReallyLR implicit $p0, implicit $p1190define [2 x <vscale x 4 x i1>] @sve_signature_pred_2xv4i1([2 x <vscale x 4 x i1>] %arg1, [2 x <vscale x 4 x i1>] %arg2) nounwind {191 ret [2 x <vscale x 4 x i1>] %arg2192}193 194; Test that a scalable predicate argument in [1 x <vscale x 32 x i1>] type is assigned to two P registers.195; CHECK-LABLE: name: sve_signature_pred_1xv32i1196; CHECK: [[RES1:%[0-9]+]]:ppr = COPY $p3197; CHECK: [[RES0:%[0-9]+]]:ppr = COPY $p2198; CHECK: $p0 = COPY [[RES0]]199; CHECK: $p1 = COPY [[RES1]]200; CHECK: RET_ReallyLR implicit $p0, implicit $p1201define [1 x <vscale x 32 x i1>] @sve_signature_pred_1xv32i1([1 x <vscale x 32 x i1>] %arg1, [1 x <vscale x 32 x i1>] %arg2) nounwind {202 ret [1 x <vscale x 32 x i1>] %arg2203}204 205; Test that a scalable predicate argument in [2 x <vscale x 32 x i1>] type is assigned to four P registers.206; CHECK-LABLE: name: sve_signature_pred_2xv32i1207; CHECK: [[RES3:%[0-9]+]]:ppr = COPY $p3208; CHECK: [[RES2:%[0-9]+]]:ppr = COPY $p2209; CHECK: [[RES1:%[0-9]+]]:ppr = COPY $p1210; CHECK: [[RES0:%[0-9]+]]:ppr = COPY $p0211; CHECK: $p0 = COPY [[RES0]]212; CHECK: $p1 = COPY [[RES1]]213; CHECK: $p2 = COPY [[RES2]]214; CHECK: $p3 = COPY [[RES3]]215; CHECK: RET_ReallyLR implicit $p0, implicit $p1, implicit $p2, implicit $p3216define [2 x <vscale x 32 x i1>] @sve_signature_pred_2xv32i1([2 x <vscale x 32 x i1>] %arg1) nounwind {217 ret [2 x <vscale x 32 x i1>] %arg1218}219 220; CHECK-LABEL: name: sve_signature_vec_caller221; CHECK-DAG: [[ARG2:%[0-9]+]]:zpr = COPY $z1222; CHECK-DAG: [[ARG1:%[0-9]+]]:zpr = COPY $z0223; CHECK-DAG: $z0 = COPY [[ARG2]]224; CHECK-DAG: $z1 = COPY [[ARG1]]225; CHECK-NEXT: BL @sve_signature_vec, csr_aarch64_sve_aapcs226; CHECK: [[RES:%[0-9]+]]:zpr = COPY $z0227; CHECK: $z0 = COPY [[RES]]228; CHECK: RET_ReallyLR implicit $z0229; DARWIN-LABEL: name: sve_signature_vec_caller230; DARWIN-DAG: [[ARG2:%[0-9]+]]:zpr = COPY $z1231; DARWIN-DAG: [[ARG1:%[0-9]+]]:zpr = COPY $z0232; DARWIN-DAG: $z0 = COPY [[ARG2]]233; DARWIN-DAG: $z1 = COPY [[ARG1]]234; DARWIN-NEXT: BL @sve_signature_vec, csr_darwin_aarch64_sve_aapcs235; DARWIN: [[RES:%[0-9]+]]:zpr = COPY $z0236; DARWIN: $z0 = COPY [[RES]]237; DARWIN: RET_ReallyLR implicit $z0238define <vscale x 4 x i32> @sve_signature_vec_caller(<vscale x 4 x i32> %arg1, <vscale x 4 x i32> %arg2) nounwind {239 %res = call <vscale x 4 x i32> @sve_signature_vec(<vscale x 4 x i32> %arg2, <vscale x 4 x i32> %arg1)240 ret <vscale x 4 x i32> %res241}242 243; CHECK-LABEL: name: sve_signature_pred_caller244; CHECK-DAG: [[ARG2:%[0-9]+]]:ppr = COPY $p1245; CHECK-DAG: [[ARG1:%[0-9]+]]:ppr = COPY $p0246; CHECK-DAG: $p0 = COPY [[ARG2]]247; CHECK-DAG: $p1 = COPY [[ARG1]]248; CHECK-NEXT: BL @sve_signature_pred, csr_aarch64_sve_aapcs249; CHECK: [[RES:%[0-9]+]]:ppr = COPY $p0250; CHECK: $p0 = COPY [[RES]]251; CHECK: RET_ReallyLR implicit $p0252; DARWIN-LABEL: name: sve_signature_pred_caller253; DARWIN-DAG: [[ARG2:%[0-9]+]]:ppr = COPY $p1254; DARWIN-DAG: [[ARG1:%[0-9]+]]:ppr = COPY $p0255; DARWIN-DAG: $p0 = COPY [[ARG2]]256; DARWIN-DAG: $p1 = COPY [[ARG1]]257; DARWIN-NEXT: BL @sve_signature_pred, csr_darwin_aarch64_sve_aapcs258; DARWIN: [[RES:%[0-9]+]]:ppr = COPY $p0259; DARWIN: $p0 = COPY [[RES]]260; DARWIN: RET_ReallyLR implicit $p0261define <vscale x 4 x i1> @sve_signature_pred_caller(<vscale x 4 x i1> %arg1, <vscale x 4 x i1> %arg2) nounwind {262 %res = call <vscale x 4 x i1> @sve_signature_pred(<vscale x 4 x i1> %arg2, <vscale x 4 x i1> %arg1)263 ret <vscale x 4 x i1> %res264}265 266; CHECK-LABEL: name: sve_signature_pred_1xv4i1_caller267; CHECK-DAG: [[ARG2:%[0-9]+]]:ppr = COPY $p1268; CHECK-DAG: [[ARG1:%[0-9]+]]:ppr = COPY $p0269; CHECK-DAG: $p0 = COPY [[ARG2]]270; CHECK-DAG: $p1 = COPY [[ARG1]]271; CHECK-NEXT: BL @sve_signature_pred_1xv4i1, csr_aarch64_sve_aapcs272; CHECK: [[RES:%[0-9]+]]:ppr = COPY $p0273; CHECK: $p0 = COPY [[RES]]274; CHECK: RET_ReallyLR implicit $p0275define [1 x <vscale x 4 x i1>] @sve_signature_pred_1xv4i1_caller([1 x <vscale x 4 x i1>] %arg1, [1 x <vscale x 4 x i1>] %arg2) nounwind {276 %res = call [1 x <vscale x 4 x i1>] @sve_signature_pred_1xv4i1([1 x <vscale x 4 x i1>] %arg2, [1 x <vscale x 4 x i1>] %arg1)277 ret [1 x <vscale x 4 x i1>] %res278}279 280; CHECK-LABEL: name: sve_signature_pred_2xv4i1_caller281; CHECK-DAG: [[ARG2_2:%[0-9]+]]:ppr = COPY $p3282; CHECK-DAG: [[ARG2_1:%[0-9]+]]:ppr = COPY $p2283; CHECK-DAG: [[ARG1_2:%[0-9]+]]:ppr = COPY $p1284; CHECK-DAG: [[ARG1_1:%[0-9]+]]:ppr = COPY $p0285; CHECK-DAG: $p0 = COPY [[ARG2_1]]286; CHECK-DAG: $p1 = COPY [[ARG2_2]]287; CHECK-DAG: $p2 = COPY [[ARG1_1]]288; CHECK-DAG: $p3 = COPY [[ARG1_2]]289; CHECK-NEXT: BL @sve_signature_pred_2xv4i1, csr_aarch64_sve_aapcs290; CHECK: [[RES0:%[0-9]+]]:ppr = COPY $p0291; CHECK: [[RES1:%[0-9]+]]:ppr = COPY $p1292; CHECK: $p0 = COPY [[RES0]]293; CHECK: $p1 = COPY [[RES1]]294; CHECK: RET_ReallyLR implicit $p0, implicit $p1295define [2 x <vscale x 4 x i1>] @sve_signature_pred_2xv4i1_caller([2 x <vscale x 4 x i1>] %arg1, [2 x <vscale x 4 x i1>] %arg2) nounwind {296 %res = call [2 x <vscale x 4 x i1>] @sve_signature_pred_2xv4i1([2 x <vscale x 4 x i1>] %arg2, [2 x <vscale x 4 x i1>] %arg1)297 ret [2 x <vscale x 4 x i1>] %res298}299 300; CHECK-LABEL: name: sve_signature_pred_1xv32i1_caller301; CHECK-DAG: [[ARG2_2:%[0-9]+]]:ppr = COPY $p3302; CHECK-DAG: [[ARG2_1:%[0-9]+]]:ppr = COPY $p2303; CHECK-DAG: [[ARG1_2:%[0-9]+]]:ppr = COPY $p1304; CHECK-DAG: [[ARG1_1:%[0-9]+]]:ppr = COPY $p0305; CHECK-DAG: $p0 = COPY [[ARG2_1]]306; CHECK-DAG: $p1 = COPY [[ARG2_2]]307; CHECK-DAG: $p2 = COPY [[ARG1_1]]308; CHECK-DAG: $p3 = COPY [[ARG1_2]]309; CHECK-NEXT: BL @sve_signature_pred_1xv32i1, csr_aarch64_sve_aapcs310; CHECK: [[RES0:%[0-9]+]]:ppr = COPY $p0311; CHECK: [[RES1:%[0-9]+]]:ppr = COPY $p1312; CHECK: $p0 = COPY [[RES0]]313; CHECK: $p1 = COPY [[RES1]]314; CHECK: RET_ReallyLR implicit $p0, implicit $p1315define [1 x <vscale x 32 x i1>] @sve_signature_pred_1xv32i1_caller([1 x <vscale x 32 x i1>] %arg1, [1 x <vscale x 32 x i1>] %arg2) nounwind {316 %res = call [1 x <vscale x 32 x i1>] @sve_signature_pred_1xv32i1([1 x <vscale x 32 x i1>] %arg2, [1 x <vscale x 32 x i1>] %arg1)317 ret [1 x <vscale x 32 x i1>] %res318}319 320; CHECK-LABEL: name: sve_signature_pred_2xv32i1_caller321; CHECK-DAG: [[ARG3:%[0-9]+]]:ppr = COPY $p3322; CHECK-DAG: [[ARG2:%[0-9]+]]:ppr = COPY $p2323; CHECK-DAG: [[ARG1:%[0-9]+]]:ppr = COPY $p1324; CHECK-DAG: [[ARG0:%[0-9]+]]:ppr = COPY $p0325; CHECK-DAG: $p0 = COPY [[ARG0]]326; CHECK-DAG: $p1 = COPY [[ARG1]]327; CHECK-DAG: $p2 = COPY [[ARG2]]328; CHECK-DAG: $p3 = COPY [[ARG3]]329; CHECK-NEXT: BL @sve_signature_pred_2xv32i1, csr_aarch64_sve_aapcs330; CHECK: [[RES0:%[0-9]+]]:ppr = COPY $p0331; CHECK: [[RES1:%[0-9]+]]:ppr = COPY $p1332; CHECK: [[RES2:%[0-9]+]]:ppr = COPY $p2333; CHECK: [[RES3:%[0-9]+]]:ppr = COPY $p3334; CHECK: $p0 = COPY [[RES0]]335; CHECK: $p1 = COPY [[RES1]]336; CHECK: $p2 = COPY [[RES2]]337; CHECK: $p3 = COPY [[RES3]]338; CHECK: RET_ReallyLR implicit $p0, implicit $p1339define [2 x <vscale x 32 x i1>] @sve_signature_pred_2xv32i1_caller([2 x <vscale x 32 x i1>] %arg1) {340 %res = call [2 x <vscale x 32 x i1>] @sve_signature_pred_2xv32i1([2 x <vscale x 32 x i1>] %arg1)341 ret [2 x <vscale x 32 x i1>] %res342}343 344; Test that functions returning or taking SVE arguments use the correct345; callee-saved set when using the default C calling convention (as opposed346; to aarch64_sve_vector_pcs)347 348; CHECKCSR-LABEL: name: sve_signature_vec_ret_callee349; CHECKCSR: callee-saved-register: '$z8'350; CHECKCSR: callee-saved-register: '$p4'351; CHECKCSR: RET_ReallyLR352define <vscale x 4 x i32> @sve_signature_vec_ret_callee() nounwind {353 call void asm sideeffect "nop", "~{z8},~{p4}"()354 ret <vscale x 4 x i32> zeroinitializer355}356 357; CHECKCSR-LABEL: name: sve_signature_vec_arg_callee358; CHECKCSR: callee-saved-register: '$z8'359; CHECKCSR: callee-saved-register: '$p4'360; CHECKCSR: RET_ReallyLR361define void @sve_signature_vec_arg_callee(<vscale x 4 x i32> %v) nounwind {362 call void asm sideeffect "nop", "~{z8},~{p4}"()363 ret void364}365