353 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-unknown -mattr=+sve2p1 -o - < %s | FileCheck %s3 4define <vscale x 8 x i1> @not_icmp_sle_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {5; CHECK-LABEL: not_icmp_sle_nxv8i16:6; CHECK: // %bb.0:7; CHECK-NEXT: ptrue p0.h8; CHECK-NEXT: cmpgt p0.h, p0/z, z0.h, z1.h9; CHECK-NEXT: ret10 %icmp = icmp sle <vscale x 8 x i16> %a, %b11 %not = xor <vscale x 8 x i1> splat(i1 true), %icmp12 ret <vscale x 8 x i1> %not13}14 15define <vscale x 4 x i1> @not_icmp_sgt_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {16; CHECK-LABEL: not_icmp_sgt_nxv4i32:17; CHECK: // %bb.0:18; CHECK-NEXT: ptrue p0.s19; CHECK-NEXT: cmpge p0.s, p0/z, z1.s, z0.s20; CHECK-NEXT: ret21 %icmp = icmp sgt <vscale x 4 x i32> %a, %b22 %not = xor <vscale x 4 x i1> %icmp, splat(i1 true)23 ret <vscale x 4 x i1> %not24}25 26define <vscale x 2 x i1> @not_fcmp_une_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {27; CHECK-LABEL: not_fcmp_une_nxv2f64:28; CHECK: // %bb.0:29; CHECK-NEXT: ptrue p0.d30; CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, z1.d31; CHECK-NEXT: ret32 %icmp = fcmp une <vscale x 2 x double> %a, %b33 %not = xor <vscale x 2 x i1> %icmp, splat(i1 true)34 ret <vscale x 2 x i1> %not35}36 37define <vscale x 4 x i1> @not_fcmp_uge_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {38; CHECK-LABEL: not_fcmp_uge_nxv4f32:39; CHECK: // %bb.0:40; CHECK-NEXT: ptrue p0.s41; CHECK-NEXT: fcmgt p0.s, p0/z, z1.s, z0.s42; CHECK-NEXT: ret43 %icmp = fcmp uge <vscale x 4 x float> %a, %b44 %not = xor <vscale x 4 x i1> %icmp, splat(i1 true)45 ret <vscale x 4 x i1> %not46}47 48define <vscale x 16 x i8> @icmp_cnot_nxv16i8(<vscale x 16 x i8> %a) {49; CHECK-LABEL: icmp_cnot_nxv16i8:50; CHECK: // %bb.0:51; CHECK-NEXT: ptrue p0.b52; CHECK-NEXT: cnot z0.b, p0/m, z0.b53; CHECK-NEXT: ret54 %mask = icmp eq <vscale x 16 x i8> %a, zeroinitializer55 %zext = zext <vscale x 16 x i1> %mask to <vscale x 16 x i8>56 ret <vscale x 16 x i8> %zext57}58 59define <vscale x 8 x i16> @icmp_cnot_nxv8i16(<vscale x 8 x i16> %a) {60; CHECK-LABEL: icmp_cnot_nxv8i16:61; CHECK: // %bb.0:62; CHECK-NEXT: ptrue p0.h63; CHECK-NEXT: cnot z0.h, p0/m, z0.h64; CHECK-NEXT: ret65 %mask = icmp eq <vscale x 8 x i16> %a, zeroinitializer66 %zext = zext <vscale x 8 x i1> %mask to <vscale x 8 x i16>67 ret <vscale x 8 x i16> %zext68}69 70define <vscale x 4 x i32> @icmp_cnot_nxv4i32(<vscale x 4 x i32> %a) {71; CHECK-LABEL: icmp_cnot_nxv4i32:72; CHECK: // %bb.0:73; CHECK-NEXT: ptrue p0.s74; CHECK-NEXT: cnot z0.s, p0/m, z0.s75; CHECK-NEXT: ret76 %mask = icmp eq <vscale x 4 x i32> %a, zeroinitializer77 %zext = zext <vscale x 4 x i1> %mask to <vscale x 4 x i32>78 ret <vscale x 4 x i32> %zext79}80 81define <vscale x 2 x i64> @icmp_cnot_nxv2i64(<vscale x 2 x i64> %a) {82; CHECK-LABEL: icmp_cnot_nxv2i64:83; CHECK: // %bb.0:84; CHECK-NEXT: ptrue p0.d85; CHECK-NEXT: cnot z0.d, p0/m, z0.d86; CHECK-NEXT: ret87 %mask = icmp eq <vscale x 2 x i64> %a, zeroinitializer88 %zext = zext <vscale x 2 x i1> %mask to <vscale x 2 x i64>89 ret <vscale x 2 x i64> %zext90}91 92define i1 @foo_first(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {93; CHECK-LABEL: foo_first:94; CHECK: // %bb.0:95; CHECK-NEXT: ptrue p0.s96; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s97; CHECK-NEXT: ptest p0, p1.b98; CHECK-NEXT: cset w0, mi99; CHECK-NEXT: ret100 %vcond = fcmp oeq <vscale x 4 x float> %a, %b101 %bit = extractelement <vscale x 4 x i1> %vcond, i64 0102 ret i1 %bit103}104 105define i1 @foo_last(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {106; CHECK-LABEL: foo_last:107; CHECK: // %bb.0:108; CHECK-NEXT: ptrue p0.s109; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff110; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s111; CHECK-NEXT: mov z0.s, p0/z, #1 // =0x1112; CHECK-NEXT: whilels p0.s, xzr, x8113; CHECK-NEXT: lastb w8, p0, z0.s114; CHECK-NEXT: and w0, w8, #0x1115; CHECK-NEXT: ret116 %vcond = fcmp oeq <vscale x 4 x float> %a, %b117 %vscale = call i64 @llvm.vscale.i64()118 %shl2 = shl nuw nsw i64 %vscale, 2119 %idx = add nuw nsw i64 %shl2, -1120 %bit = extractelement <vscale x 4 x i1> %vcond, i64 %idx121 ret i1 %bit122}123 124define i1 @whilege_first(i64 %next, i64 %end) {125; CHECK-LABEL: whilege_first:126; CHECK: // %bb.0:127; CHECK-NEXT: whilege p0.s, x0, x1128; CHECK-NEXT: cset w0, mi129; CHECK-NEXT: ret130 %predicate = call <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i64(i64 %next, i64 %end)131 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0132 ret i1 %bit133}134 135define i1 @whilegt_first(i64 %next, i64 %end) {136; CHECK-LABEL: whilegt_first:137; CHECK: // %bb.0:138; CHECK-NEXT: whilegt p0.s, x0, x1139; CHECK-NEXT: cset w0, mi140; CHECK-NEXT: ret141 %predicate = call <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i64(i64 %next, i64 %end)142 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0143 ret i1 %bit144}145 146define i1 @whilehi_first(i64 %next, i64 %end) {147; CHECK-LABEL: whilehi_first:148; CHECK: // %bb.0:149; CHECK-NEXT: whilehi p0.s, x0, x1150; CHECK-NEXT: cset w0, mi151; CHECK-NEXT: ret152 %predicate = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i64(i64 %next, i64 %end)153 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0154 ret i1 %bit155}156 157define i1 @whilehs_first(i64 %next, i64 %end) {158; CHECK-LABEL: whilehs_first:159; CHECK: // %bb.0:160; CHECK-NEXT: whilehs p0.s, x0, x1161; CHECK-NEXT: cset w0, mi162; CHECK-NEXT: ret163 %predicate = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i64(i64 %next, i64 %end)164 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0165 ret i1 %bit166}167 168define i1 @whilele_first(i64 %next, i64 %end) {169; CHECK-LABEL: whilele_first:170; CHECK: // %bb.0:171; CHECK-NEXT: whilele p0.s, x0, x1172; CHECK-NEXT: cset w0, mi173; CHECK-NEXT: ret174 %predicate = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %next, i64 %end)175 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0176 ret i1 %bit177}178 179define i1 @whilelo_first(i64 %next, i64 %end) {180; CHECK-LABEL: whilelo_first:181; CHECK: // %bb.0:182; CHECK-NEXT: whilelo p0.s, x0, x1183; CHECK-NEXT: cset w0, mi184; CHECK-NEXT: ret185 %predicate = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i64(i64 %next, i64 %end)186 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0187 ret i1 %bit188}189 190define i1 @whilels_first(i64 %next, i64 %end) {191; CHECK-LABEL: whilels_first:192; CHECK: // %bb.0:193; CHECK-NEXT: whilels p0.s, x0, x1194; CHECK-NEXT: cset w0, mi195; CHECK-NEXT: ret196 %predicate = call <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i64(i64 %next, i64 %end)197 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0198 ret i1 %bit199}200 201define i1 @whilelt_first(i64 %next, i64 %end) {202; CHECK-LABEL: whilelt_first:203; CHECK: // %bb.0:204; CHECK-NEXT: whilelt p0.s, x0, x1205; CHECK-NEXT: cset w0, mi206; CHECK-NEXT: ret207 %predicate = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %next, i64 %end)208 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0209 ret i1 %bit210}211 212define i1 @lane_mask_first(i64 %next, i64 %end) {213; CHECK-LABEL: lane_mask_first:214; CHECK: // %bb.0:215; CHECK-NEXT: whilelo p0.s, x0, x1216; CHECK-NEXT: cset w0, mi217; CHECK-NEXT: ret218 %predicate = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 %next, i64 %end)219 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0220 ret i1 %bit221}222 223define i1 @whilege_x2_first(i64 %next, i64 %end) {224; CHECK-LABEL: whilege_x2_first:225; CHECK: // %bb.0:226; CHECK-NEXT: whilege { p0.s, p1.s }, x0, x1227; CHECK-NEXT: cset w0, mi228; CHECK-NEXT: ret229 %predpair = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1.i64(i64 %next, i64 %end)230 %predicate = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %predpair, 0231 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0232 ret i1 %bit233}234 235define i1 @whilegt_x2_first(i64 %next, i64 %end) {236; CHECK-LABEL: whilegt_x2_first:237; CHECK: // %bb.0:238; CHECK-NEXT: whilegt { p0.s, p1.s }, x0, x1239; CHECK-NEXT: cset w0, mi240; CHECK-NEXT: ret241 %predpair = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilegt.x2.nxv4i1.i64(i64 %next, i64 %end)242 %predicate = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %predpair, 0243 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0244 ret i1 %bit245}246 247define i1 @whilehi_x2_first(i64 %next, i64 %end) {248; CHECK-LABEL: whilehi_x2_first:249; CHECK: // %bb.0:250; CHECK-NEXT: whilehi { p0.s, p1.s }, x0, x1251; CHECK-NEXT: cset w0, mi252; CHECK-NEXT: ret253 %predpair = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehi.x2.nxv4i1.i64(i64 %next, i64 %end)254 %predicate = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %predpair, 0255 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0256 ret i1 %bit257}258 259define i1 @whilehs_x2_first(i64 %next, i64 %end) {260; CHECK-LABEL: whilehs_x2_first:261; CHECK: // %bb.0:262; CHECK-NEXT: whilehs { p0.s, p1.s }, x0, x1263; CHECK-NEXT: cset w0, mi264; CHECK-NEXT: ret265 %predpair = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1.i64(i64 %next, i64 %end)266 %predicate = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %predpair, 0267 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0268 ret i1 %bit269}270 271define i1 @whilele_x2_first(i64 %next, i64 %end) {272; CHECK-LABEL: whilele_x2_first:273; CHECK: // %bb.0:274; CHECK-NEXT: whilele { p0.s, p1.s }, x0, x1275; CHECK-NEXT: cset w0, mi276; CHECK-NEXT: ret277 %predpair = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilele.x2.nxv4i1.i64(i64 %next, i64 %end)278 %predicate = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %predpair, 0279 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0280 ret i1 %bit281}282 283define i1 @whilelo_x2_first(i64 %next, i64 %end) {284; CHECK-LABEL: whilelo_x2_first:285; CHECK: // %bb.0:286; CHECK-NEXT: whilelo { p0.s, p1.s }, x0, x1287; CHECK-NEXT: cset w0, mi288; CHECK-NEXT: ret289 %predpair = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilelo.x2.nxv4i1.i64(i64 %next, i64 %end)290 %predicate = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %predpair, 0291 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0292 ret i1 %bit293}294 295define i1 @whilels_x2_first(i64 %next, i64 %end) {296; CHECK-LABEL: whilels_x2_first:297; CHECK: // %bb.0:298; CHECK-NEXT: whilels { p0.s, p1.s }, x0, x1299; CHECK-NEXT: cset w0, mi300; CHECK-NEXT: ret301 %predpair = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilels.x2.nxv4i1.i64(i64 %next, i64 %end)302 %predicate = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %predpair, 0303 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0304 ret i1 %bit305}306 307define i1 @whilelt_x2_first(i64 %next, i64 %end) {308; CHECK-LABEL: whilelt_x2_first:309; CHECK: // %bb.0:310; CHECK-NEXT: whilelt { p0.s, p1.s }, x0, x1311; CHECK-NEXT: cset w0, mi312; CHECK-NEXT: ret313 %predpair = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilelt.x2.nxv4i1.i64(i64 %next, i64 %end)314 %predicate = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %predpair, 0315 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0316 ret i1 %bit317}318 319; Do not combine to ptest when the extract is not from the first vector result320define i1 @whilege_x2_second_result(i64 %next, i64 %end) {321; CHECK-LABEL: whilege_x2_second_result:322; CHECK: // %bb.0:323; CHECK-NEXT: whilege { p0.s, p1.s }, x0, x1324; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x1325; CHECK-NEXT: fmov w8, s0326; CHECK-NEXT: and w0, w8, #0x1327; CHECK-NEXT: ret328 %predpair = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1.i64(i64 %next, i64 %end)329 %predicate = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %predpair, 1330 %bit = extractelement <vscale x 4 x i1> %predicate, i64 0331 ret i1 %bit332}333 334declare i64 @llvm.vscale.i64()335declare <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i64(i64, i64)336declare <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i64(i64, i64)337declare <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i64(i64, i64)338declare <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i64(i64, i64)339declare <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64, i64)340declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i64(i64, i64)341declare <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i64(i64, i64)342declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64, i64)343declare <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64, i64)344 345declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64, i64)346declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilegt.x2.nxv4i1(i64, i64)347declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehi.x2.nxv4i1(i64, i64)348declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64, i64)349declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilele.x2.nxv4i1(i64, i64)350declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilelo.x2.nxv4i1(i64, i64)351declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilels.x2.nxv4i1(i64, i64)352declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilelt.x2.nxv4i1(i64, i64)353