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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=aarch64-eabi -mattr=+sve2 < %s | FileCheck %s3 4define float @add_f32(<vscale x 8 x float> %a, <vscale x 4 x float> %b) {5; CHECK-LABEL: add_f32:6; CHECK: // %bb.0:7; CHECK-NEXT: fadd z0.s, z0.s, z1.s8; CHECK-NEXT: ptrue p0.s9; CHECK-NEXT: fadd z0.s, z0.s, z2.s10; CHECK-NEXT: faddv s0, p0, z0.s11; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z012; CHECK-NEXT: ret13 %r1 = call fast float @llvm.vector.reduce.fadd.f32.nxv8f32(float -0.0, <vscale x 8 x float> %a)14 %r2 = call fast float @llvm.vector.reduce.fadd.f32.nxv4f32(float -0.0, <vscale x 4 x float> %b)15 %r = fadd fast float %r1, %r216 ret float %r17}18 19;define float @fmul_f32(<vscale x 8 x float> %a, <vscale x 4 x float> %b) {20; %r1 = call fast float @llvm.vector.reduce.fmul.f32.nxv8f32(float 1.0, <vscale x 8 x float> %a)21; %r2 = call fast float @llvm.vector.reduce.fmul.f32.nxv4f32(float 1.0, <vscale x 4 x float> %b)22; %r = fmul fast float %r1, %r223; ret float %r24;}25 26define float @fmin_f32(<vscale x 8 x float> %a, <vscale x 4 x float> %b) {27; CHECK-LABEL: fmin_f32:28; CHECK: // %bb.0:29; CHECK-NEXT: ptrue p0.s30; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s31; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z2.s32; CHECK-NEXT: fminnmv s0, p0, z0.s33; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z034; CHECK-NEXT: ret35 %r1 = call fast float @llvm.vector.reduce.fmin.nxv8f32(<vscale x 8 x float> %a)36 %r2 = call fast float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %b)37 %r = call float @llvm.minnum.f32(float %r1, float %r2)38 ret float %r39}40 41define float @fmax_f32(<vscale x 8 x float> %a, <vscale x 4 x float> %b) {42; CHECK-LABEL: fmax_f32:43; CHECK: // %bb.0:44; CHECK-NEXT: ptrue p0.s45; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s46; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z2.s47; CHECK-NEXT: fmaxnmv s0, p0, z0.s48; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z049; CHECK-NEXT: ret50 %r1 = call fast float @llvm.vector.reduce.fmax.nxv8f32(<vscale x 8 x float> %a)51 %r2 = call fast float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float> %b)52 %r = call float @llvm.maxnum.f32(float %r1, float %r2)53 ret float %r54}55 56define float @fminimum_f32(<vscale x 8 x float> %a, <vscale x 4 x float> %b) {57; CHECK-LABEL: fminimum_f32:58; CHECK: // %bb.0:59; CHECK-NEXT: ptrue p0.s60; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s61; CHECK-NEXT: fminv s1, p0, z2.s62; CHECK-NEXT: fminv s0, p0, z0.s63; CHECK-NEXT: fminnm s0, s0, s164; CHECK-NEXT: ret65 %r1 = call fast float @llvm.vector.reduce.fminimum.nxv8f32(<vscale x 8 x float> %a)66 %r2 = call fast float @llvm.vector.reduce.fminimum.nxv4f32(<vscale x 4 x float> %b)67 %r = call float @llvm.minnum.f32(float %r1, float %r2)68 ret float %r69}70 71define float @fmaximum_f32(<vscale x 8 x float> %a, <vscale x 4 x float> %b) {72; CHECK-LABEL: fmaximum_f32:73; CHECK: // %bb.0:74; CHECK-NEXT: ptrue p0.s75; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s76; CHECK-NEXT: fmaxv s1, p0, z2.s77; CHECK-NEXT: fmaxv s0, p0, z0.s78; CHECK-NEXT: fmaxnm s0, s0, s179; CHECK-NEXT: ret80 %r1 = call fast float @llvm.vector.reduce.fmaximum.nxv8f32(<vscale x 8 x float> %a)81 %r2 = call fast float @llvm.vector.reduce.fmaximum.nxv4f32(<vscale x 4 x float> %b)82 %r = call float @llvm.maxnum.f32(float %r1, float %r2)83 ret float %r84}85 86 87define i32 @add_i32(<vscale x 8 x i32> %a, <vscale x 4 x i32> %b) {88; CHECK-LABEL: add_i32:89; CHECK: // %bb.0:90; CHECK-NEXT: add z0.s, z0.s, z1.s91; CHECK-NEXT: ptrue p0.s92; CHECK-NEXT: add z0.s, z0.s, z2.s93; CHECK-NEXT: uaddv d0, p0, z0.s94; CHECK-NEXT: fmov w0, s095; CHECK-NEXT: ret96 %r1 = call i32 @llvm.vector.reduce.add.i32.nxv8i32(<vscale x 8 x i32> %a)97 %r2 = call i32 @llvm.vector.reduce.add.i32.nxv4i32(<vscale x 4 x i32> %b)98 %r = add i32 %r1, %r299 ret i32 %r100}101 102define i16 @add_ext_i16(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {103; CHECK-LABEL: add_ext_i16:104; CHECK: // %bb.0:105; CHECK-NEXT: uunpkhi z2.h, z0.b106; CHECK-NEXT: uunpklo z0.h, z0.b107; CHECK-NEXT: uunpkhi z3.h, z1.b108; CHECK-NEXT: uunpklo z1.h, z1.b109; CHECK-NEXT: ptrue p0.h110; CHECK-NEXT: add z0.h, z0.h, z2.h111; CHECK-NEXT: add z1.h, z1.h, z3.h112; CHECK-NEXT: add z0.h, z0.h, z1.h113; CHECK-NEXT: uaddv d0, p0, z0.h114; CHECK-NEXT: fmov w0, s0115; CHECK-NEXT: ret116 %ae = zext <vscale x 16 x i8> %a to <vscale x 16 x i16>117 %be = zext <vscale x 16 x i8> %b to <vscale x 16 x i16>118 %r1 = call i16 @llvm.vector.reduce.add.i16.nxv16i16(<vscale x 16 x i16> %ae)119 %r2 = call i16 @llvm.vector.reduce.add.i16.nxv16i16(<vscale x 16 x i16> %be)120 %r = add i16 %r1, %r2121 ret i16 %r122}123 124define i16 @add_ext_v32i16(<vscale x 32 x i8> %a, <vscale x 16 x i8> %b) {125; CHECK-LABEL: add_ext_v32i16:126; CHECK: // %bb.0:127; CHECK-NEXT: uunpklo z3.h, z1.b128; CHECK-NEXT: uunpklo z4.h, z0.b129; CHECK-NEXT: uunpkhi z1.h, z1.b130; CHECK-NEXT: uunpkhi z0.h, z0.b131; CHECK-NEXT: uunpkhi z5.h, z2.b132; CHECK-NEXT: uunpklo z2.h, z2.b133; CHECK-NEXT: ptrue p0.h134; CHECK-NEXT: add z0.h, z0.h, z1.h135; CHECK-NEXT: add z1.h, z4.h, z3.h136; CHECK-NEXT: add z0.h, z1.h, z0.h137; CHECK-NEXT: add z1.h, z2.h, z5.h138; CHECK-NEXT: add z0.h, z0.h, z1.h139; CHECK-NEXT: uaddv d0, p0, z0.h140; CHECK-NEXT: fmov w0, s0141; CHECK-NEXT: ret142 %ae = zext <vscale x 32 x i8> %a to <vscale x 32 x i16>143 %be = zext <vscale x 16 x i8> %b to <vscale x 16 x i16>144 %r1 = call i16 @llvm.vector.reduce.add.i16.nxv32i16(<vscale x 32 x i16> %ae)145 %r2 = call i16 @llvm.vector.reduce.add.i16.nxv16i16(<vscale x 16 x i16> %be)146 %r = add i16 %r1, %r2147 ret i16 %r148}149 150;define i32 @mul_i32(<vscale x 8 x i32> %a, <vscale x 4 x i32> %b) {151; %r1 = call i32 @llvm.vector.reduce.mul.i32.nxv8i32(<vscale x 8 x i32> %a)152; %r2 = call i32 @llvm.vector.reduce.mul.i32.nxv4i32(<vscale x 4 x i32> %b)153; %r = mul i32 %r1, %r2154; ret i32 %r155;}156 157define i32 @and_i32(<vscale x 8 x i32> %a, <vscale x 4 x i32> %b) {158; CHECK-LABEL: and_i32:159; CHECK: // %bb.0:160; CHECK-NEXT: and z0.d, z0.d, z1.d161; CHECK-NEXT: ptrue p0.s162; CHECK-NEXT: and z0.d, z0.d, z2.d163; CHECK-NEXT: andv s0, p0, z0.s164; CHECK-NEXT: fmov w0, s0165; CHECK-NEXT: ret166 %r1 = call i32 @llvm.vector.reduce.and.i32.nxv8i32(<vscale x 8 x i32> %a)167 %r2 = call i32 @llvm.vector.reduce.and.i32.nxv4i32(<vscale x 4 x i32> %b)168 %r = and i32 %r1, %r2169 ret i32 %r170}171 172define i32 @or_i32(<vscale x 8 x i32> %a, <vscale x 4 x i32> %b) {173; CHECK-LABEL: or_i32:174; CHECK: // %bb.0:175; CHECK-NEXT: orr z0.d, z0.d, z1.d176; CHECK-NEXT: ptrue p0.s177; CHECK-NEXT: orr z0.d, z0.d, z2.d178; CHECK-NEXT: orv s0, p0, z0.s179; CHECK-NEXT: fmov w0, s0180; CHECK-NEXT: ret181 %r1 = call i32 @llvm.vector.reduce.or.i32.nxv8i32(<vscale x 8 x i32> %a)182 %r2 = call i32 @llvm.vector.reduce.or.i32.nxv4i32(<vscale x 4 x i32> %b)183 %r = or i32 %r1, %r2184 ret i32 %r185}186 187define i32 @xor_i32(<vscale x 8 x i32> %a, <vscale x 4 x i32> %b) {188; CHECK-LABEL: xor_i32:189; CHECK: // %bb.0:190; CHECK-NEXT: eor3 z0.d, z0.d, z1.d, z2.d191; CHECK-NEXT: ptrue p0.s192; CHECK-NEXT: eorv s0, p0, z0.s193; CHECK-NEXT: fmov w0, s0194; CHECK-NEXT: ret195 %r1 = call i32 @llvm.vector.reduce.xor.i32.nxv8i32(<vscale x 8 x i32> %a)196 %r2 = call i32 @llvm.vector.reduce.xor.i32.nxv4i32(<vscale x 4 x i32> %b)197 %r = xor i32 %r1, %r2198 ret i32 %r199}200 201define i32 @umin_i32(<vscale x 8 x i32> %a, <vscale x 4 x i32> %b) {202; CHECK-LABEL: umin_i32:203; CHECK: // %bb.0:204; CHECK-NEXT: ptrue p0.s205; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s206; CHECK-NEXT: umin z0.s, p0/m, z0.s, z2.s207; CHECK-NEXT: uminv s0, p0, z0.s208; CHECK-NEXT: fmov w0, s0209; CHECK-NEXT: ret210 %r1 = call i32 @llvm.vector.reduce.umin.i32.nxv8i32(<vscale x 8 x i32> %a)211 %r2 = call i32 @llvm.vector.reduce.umin.i32.nxv4i32(<vscale x 4 x i32> %b)212 %r = call i32 @llvm.umin.i32(i32 %r1, i32 %r2)213 ret i32 %r214}215 216define i32 @umax_i32(<vscale x 8 x i32> %a, <vscale x 4 x i32> %b) {217; CHECK-LABEL: umax_i32:218; CHECK: // %bb.0:219; CHECK-NEXT: ptrue p0.s220; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s221; CHECK-NEXT: umax z0.s, p0/m, z0.s, z2.s222; CHECK-NEXT: umaxv s0, p0, z0.s223; CHECK-NEXT: fmov w0, s0224; CHECK-NEXT: ret225 %r1 = call i32 @llvm.vector.reduce.umax.i32.nxv8i32(<vscale x 8 x i32> %a)226 %r2 = call i32 @llvm.vector.reduce.umax.i32.nxv4i32(<vscale x 4 x i32> %b)227 %r = call i32 @llvm.umax.i32(i32 %r1, i32 %r2)228 ret i32 %r229}230 231define i32 @smin_i32(<vscale x 8 x i32> %a, <vscale x 4 x i32> %b) {232; CHECK-LABEL: smin_i32:233; CHECK: // %bb.0:234; CHECK-NEXT: ptrue p0.s235; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s236; CHECK-NEXT: smin z0.s, p0/m, z0.s, z2.s237; CHECK-NEXT: sminv s0, p0, z0.s238; CHECK-NEXT: fmov w0, s0239; CHECK-NEXT: ret240 %r1 = call i32 @llvm.vector.reduce.smin.i32.nxv8i32(<vscale x 8 x i32> %a)241 %r2 = call i32 @llvm.vector.reduce.smin.i32.nxv4i32(<vscale x 4 x i32> %b)242 %r = call i32 @llvm.smin.i32(i32 %r1, i32 %r2)243 ret i32 %r244}245 246define i32 @smax_i32(<vscale x 8 x i32> %a, <vscale x 4 x i32> %b) {247; CHECK-LABEL: smax_i32:248; CHECK: // %bb.0:249; CHECK-NEXT: ptrue p0.s250; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s251; CHECK-NEXT: smax z0.s, p0/m, z0.s, z2.s252; CHECK-NEXT: smaxv s0, p0, z0.s253; CHECK-NEXT: fmov w0, s0254; CHECK-NEXT: ret255 %r1 = call i32 @llvm.vector.reduce.smax.i32.nxv8i32(<vscale x 8 x i32> %a)256 %r2 = call i32 @llvm.vector.reduce.smax.i32.nxv4i32(<vscale x 4 x i32> %b)257 %r = call i32 @llvm.smax.i32(i32 %r1, i32 %r2)258 ret i32 %r259}260 261declare float @llvm.vector.reduce.fadd.f32.nxv8f32(float, <vscale x 8 x float>)262declare float @llvm.vector.reduce.fadd.f32.nxv4f32(float, <vscale x 4 x float>)263declare float @llvm.vector.reduce.fmul.f32.nxv8f32(float, <vscale x 8 x float>)264declare float @llvm.vector.reduce.fmul.f32.nxv4f32(float, <vscale x 4 x float>)265declare float @llvm.vector.reduce.fmin.nxv8f32(<vscale x 8 x float>)266declare float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float>)267declare float @llvm.vector.reduce.fminimum.nxv8f32(<vscale x 8 x float>)268declare float @llvm.vector.reduce.fminimum.nxv4f32(<vscale x 4 x float>)269declare float @llvm.vector.reduce.fmax.nxv8f32(<vscale x 8 x float>)270declare float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float>)271declare float @llvm.vector.reduce.fmaximum.nxv8f32(<vscale x 8 x float>)272declare float @llvm.vector.reduce.fmaximum.nxv4f32(<vscale x 4 x float>)273declare i32 @llvm.vector.reduce.add.i32.nxv8i32(<vscale x 8 x i32>)274declare i32 @llvm.vector.reduce.add.i32.nxv4i32(<vscale x 4 x i32>)275declare i16 @llvm.vector.reduce.add.i16.nxv32i16(<vscale x 32 x i16>)276declare i16 @llvm.vector.reduce.add.i16.nxv16i16(<vscale x 16 x i16>)277declare i32 @llvm.vector.reduce.mul.i32.nxv8i32(<vscale x 8 x i32>)278declare i32 @llvm.vector.reduce.mul.i32.nxv4i32(<vscale x 4 x i32>)279declare i32 @llvm.vector.reduce.and.i32.nxv8i32(<vscale x 8 x i32>)280declare i32 @llvm.vector.reduce.and.i32.nxv4i32(<vscale x 4 x i32>)281declare i32 @llvm.vector.reduce.or.i32.nxv8i32(<vscale x 8 x i32>)282declare i32 @llvm.vector.reduce.or.i32.nxv4i32(<vscale x 4 x i32>)283declare i32 @llvm.vector.reduce.xor.i32.nxv8i32(<vscale x 8 x i32>)284declare i32 @llvm.vector.reduce.xor.i32.nxv4i32(<vscale x 4 x i32>)285declare i32 @llvm.vector.reduce.umin.i32.nxv8i32(<vscale x 8 x i32>)286declare i32 @llvm.vector.reduce.umin.i32.nxv4i32(<vscale x 4 x i32>)287declare i32 @llvm.vector.reduce.umax.i32.nxv8i32(<vscale x 8 x i32>)288declare i32 @llvm.vector.reduce.umax.i32.nxv4i32(<vscale x 4 x i32>)289declare i32 @llvm.vector.reduce.smin.i32.nxv8i32(<vscale x 8 x i32>)290declare i32 @llvm.vector.reduce.smin.i32.nxv4i32(<vscale x 4 x i32>)291declare i32 @llvm.vector.reduce.smax.i32.nxv8i32(<vscale x 8 x i32>)292declare i32 @llvm.vector.reduce.smax.i32.nxv4i32(<vscale x 4 x i32>)293declare float @llvm.minnum.f32(float, float)294declare float @llvm.maxnum.f32(float, float)295declare float @llvm.minimum.f32(float, float)296declare float @llvm.maximum.f32(float, float)297declare i32 @llvm.umin.i32(i32, i32)298declare i32 @llvm.umax.i32(i32, i32)299declare i32 @llvm.smin.i32(i32, i32)300declare i32 @llvm.smax.i32(i32, i32)301