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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -use-constant-int-for-scalable-splat < %s | FileCheck %s4 5; Check that expensive divides are expanded into a more performant sequence6 7;8; SDIV9;10 11define <vscale x 16 x i8> @sdiv_i8(<vscale x 16 x i8> %a) #0 {12; CHECK-LABEL: sdiv_i8:13; CHECK: // %bb.0:14; CHECK-NEXT: mov z1.b, #86 // =0x5615; CHECK-NEXT: ptrue p0.b16; CHECK-NEXT: smulh z0.b, p0/m, z0.b, z1.b17; CHECK-NEXT: lsr z1.b, z0.b, #718; CHECK-NEXT: add z0.b, z0.b, z1.b19; CHECK-NEXT: ret20 %div = sdiv <vscale x 16 x i8> %a, splat (i8 3)21 ret <vscale x 16 x i8> %div22}23 24define <vscale x 8 x i16> @sdiv_i16(<vscale x 8 x i16> %a) #0 {25; CHECK-LABEL: sdiv_i16:26; CHECK: // %bb.0:27; CHECK-NEXT: mov w8, #21846 // =0x555628; CHECK-NEXT: ptrue p0.h29; CHECK-NEXT: mov z1.h, w830; CHECK-NEXT: smulh z0.h, p0/m, z0.h, z1.h31; CHECK-NEXT: lsr z1.h, z0.h, #1532; CHECK-NEXT: add z0.h, z0.h, z1.h33; CHECK-NEXT: ret34 %div = sdiv <vscale x 8 x i16> %a, splat (i16 3)35 ret <vscale x 8 x i16> %div36}37 38define <vscale x 4 x i32> @sdiv_i32(<vscale x 4 x i32> %a) #0 {39; CHECK-LABEL: sdiv_i32:40; CHECK: // %bb.0:41; CHECK-NEXT: mov w8, #21846 // =0x555642; CHECK-NEXT: ptrue p0.s43; CHECK-NEXT: movk w8, #21845, lsl #1644; CHECK-NEXT: mov z1.s, w845; CHECK-NEXT: smulh z0.s, p0/m, z0.s, z1.s46; CHECK-NEXT: lsr z1.s, z0.s, #3147; CHECK-NEXT: add z0.s, z0.s, z1.s48; CHECK-NEXT: ret49 %div = sdiv <vscale x 4 x i32> %a, splat (i32 3)50 ret <vscale x 4 x i32> %div51}52 53define <vscale x 2 x i64> @sdiv_i64(<vscale x 2 x i64> %a) #0 {54; CHECK-LABEL: sdiv_i64:55; CHECK: // %bb.0:56; CHECK-NEXT: mov x8, #6148914691236517205 // =0x555555555555555557; CHECK-NEXT: ptrue p0.d58; CHECK-NEXT: movk x8, #2184659; CHECK-NEXT: mov z1.d, x860; CHECK-NEXT: smulh z0.d, p0/m, z0.d, z1.d61; CHECK-NEXT: lsr z1.d, z0.d, #6362; CHECK-NEXT: add z0.d, z0.d, z1.d63; CHECK-NEXT: ret64 %div = sdiv <vscale x 2 x i64> %a, splat (i64 3)65 ret <vscale x 2 x i64> %div66}67 68;69; UDIV70;71 72define <vscale x 16 x i8> @udiv_i8(<vscale x 16 x i8> %a) #0 {73; CHECK-LABEL: udiv_i8:74; CHECK: // %bb.0:75; CHECK-NEXT: mov z1.b, #-85 // =0xffffffffffffffab76; CHECK-NEXT: ptrue p0.b77; CHECK-NEXT: umulh z0.b, p0/m, z0.b, z1.b78; CHECK-NEXT: lsr z0.b, z0.b, #179; CHECK-NEXT: ret80 %div = udiv <vscale x 16 x i8> %a, splat (i8 3)81 ret <vscale x 16 x i8> %div82}83 84define <vscale x 8 x i16> @udiv_i16(<vscale x 8 x i16> %a) #0 {85; CHECK-LABEL: udiv_i16:86; CHECK: // %bb.0:87; CHECK-NEXT: mov w8, #-21845 // =0xffffaaab88; CHECK-NEXT: ptrue p0.h89; CHECK-NEXT: mov z1.h, w890; CHECK-NEXT: umulh z0.h, p0/m, z0.h, z1.h91; CHECK-NEXT: lsr z0.h, z0.h, #192; CHECK-NEXT: ret93 %div = udiv <vscale x 8 x i16> %a, splat (i16 3)94 ret <vscale x 8 x i16> %div95}96 97define <vscale x 4 x i32> @udiv_i32(<vscale x 4 x i32> %a) #0 {98; CHECK-LABEL: udiv_i32:99; CHECK: // %bb.0:100; CHECK-NEXT: mov w8, #43691 // =0xaaab101; CHECK-NEXT: ptrue p0.s102; CHECK-NEXT: movk w8, #43690, lsl #16103; CHECK-NEXT: mov z1.s, w8104; CHECK-NEXT: umulh z0.s, p0/m, z0.s, z1.s105; CHECK-NEXT: lsr z0.s, z0.s, #1106; CHECK-NEXT: ret107 %div = udiv <vscale x 4 x i32> %a, splat (i32 3)108 ret <vscale x 4 x i32> %div109}110 111define <vscale x 2 x i64> @udiv_i64(<vscale x 2 x i64> %a) #0 {112; CHECK-LABEL: udiv_i64:113; CHECK: // %bb.0:114; CHECK-NEXT: mov x8, #-6148914691236517206 // =0xaaaaaaaaaaaaaaaa115; CHECK-NEXT: ptrue p0.d116; CHECK-NEXT: movk x8, #43691117; CHECK-NEXT: mov z1.d, x8118; CHECK-NEXT: umulh z0.d, p0/m, z0.d, z1.d119; CHECK-NEXT: lsr z0.d, z0.d, #1120; CHECK-NEXT: ret121 %div = udiv <vscale x 2 x i64> %a, splat (i64 3)122 ret <vscale x 2 x i64> %div123}124 125attributes #0 = { "target-features"="+sve" }126