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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6define <vscale x 8 x i8> @extload_icmp_nxv8i8(ptr %in) #0 {7; CHECK-LABEL: extload_icmp_nxv8i8:8; CHECK: // %bb.0:9; CHECK-NEXT: ptrue p0.h10; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]11; CHECK-NEXT: cnot z0.h, p0/m, z0.h12; CHECK-NEXT: ret13 %ld = load <vscale x 8 x i8>, ptr %in14 %cmp = icmp eq <vscale x 8 x i8> %ld, zeroinitializer15 %ex = zext <vscale x 8 x i1> %cmp to <vscale x 8 x i8>16 ret <vscale x 8 x i8> %ex17}18 19define <vscale x 16 x i8> @extload_icmp_nxv16i8(ptr %in) #0 {20; CHECK-LABEL: extload_icmp_nxv16i8:21; CHECK: // %bb.0:22; CHECK-NEXT: ldr z0, [x0]23; CHECK-NEXT: ptrue p0.b24; CHECK-NEXT: cnot z0.b, p0/m, z0.b25; CHECK-NEXT: ret26 %ld = load <vscale x 16 x i8>, ptr %in27 %cmp = icmp eq <vscale x 16 x i8> %ld, zeroinitializer28 %ex = zext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>29 ret <vscale x 16 x i8> %ex30}31 32define <vscale x 4 x i16> @extload_icmp_nxv4i16(ptr %in) #0 {33; CHECK-LABEL: extload_icmp_nxv4i16:34; CHECK: // %bb.0:35; CHECK-NEXT: ptrue p0.s36; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]37; CHECK-NEXT: cnot z0.s, p0/m, z0.s38; CHECK-NEXT: ret39 %ld = load <vscale x 4 x i16>, ptr %in40 %cmp = icmp eq <vscale x 4 x i16> %ld, zeroinitializer41 %ex = zext <vscale x 4 x i1> %cmp to <vscale x 4 x i16>42 ret <vscale x 4 x i16> %ex43}44 45define <vscale x 8 x i16> @extload_icmp_nxv8i16(ptr %in) #0 {46; CHECK-LABEL: extload_icmp_nxv8i16:47; CHECK: // %bb.0:48; CHECK-NEXT: ldr z0, [x0]49; CHECK-NEXT: ptrue p0.h50; CHECK-NEXT: cnot z0.h, p0/m, z0.h51; CHECK-NEXT: ret52 %ld = load <vscale x 8 x i16>, ptr %in53 %cmp = icmp eq <vscale x 8 x i16> %ld, zeroinitializer54 %ex = zext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>55 ret <vscale x 8 x i16> %ex56}57 58define <vscale x 2 x i32> @extload_icmp_nxv2i32(ptr %in) #0 {59; CHECK-LABEL: extload_icmp_nxv2i32:60; CHECK: // %bb.0:61; CHECK-NEXT: ptrue p0.d62; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]63; CHECK-NEXT: cnot z0.d, p0/m, z0.d64; CHECK-NEXT: ret65 %ld = load <vscale x 2 x i32>, ptr %in66 %cmp = icmp eq <vscale x 2 x i32> %ld, zeroinitializer67 %ex = zext <vscale x 2 x i1> %cmp to <vscale x 2 x i32>68 ret <vscale x 2 x i32> %ex69}70 71define <vscale x 4 x i32> @extload_icmp_nxv4i32(ptr %in) #0 {72; CHECK-LABEL: extload_icmp_nxv4i32:73; CHECK: // %bb.0:74; CHECK-NEXT: ldr z0, [x0]75; CHECK-NEXT: ptrue p0.s76; CHECK-NEXT: cnot z0.s, p0/m, z0.s77; CHECK-NEXT: ret78 %ld = load <vscale x 4 x i32>, ptr %in79 %cmp = icmp eq <vscale x 4 x i32> %ld, zeroinitializer80 %ex = zext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>81 ret <vscale x 4 x i32> %ex82}83 84define <vscale x 2 x i64> @extload_icmp_nxv2i64(ptr %in) #0 {85; CHECK-LABEL: extload_icmp_nxv2i64:86; CHECK: // %bb.0:87; CHECK-NEXT: ldr z0, [x0]88; CHECK-NEXT: ptrue p0.d89; CHECK-NEXT: cnot z0.d, p0/m, z0.d90; CHECK-NEXT: ret91 %ld = load <vscale x 2 x i64>, ptr %in92 %cmp = icmp eq <vscale x 2 x i64> %ld, zeroinitializer93 %ex = zext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>94 ret <vscale x 2 x i64> %ex95}96 97 98 99attributes #0 = { "target-features"="+sve" }100