1557 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s | FileCheck %s --check-prefixes=CHECK3 4; Extracting illegal subvectors5 6; NOTE: Insert sub-vector into a legal type to avoid relying on an undefined7; calling convention.8define <vscale x 4 x i32> @extract_nxv1i32_nxv4i32_0(<vscale x 4 x i32> %vec) nounwind {9; CHECK-LABEL: extract_nxv1i32_nxv4i32_0:10; CHECK: // %bb.0:11; CHECK-NEXT: ret12 %e = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0)13 %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> poison, <vscale x 1 x i32> %e, i64 0)14 ret <vscale x 4 x i32> %retval15}16 17; NOTE: Insert sub-vector into a legal type to avoid relying on an undefined18; calling convention.19define <vscale x 4 x i32> @extract_nxv1i32_nxv4i32_1(<vscale x 4 x i32> %vec) nounwind {20; CHECK-LABEL: extract_nxv1i32_nxv4i32_1:21; CHECK: // %bb.0:22; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill23; CHECK-NEXT: addvl sp, sp, #-124; CHECK-NEXT: rdvl x8, #125; CHECK-NEXT: mov x9, sp26; CHECK-NEXT: str z0, [sp]27; CHECK-NEXT: lsr x8, x8, #428; CHECK-NEXT: whilelo p0.s, xzr, x829; CHECK-NEXT: cntw x830; CHECK-NEXT: add x8, x9, x831; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]32; CHECK-NEXT: addvl sp, sp, #133; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload34; CHECK-NEXT: ret35 %e = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %vec, i64 1)36 %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> poison, <vscale x 1 x i32> %e, i64 0)37 ret <vscale x 4 x i32> %retval38}39 40; NOTE: Insert sub-vector into a legal type to avoid relying on an undefined41; calling convention.42define <vscale x 4 x i32> @extract_nxv1i32_nxv4i32_2(<vscale x 4 x i32> %vec) nounwind {43; CHECK-LABEL: extract_nxv1i32_nxv4i32_2:44; CHECK: // %bb.0:45; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill46; CHECK-NEXT: addvl sp, sp, #-147; CHECK-NEXT: rdvl x8, #148; CHECK-NEXT: mov x9, sp49; CHECK-NEXT: str z0, [sp]50; CHECK-NEXT: lsr x8, x8, #451; CHECK-NEXT: whilelo p0.s, xzr, x852; CHECK-NEXT: cnth x853; CHECK-NEXT: add x8, x9, x854; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]55; CHECK-NEXT: addvl sp, sp, #156; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload57; CHECK-NEXT: ret58 %e = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %vec, i64 2)59 %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> poison, <vscale x 1 x i32> %e, i64 0)60 ret <vscale x 4 x i32> %retval61}62 63; NOTE: Insert sub-vector into a legal type to avoid relying on an undefined64; calling convention.65define <vscale x 4 x i32> @extract_nxv1i32_nxv4i32_3(<vscale x 4 x i32> %vec) nounwind {66; CHECK-LABEL: extract_nxv1i32_nxv4i32_3:67; CHECK: // %bb.0:68; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill69; CHECK-NEXT: addvl sp, sp, #-170; CHECK-NEXT: rdvl x8, #171; CHECK-NEXT: mov x9, sp72; CHECK-NEXT: str z0, [sp]73; CHECK-NEXT: lsr x8, x8, #474; CHECK-NEXT: whilelo p0.s, xzr, x875; CHECK-NEXT: cntw x8, all, mul #376; CHECK-NEXT: add x8, x9, x877; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]78; CHECK-NEXT: addvl sp, sp, #179; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload80; CHECK-NEXT: ret81 %e = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %vec, i64 3)82 %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> poison, <vscale x 1 x i32> %e, i64 0)83 ret <vscale x 4 x i32> %retval84}85 86; NOTE: Insert sub-vector into a legal type to avoid relying on an undefined87; calling convention.88define <vscale x 2 x float> @extract_nxv1f32_nxv2f32_0(<vscale x 2 x float> %vec) nounwind {89; CHECK-LABEL: extract_nxv1f32_nxv2f32_0:90; CHECK: // %bb.0:91; CHECK-NEXT: ret92 %e = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv2f32(<vscale x 2 x float> %vec, i64 0)93 %retval = call <vscale x 2 x float> @llvm.vector.insert.nxv2f32.nxv1f32(<vscale x 2 x float> poison, <vscale x 1 x float> %e, i64 0)94 ret <vscale x 2 x float> %retval95}96 97; NOTE: Insert sub-vector into a legal type to avoid relying on an undefined98; calling convention.99define <vscale x 2 x float> @extract_nxv1f32_nxv2f32_1(<vscale x 2 x float> %vec) nounwind {100; CHECK-LABEL: extract_nxv1f32_nxv2f32_1:101; CHECK: // %bb.0:102; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill103; CHECK-NEXT: addvl sp, sp, #-1104; CHECK-NEXT: rdvl x8, #1105; CHECK-NEXT: ptrue p0.d106; CHECK-NEXT: addpl x9, sp, #4107; CHECK-NEXT: lsr x8, x8, #4108; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]109; CHECK-NEXT: whilelo p1.d, xzr, x8110; CHECK-NEXT: cntw x8111; CHECK-NEXT: add x8, x9, x8112; CHECK-NEXT: ld1w { z0.d }, p1/z, [x8]113; CHECK-NEXT: addvl sp, sp, #1114; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload115; CHECK-NEXT: ret116 %e = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv2f32(<vscale x 2 x float> %vec, i64 1)117 %retval = call <vscale x 2 x float> @llvm.vector.insert.nxv2f32.nxv1f32(<vscale x 2 x float> poison, <vscale x 1 x float> %e, i64 0)118 ret <vscale x 2 x float> %retval119}120 121; NOTE: Insert sub-vector into a legal type to avoid relying on an undefined122; calling convention.123define <vscale x 4 x float> @extract_nxv1f32_nxv4f32_0(<vscale x 4 x float> %vec) nounwind {124; CHECK-LABEL: extract_nxv1f32_nxv4f32_0:125; CHECK: // %bb.0:126; CHECK-NEXT: ret127 %e = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> %vec, i64 0)128 %retval = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> poison, <vscale x 1 x float> %e, i64 0)129 ret <vscale x 4 x float> %retval130}131 132; NOTE: Insert sub-vector into a legal type to avoid relying on an undefined133; calling convention.134define <vscale x 4 x float> @extract_nxv1f32_nxv4f32_1(<vscale x 4 x float> %vec) nounwind {135; CHECK-LABEL: extract_nxv1f32_nxv4f32_1:136; CHECK: // %bb.0:137; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill138; CHECK-NEXT: addvl sp, sp, #-1139; CHECK-NEXT: rdvl x8, #1140; CHECK-NEXT: mov x9, sp141; CHECK-NEXT: str z0, [sp]142; CHECK-NEXT: lsr x8, x8, #4143; CHECK-NEXT: whilelo p0.d, xzr, x8144; CHECK-NEXT: cntw x8145; CHECK-NEXT: add x8, x9, x8146; CHECK-NEXT: ld1w { z0.d }, p0/z, [x8]147; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s148; CHECK-NEXT: addvl sp, sp, #1149; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload150; CHECK-NEXT: ret151 %e = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> %vec, i64 1)152 %retval = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> poison, <vscale x 1 x float> %e, i64 0)153 ret <vscale x 4 x float> %retval154}155 156; NOTE: Insert sub-vector into a legal type to avoid relying on an undefined157; calling convention.158define <vscale x 4 x float> @extract_nxv1f32_nxv4f32_2(<vscale x 4 x float> %vec) nounwind {159; CHECK-LABEL: extract_nxv1f32_nxv4f32_2:160; CHECK: // %bb.0:161; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill162; CHECK-NEXT: addvl sp, sp, #-1163; CHECK-NEXT: rdvl x8, #1164; CHECK-NEXT: str z0, [sp]165; CHECK-NEXT: lsr x8, x8, #4166; CHECK-NEXT: whilelo p0.d, xzr, x8167; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]168; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s169; CHECK-NEXT: addvl sp, sp, #1170; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload171; CHECK-NEXT: ret172 %e = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> %vec, i64 2)173 %retval = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> poison, <vscale x 1 x float> %e, i64 0)174 ret <vscale x 4 x float> %retval175}176 177; NOTE: Insert sub-vector into a legal type to avoid relying on an undefined178; calling convention.179define <vscale x 4 x float> @extract_nxv1f32_nxv4f32_3(<vscale x 4 x float> %vec) nounwind {180; CHECK-LABEL: extract_nxv1f32_nxv4f32_3:181; CHECK: // %bb.0:182; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill183; CHECK-NEXT: addvl sp, sp, #-1184; CHECK-NEXT: rdvl x8, #1185; CHECK-NEXT: mov x9, sp186; CHECK-NEXT: str z0, [sp]187; CHECK-NEXT: lsr x8, x8, #4188; CHECK-NEXT: whilelo p0.d, xzr, x8189; CHECK-NEXT: cntw x8, all, mul #3190; CHECK-NEXT: add x8, x9, x8191; CHECK-NEXT: ld1w { z0.d }, p0/z, [x8]192; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s193; CHECK-NEXT: addvl sp, sp, #1194; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload195; CHECK-NEXT: ret196 %e = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> %vec, i64 3)197 %retval = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> poison, <vscale x 1 x float> %e, i64 0)198 ret <vscale x 4 x float> %retval199}200 201define <vscale x 1 x i16> @extract_nxv1i16_nxv6i16(<vscale x 6 x i16> %vec) nounwind {202; CHECK-LABEL: extract_nxv1i16_nxv6i16:203; CHECK: // %bb.0:204; CHECK-NEXT: ret205 %retval = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv6i16(<vscale x 6 x i16> %vec, i64 0)206 ret <vscale x 1 x i16> %retval207}208 209;210; Extract half i1 vector that needs promotion from legal type.211;212define <vscale x 8 x i1> @extract_nxv8i1_nxv16i1_0(<vscale x 16 x i1> %in) {213; CHECK-LABEL: extract_nxv8i1_nxv16i1_0:214; CHECK: // %bb.0:215; CHECK-NEXT: punpklo p0.h, p0.b216; CHECK-NEXT: ret217 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %in, i64 0)218 ret <vscale x 8 x i1> %res219}220 221define <vscale x 8 x i1> @extract_nxv8i1_nxv16i1_8(<vscale x 16 x i1> %in) {222; CHECK-LABEL: extract_nxv8i1_nxv16i1_8:223; CHECK: // %bb.0:224; CHECK-NEXT: punpkhi p0.h, p0.b225; CHECK-NEXT: ret226 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %in, i64 8)227 ret <vscale x 8 x i1> %res228}229 230;231; Extract i1 vector that needs widening from one that needs widening.232;233define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_0(<vscale x 28 x i1> %in) {234; CHECK-LABEL: extract_nxv14i1_nxv28i1_0:235; CHECK: // %bb.0:236; CHECK-NEXT: ret237 %res = call <vscale x 14 x i1> @llvm.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1> %in, i64 0)238 ret <vscale x 14 x i1> %res239}240 241define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_14(<vscale x 28 x i1> %in) uwtable {242; CHECK-LABEL: extract_nxv14i1_nxv28i1_14:243; CHECK: // %bb.0:244; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill245; CHECK-NEXT: .cfi_def_cfa_offset 16246; CHECK-NEXT: .cfi_offset w29, -16247; CHECK-NEXT: addvl sp, sp, #-1248; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG249; CHECK-NEXT: punpkhi p2.h, p1.b250; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill251; CHECK-NEXT: punpklo p1.h, p1.b252; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill253; CHECK-NEXT: punpklo p2.h, p2.b254; CHECK-NEXT: punpkhi p3.h, p1.b255; CHECK-NEXT: punpkhi p4.h, p2.b256; CHECK-NEXT: punpklo p2.h, p2.b257; CHECK-NEXT: uzp1 p4.s, p4.s, p0.s258; CHECK-NEXT: punpkhi p0.h, p0.b259; CHECK-NEXT: punpkhi p5.h, p3.b260; CHECK-NEXT: punpklo p1.h, p1.b261; CHECK-NEXT: punpkhi p0.h, p0.b262; CHECK-NEXT: uzp1 p2.s, p5.s, p2.s263; CHECK-NEXT: punpklo p3.h, p3.b264; CHECK-NEXT: punpkhi p5.h, p1.b265; CHECK-NEXT: punpklo p1.h, p1.b266; CHECK-NEXT: punpkhi p0.h, p0.b267; CHECK-NEXT: uzp1 p3.s, p5.s, p3.s268; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload269; CHECK-NEXT: uzp1 p0.s, p0.s, p1.s270; CHECK-NEXT: uzp1 p1.h, p2.h, p4.h271; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload272; CHECK-NEXT: uzp1 p0.h, p0.h, p3.h273; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b274; CHECK-NEXT: addvl sp, sp, #1275; CHECK-NEXT: .cfi_def_cfa wsp, 16276; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload277; CHECK-NEXT: .cfi_def_cfa_offset 0278; CHECK-NEXT: .cfi_restore w29279; CHECK-NEXT: ret280 %res = call <vscale x 14 x i1> @llvm.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1> %in, i64 14)281 ret <vscale x 14 x i1> %res282}283 284;285; Extract half i1 vector that needs promotion from one that needs splitting.286;287define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_0(<vscale x 32 x i1> %in) {288; CHECK-LABEL: extract_nxv8i1_nxv32i1_0:289; CHECK: // %bb.0:290; CHECK-NEXT: punpklo p0.h, p0.b291; CHECK-NEXT: ret292 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 0)293 ret <vscale x 8 x i1> %res294}295 296define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_8(<vscale x 32 x i1> %in) {297; CHECK-LABEL: extract_nxv8i1_nxv32i1_8:298; CHECK: // %bb.0:299; CHECK-NEXT: punpkhi p0.h, p0.b300; CHECK-NEXT: ret301 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 8)302 ret <vscale x 8 x i1> %res303}304 305define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_16(<vscale x 32 x i1> %in) {306; CHECK-LABEL: extract_nxv8i1_nxv32i1_16:307; CHECK: // %bb.0:308; CHECK-NEXT: punpklo p0.h, p1.b309; CHECK-NEXT: ret310 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 16)311 ret <vscale x 8 x i1> %res312}313 314define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_24(<vscale x 32 x i1> %in) {315; CHECK-LABEL: extract_nxv8i1_nxv32i1_24:316; CHECK: // %bb.0:317; CHECK-NEXT: punpkhi p0.h, p1.b318; CHECK-NEXT: ret319 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 24)320 ret <vscale x 8 x i1> %res321}322 323;324; Extract 1/4th i1 vector that needs promotion from legal type.325;326define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_0(<vscale x 16 x i1> %in) {327; CHECK-LABEL: extract_nxv4i1_nxv16i1_0:328; CHECK: // %bb.0:329; CHECK-NEXT: punpklo p0.h, p0.b330; CHECK-NEXT: punpklo p0.h, p0.b331; CHECK-NEXT: ret332 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 0)333 ret <vscale x 4 x i1> %res334}335 336define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_4(<vscale x 16 x i1> %in) {337; CHECK-LABEL: extract_nxv4i1_nxv16i1_4:338; CHECK: // %bb.0:339; CHECK-NEXT: punpklo p0.h, p0.b340; CHECK-NEXT: punpkhi p0.h, p0.b341; CHECK-NEXT: ret342 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 4)343 ret <vscale x 4 x i1> %res344}345 346define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_8(<vscale x 16 x i1> %in) {347; CHECK-LABEL: extract_nxv4i1_nxv16i1_8:348; CHECK: // %bb.0:349; CHECK-NEXT: punpkhi p0.h, p0.b350; CHECK-NEXT: punpklo p0.h, p0.b351; CHECK-NEXT: ret352 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 8)353 ret <vscale x 4 x i1> %res354}355 356define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_12(<vscale x 16 x i1> %in) {357; CHECK-LABEL: extract_nxv4i1_nxv16i1_12:358; CHECK: // %bb.0:359; CHECK-NEXT: punpkhi p0.h, p0.b360; CHECK-NEXT: punpkhi p0.h, p0.b361; CHECK-NEXT: ret362 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 12)363 ret <vscale x 4 x i1> %res364}365 366;367; Extract 1/8th i1 vector that needs promotion from legal type.368;369define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_0(<vscale x 16 x i1> %in) {370; CHECK-LABEL: extract_nxv2i1_nxv16i1_0:371; CHECK: // %bb.0:372; CHECK-NEXT: punpklo p0.h, p0.b373; CHECK-NEXT: punpklo p0.h, p0.b374; CHECK-NEXT: punpklo p0.h, p0.b375; CHECK-NEXT: ret376 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 0)377 ret <vscale x 2 x i1> %res378}379 380define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_2(<vscale x 16 x i1> %in) {381; CHECK-LABEL: extract_nxv2i1_nxv16i1_2:382; CHECK: // %bb.0:383; CHECK-NEXT: punpklo p0.h, p0.b384; CHECK-NEXT: punpklo p0.h, p0.b385; CHECK-NEXT: punpkhi p0.h, p0.b386; CHECK-NEXT: ret387 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 2)388 ret <vscale x 2 x i1> %res389}390 391define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_4(<vscale x 16 x i1> %in) {392; CHECK-LABEL: extract_nxv2i1_nxv16i1_4:393; CHECK: // %bb.0:394; CHECK-NEXT: punpklo p0.h, p0.b395; CHECK-NEXT: punpkhi p0.h, p0.b396; CHECK-NEXT: punpklo p0.h, p0.b397; CHECK-NEXT: ret398 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 4)399 ret <vscale x 2 x i1> %res400}401 402define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_6(<vscale x 16 x i1> %in) {403; CHECK-LABEL: extract_nxv2i1_nxv16i1_6:404; CHECK: // %bb.0:405; CHECK-NEXT: punpklo p0.h, p0.b406; CHECK-NEXT: punpkhi p0.h, p0.b407; CHECK-NEXT: punpkhi p0.h, p0.b408; CHECK-NEXT: ret409 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 6)410 ret <vscale x 2 x i1> %res411}412 413define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_8(<vscale x 16 x i1> %in) {414; CHECK-LABEL: extract_nxv2i1_nxv16i1_8:415; CHECK: // %bb.0:416; CHECK-NEXT: punpkhi p0.h, p0.b417; CHECK-NEXT: punpklo p0.h, p0.b418; CHECK-NEXT: punpklo p0.h, p0.b419; CHECK-NEXT: ret420 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 8)421 ret <vscale x 2 x i1> %res422}423 424define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_10(<vscale x 16 x i1> %in) {425; CHECK-LABEL: extract_nxv2i1_nxv16i1_10:426; CHECK: // %bb.0:427; CHECK-NEXT: punpkhi p0.h, p0.b428; CHECK-NEXT: punpklo p0.h, p0.b429; CHECK-NEXT: punpkhi p0.h, p0.b430; CHECK-NEXT: ret431 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 10)432 ret <vscale x 2 x i1> %res433}434 435define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_12(<vscale x 16 x i1> %in) {436; CHECK-LABEL: extract_nxv2i1_nxv16i1_12:437; CHECK: // %bb.0:438; CHECK-NEXT: punpkhi p0.h, p0.b439; CHECK-NEXT: punpkhi p0.h, p0.b440; CHECK-NEXT: punpklo p0.h, p0.b441; CHECK-NEXT: ret442 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 12)443 ret <vscale x 2 x i1> %res444}445 446define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_14(<vscale x 16 x i1> %in) {447; CHECK-LABEL: extract_nxv2i1_nxv16i1_14:448; CHECK: // %bb.0:449; CHECK-NEXT: punpkhi p0.h, p0.b450; CHECK-NEXT: punpkhi p0.h, p0.b451; CHECK-NEXT: punpkhi p0.h, p0.b452; CHECK-NEXT: ret453 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 14)454 ret <vscale x 2 x i1> %res455}456 457;458; Extract i1 vector that needs promotion from one that needs widening.459;460define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_0(<vscale x 12 x i1> %in) {461; CHECK-LABEL: extract_nxv4i1_nxv12i1_0:462; CHECK: // %bb.0:463; CHECK-NEXT: punpklo p0.h, p0.b464; CHECK-NEXT: punpklo p0.h, p0.b465; CHECK-NEXT: ret466 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 0)467 ret <vscale x 4 x i1> %res468}469 470define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_4(<vscale x 12 x i1> %in) {471; CHECK-LABEL: extract_nxv4i1_nxv12i1_4:472; CHECK: // %bb.0:473; CHECK-NEXT: punpklo p0.h, p0.b474; CHECK-NEXT: punpkhi p0.h, p0.b475; CHECK-NEXT: ret476 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 4)477 ret <vscale x 4 x i1> %res478}479 480define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_8(<vscale x 12 x i1> %in) {481; CHECK-LABEL: extract_nxv4i1_nxv12i1_8:482; CHECK: // %bb.0:483; CHECK-NEXT: punpkhi p0.h, p0.b484; CHECK-NEXT: punpklo p0.h, p0.b485; CHECK-NEXT: ret486 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 8)487 ret <vscale x 4 x i1> %res488}489 490;491; Extract 1/8th i8 vector that needs promotion from legal type.492;493define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_0(<vscale x 16 x i8> %in) {494; CHECK-LABEL: extract_nxv2i8_nxv16i8_0:495; CHECK: // %bb.0:496; CHECK-NEXT: uunpklo z0.h, z0.b497; CHECK-NEXT: uunpklo z0.s, z0.h498; CHECK-NEXT: uunpklo z0.d, z0.s499; CHECK-NEXT: ret500 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 0)501 ret <vscale x 2 x i8> %res502}503 504define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_2(<vscale x 16 x i8> %in) {505; CHECK-LABEL: extract_nxv2i8_nxv16i8_2:506; CHECK: // %bb.0:507; CHECK-NEXT: uunpklo z0.h, z0.b508; CHECK-NEXT: uunpklo z0.s, z0.h509; CHECK-NEXT: uunpkhi z0.d, z0.s510; CHECK-NEXT: ret511 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 2)512 ret <vscale x 2 x i8> %res513}514 515define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_4(<vscale x 16 x i8> %in) {516; CHECK-LABEL: extract_nxv2i8_nxv16i8_4:517; CHECK: // %bb.0:518; CHECK-NEXT: uunpklo z0.h, z0.b519; CHECK-NEXT: uunpkhi z0.s, z0.h520; CHECK-NEXT: uunpklo z0.d, z0.s521; CHECK-NEXT: ret522 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 4)523 ret <vscale x 2 x i8> %res524}525 526define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_6(<vscale x 16 x i8> %in) {527; CHECK-LABEL: extract_nxv2i8_nxv16i8_6:528; CHECK: // %bb.0:529; CHECK-NEXT: uunpklo z0.h, z0.b530; CHECK-NEXT: uunpkhi z0.s, z0.h531; CHECK-NEXT: uunpkhi z0.d, z0.s532; CHECK-NEXT: ret533 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 6)534 ret <vscale x 2 x i8> %res535}536 537define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_8(<vscale x 16 x i8> %in) {538; CHECK-LABEL: extract_nxv2i8_nxv16i8_8:539; CHECK: // %bb.0:540; CHECK-NEXT: uunpkhi z0.h, z0.b541; CHECK-NEXT: uunpklo z0.s, z0.h542; CHECK-NEXT: uunpklo z0.d, z0.s543; CHECK-NEXT: ret544 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 8)545 ret <vscale x 2 x i8> %res546}547 548define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_10(<vscale x 16 x i8> %in) {549; CHECK-LABEL: extract_nxv2i8_nxv16i8_10:550; CHECK: // %bb.0:551; CHECK-NEXT: uunpkhi z0.h, z0.b552; CHECK-NEXT: uunpklo z0.s, z0.h553; CHECK-NEXT: uunpkhi z0.d, z0.s554; CHECK-NEXT: ret555 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 10)556 ret <vscale x 2 x i8> %res557}558 559define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_12(<vscale x 16 x i8> %in) {560; CHECK-LABEL: extract_nxv2i8_nxv16i8_12:561; CHECK: // %bb.0:562; CHECK-NEXT: uunpkhi z0.h, z0.b563; CHECK-NEXT: uunpkhi z0.s, z0.h564; CHECK-NEXT: uunpklo z0.d, z0.s565; CHECK-NEXT: ret566 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 12)567 ret <vscale x 2 x i8> %res568}569 570define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_14(<vscale x 16 x i8> %in) {571; CHECK-LABEL: extract_nxv2i8_nxv16i8_14:572; CHECK: // %bb.0:573; CHECK-NEXT: uunpkhi z0.h, z0.b574; CHECK-NEXT: uunpkhi z0.s, z0.h575; CHECK-NEXT: uunpkhi z0.d, z0.s576; CHECK-NEXT: ret577 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 14)578 ret <vscale x 2 x i8> %res579}580 581;582; Extract i8 vector that needs promotion from one that needs widening.583;584define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_0(<vscale x 12 x i8> %in) {585; CHECK-LABEL: extract_nxv4i8_nxv12i8_0:586; CHECK: // %bb.0:587; CHECK-NEXT: uunpklo z0.h, z0.b588; CHECK-NEXT: uunpklo z0.s, z0.h589; CHECK-NEXT: ret590 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 0)591 ret <vscale x 4 x i8> %res592}593 594define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_4(<vscale x 12 x i8> %in) {595; CHECK-LABEL: extract_nxv4i8_nxv12i8_4:596; CHECK: // %bb.0:597; CHECK-NEXT: uunpklo z0.h, z0.b598; CHECK-NEXT: uunpkhi z0.s, z0.h599; CHECK-NEXT: ret600 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 4)601 ret <vscale x 4 x i8> %res602}603 604define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_8(<vscale x 12 x i8> %in) {605; CHECK-LABEL: extract_nxv4i8_nxv12i8_8:606; CHECK: // %bb.0:607; CHECK-NEXT: uunpkhi z0.h, z0.b608; CHECK-NEXT: uunpklo z0.s, z0.h609; CHECK-NEXT: ret610 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 8)611 ret <vscale x 4 x i8> %res612}613 614;615; Extract i8 vector that needs both widening + promotion from one that needs widening.616; (nxv6i8 -> nxv8i8 -> nxv8i16)617;618define <vscale x 6 x i8> @extract_nxv6i8_nxv12i8_0(<vscale x 12 x i8> %in) {619; CHECK-LABEL: extract_nxv6i8_nxv12i8_0:620; CHECK: // %bb.0:621; CHECK-NEXT: uunpklo z0.h, z0.b622; CHECK-NEXT: ret623 %res = call <vscale x 6 x i8> @llvm.vector.extract.nxv6i8.nxv12i8(<vscale x 12 x i8> %in, i64 0)624 ret <vscale x 6 x i8> %res625}626 627define <vscale x 6 x i8> @extract_nxv6i8_nxv12i8_6(<vscale x 12 x i8> %in) {628; CHECK-LABEL: extract_nxv6i8_nxv12i8_6:629; CHECK: // %bb.0:630; CHECK-NEXT: uunpkhi z1.h, z0.b631; CHECK-NEXT: uunpklo z0.h, z0.b632; CHECK-NEXT: uunpklo z1.s, z1.h633; CHECK-NEXT: uunpkhi z0.s, z0.h634; CHECK-NEXT: uunpkhi z2.d, z1.s635; CHECK-NEXT: uunpklo z1.d, z1.s636; CHECK-NEXT: uunpkhi z0.d, z0.s637; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s638; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s639; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h640; CHECK-NEXT: ret641 %res = call <vscale x 6 x i8> @llvm.vector.extract.nxv6i8.nxv12i8(<vscale x 12 x i8> %in, i64 6)642 ret <vscale x 6 x i8> %res643}644 645;646; Extract half i8 vector that needs promotion from one that needs splitting.647;648define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_0(<vscale x 32 x i8> %in) {649; CHECK-LABEL: extract_nxv8i8_nxv32i8_0:650; CHECK: // %bb.0:651; CHECK-NEXT: uunpklo z0.h, z0.b652; CHECK-NEXT: ret653 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 0)654 ret <vscale x 8 x i8> %res655}656 657define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_8(<vscale x 32 x i8> %in) {658; CHECK-LABEL: extract_nxv8i8_nxv32i8_8:659; CHECK: // %bb.0:660; CHECK-NEXT: uunpkhi z0.h, z0.b661; CHECK-NEXT: ret662 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 8)663 ret <vscale x 8 x i8> %res664}665 666define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_16(<vscale x 32 x i8> %in) {667; CHECK-LABEL: extract_nxv8i8_nxv32i8_16:668; CHECK: // %bb.0:669; CHECK-NEXT: uunpklo z0.h, z1.b670; CHECK-NEXT: ret671 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 16)672 ret <vscale x 8 x i8> %res673}674 675define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_24(<vscale x 32 x i8> %in) {676; CHECK-LABEL: extract_nxv8i8_nxv32i8_24:677; CHECK: // %bb.0:678; CHECK-NEXT: uunpkhi z0.h, z1.b679; CHECK-NEXT: ret680 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 24)681 ret <vscale x 8 x i8> %res682}683 684;685; Extract half i8 vector that needs promotion from legal type.686;687define <vscale x 8 x i8> @extract_nxv8i8_nxv16i8_0(<vscale x 16 x i8> %in) {688; CHECK-LABEL: extract_nxv8i8_nxv16i8_0:689; CHECK: // %bb.0:690; CHECK-NEXT: uunpklo z0.h, z0.b691; CHECK-NEXT: ret692 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %in, i64 0)693 ret <vscale x 8 x i8> %res694}695 696define <vscale x 8 x i8> @extract_nxv8i8_nxv16i8_8(<vscale x 16 x i8> %in) {697; CHECK-LABEL: extract_nxv8i8_nxv16i8_8:698; CHECK: // %bb.0:699; CHECK-NEXT: uunpkhi z0.h, z0.b700; CHECK-NEXT: ret701 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %in, i64 8)702 ret <vscale x 8 x i8> %res703}704 705;706; Extract i8 vector that needs widening from one that needs widening.707;708define <vscale x 14 x i8> @extract_nxv14i8_nxv28i8_0(<vscale x 28 x i8> %in) {709; CHECK-LABEL: extract_nxv14i8_nxv28i8_0:710; CHECK: // %bb.0:711; CHECK-NEXT: ret712 %res = call <vscale x 14 x i8> @llvm.vector.extract.nxv14i8.nxv28i8(<vscale x 28 x i8> %in, i64 0)713 ret <vscale x 14 x i8> %res714}715 716define <vscale x 14 x i8> @extract_nxv14i8_nxv28i8_14(<vscale x 28 x i8> %in) {717; CHECK-LABEL: extract_nxv14i8_nxv28i8_14:718; CHECK: // %bb.0:719; CHECK-NEXT: uunpkhi z0.h, z0.b720; CHECK-NEXT: uunpklo z2.h, z1.b721; CHECK-NEXT: uunpkhi z1.h, z1.b722; CHECK-NEXT: uunpkhi z0.s, z0.h723; CHECK-NEXT: uunpklo z4.s, z2.h724; CHECK-NEXT: uunpkhi z2.s, z2.h725; CHECK-NEXT: uunpklo z1.s, z1.h726; CHECK-NEXT: uunpkhi z0.d, z0.s727; CHECK-NEXT: uunpklo z5.d, z4.s728; CHECK-NEXT: uunpkhi z4.d, z4.s729; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s730; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h731; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b732; CHECK-NEXT: uunpklo z0.h, z0.b733; CHECK-NEXT: uunpklo z3.s, z0.h734; CHECK-NEXT: uunpkhi z0.s, z0.h735; CHECK-NEXT: uunpklo z3.d, z3.s736; CHECK-NEXT: uzp1 z3.s, z3.s, z5.s737; CHECK-NEXT: uzp1 z0.h, z3.h, z0.h738; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b739; CHECK-NEXT: uunpklo z0.h, z0.b740; CHECK-NEXT: uunpkhi z3.s, z0.h741; CHECK-NEXT: uunpklo z0.s, z0.h742; CHECK-NEXT: uunpkhi z3.d, z3.s743; CHECK-NEXT: uzp1 z3.s, z4.s, z3.s744; CHECK-NEXT: uunpklo z4.d, z2.s745; CHECK-NEXT: uunpkhi z2.d, z2.s746; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h747; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b748; CHECK-NEXT: uunpklo z0.h, z0.b749; CHECK-NEXT: uunpkhi z3.s, z0.h750; CHECK-NEXT: uunpklo z0.s, z0.h751; CHECK-NEXT: uunpklo z3.d, z3.s752; CHECK-NEXT: uzp1 z3.s, z3.s, z4.s753; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h754; CHECK-NEXT: uzp1 z3.b, z0.b, z0.b755; CHECK-NEXT: uunpkhi z3.h, z3.b756; CHECK-NEXT: uunpklo z4.s, z3.h757; CHECK-NEXT: uunpkhi z3.s, z3.h758; CHECK-NEXT: uunpkhi z4.d, z4.s759; CHECK-NEXT: uzp1 z2.s, z2.s, z4.s760; CHECK-NEXT: uunpklo z4.d, z1.s761; CHECK-NEXT: uunpkhi z1.d, z1.s762; CHECK-NEXT: uzp1 z2.h, z2.h, z3.h763; CHECK-NEXT: uzp1 z2.b, z0.b, z2.b764; CHECK-NEXT: uunpkhi z2.h, z2.b765; CHECK-NEXT: uunpklo z3.s, z2.h766; CHECK-NEXT: uunpkhi z2.s, z2.h767; CHECK-NEXT: uunpklo z3.d, z3.s768; CHECK-NEXT: uzp1 z3.s, z3.s, z4.s769; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h770; CHECK-NEXT: uzp1 z2.b, z0.b, z2.b771; CHECK-NEXT: uunpkhi z2.h, z2.b772; CHECK-NEXT: uunpkhi z3.s, z2.h773; CHECK-NEXT: uunpklo z2.s, z2.h774; CHECK-NEXT: uunpkhi z3.d, z3.s775; CHECK-NEXT: uzp1 z1.s, z1.s, z3.s776; CHECK-NEXT: uzp1 z1.h, z2.h, z1.h777; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b778; CHECK-NEXT: ret779 %res = call <vscale x 14 x i8> @llvm.vector.extract.nxv14i8.nxv28i8(<vscale x 28 x i8> %in, i64 14)780 ret <vscale x 14 x i8> %res781}782 783;784; Extract 1/4th i8 vector that needs promotion from legal type.785;786define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_0(<vscale x 16 x i8> %in) {787; CHECK-LABEL: extract_nxv4i8_nxv16i8_0:788; CHECK: // %bb.0:789; CHECK-NEXT: uunpklo z0.h, z0.b790; CHECK-NEXT: uunpklo z0.s, z0.h791; CHECK-NEXT: ret792 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 0)793 ret <vscale x 4 x i8> %res794}795 796define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_4(<vscale x 16 x i8> %in) {797; CHECK-LABEL: extract_nxv4i8_nxv16i8_4:798; CHECK: // %bb.0:799; CHECK-NEXT: uunpklo z0.h, z0.b800; CHECK-NEXT: uunpkhi z0.s, z0.h801; CHECK-NEXT: ret802 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 4)803 ret <vscale x 4 x i8> %res804}805 806define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_8(<vscale x 16 x i8> %in) {807; CHECK-LABEL: extract_nxv4i8_nxv16i8_8:808; CHECK: // %bb.0:809; CHECK-NEXT: uunpkhi z0.h, z0.b810; CHECK-NEXT: uunpklo z0.s, z0.h811; CHECK-NEXT: ret812 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 8)813 ret <vscale x 4 x i8> %res814}815 816define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_12(<vscale x 16 x i8> %in) {817; CHECK-LABEL: extract_nxv4i8_nxv16i8_12:818; CHECK: // %bb.0:819; CHECK-NEXT: uunpkhi z0.h, z0.b820; CHECK-NEXT: uunpkhi z0.s, z0.h821; CHECK-NEXT: ret822 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 12)823 ret <vscale x 4 x i8> %res824}825 826;827; Extract f16 vector that needs promotion from one that needs widening.828;829define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_0(<vscale x 6 x half> %in) {830; CHECK-LABEL: extract_nxv2f16_nxv6f16_0:831; CHECK: // %bb.0:832; CHECK-NEXT: uunpklo z0.s, z0.h833; CHECK-NEXT: uunpklo z0.d, z0.s834; CHECK-NEXT: ret835 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 0)836 ret <vscale x 2 x half> %res837}838 839define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_2(<vscale x 6 x half> %in) {840; CHECK-LABEL: extract_nxv2f16_nxv6f16_2:841; CHECK: // %bb.0:842; CHECK-NEXT: uunpklo z0.s, z0.h843; CHECK-NEXT: uunpkhi z0.d, z0.s844; CHECK-NEXT: ret845 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 2)846 ret <vscale x 2 x half> %res847}848 849define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_4(<vscale x 6 x half> %in) {850; CHECK-LABEL: extract_nxv2f16_nxv6f16_4:851; CHECK: // %bb.0:852; CHECK-NEXT: uunpkhi z0.s, z0.h853; CHECK-NEXT: uunpklo z0.d, z0.s854; CHECK-NEXT: ret855 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 4)856 ret <vscale x 2 x half> %res857}858 859;860; Extract half f16 vector that needs promotion from legal type.861;862define <vscale x 4 x half> @extract_nxv4f16_nxv8f16_0(<vscale x 8 x half> %in) {863; CHECK-LABEL: extract_nxv4f16_nxv8f16_0:864; CHECK: // %bb.0:865; CHECK-NEXT: uunpklo z0.s, z0.h866; CHECK-NEXT: ret867 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %in, i64 0)868 ret <vscale x 4 x half> %res869}870 871define <vscale x 4 x half> @extract_nxv4f16_nxv8f16_4(<vscale x 8 x half> %in) {872; CHECK-LABEL: extract_nxv4f16_nxv8f16_4:873; CHECK: // %bb.0:874; CHECK-NEXT: uunpkhi z0.s, z0.h875; CHECK-NEXT: ret876 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %in, i64 4)877 ret <vscale x 4 x half> %res878}879 880;881; Extract f16 vector that needs widening from one that needs widening.882;883define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_0(<vscale x 12 x half> %in) {884; CHECK-LABEL: extract_nxv6f16_nxv12f16_0:885; CHECK: // %bb.0:886; CHECK-NEXT: ret887 %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 0)888 ret <vscale x 6 x half> %res889}890 891define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) {892; CHECK-LABEL: extract_nxv6f16_nxv12f16_6:893; CHECK: // %bb.0:894; CHECK-NEXT: uunpklo z1.s, z1.h895; CHECK-NEXT: uunpkhi z0.s, z0.h896; CHECK-NEXT: uunpkhi z2.d, z1.s897; CHECK-NEXT: uunpklo z1.d, z1.s898; CHECK-NEXT: uunpkhi z0.d, z0.s899; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s900; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s901; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h902; CHECK-NEXT: ret903 %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6)904 ret <vscale x 6 x half> %res905}906 907;908; Extract half f16 vector that needs promotion from one that needs splitting.909;910define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_0(<vscale x 16 x half> %in) {911; CHECK-LABEL: extract_nxv4f16_nxv16f16_0:912; CHECK: // %bb.0:913; CHECK-NEXT: uunpklo z0.s, z0.h914; CHECK-NEXT: ret915 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 0)916 ret <vscale x 4 x half> %res917}918 919define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_4(<vscale x 16 x half> %in) {920; CHECK-LABEL: extract_nxv4f16_nxv16f16_4:921; CHECK: // %bb.0:922; CHECK-NEXT: uunpkhi z0.s, z0.h923; CHECK-NEXT: ret924 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 4)925 ret <vscale x 4 x half> %res926}927 928define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_8(<vscale x 16 x half> %in) {929; CHECK-LABEL: extract_nxv4f16_nxv16f16_8:930; CHECK: // %bb.0:931; CHECK-NEXT: uunpklo z0.s, z1.h932; CHECK-NEXT: ret933 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 8)934 ret <vscale x 4 x half> %res935}936 937define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_12(<vscale x 16 x half> %in) {938; CHECK-LABEL: extract_nxv4f16_nxv16f16_12:939; CHECK: // %bb.0:940; CHECK-NEXT: uunpkhi z0.s, z1.h941; CHECK-NEXT: ret942 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 12)943 ret <vscale x 4 x half> %res944}945 946;947; Extract 1/4th f16 vector that needs promotion from legal type.948;949define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_0(<vscale x 8 x half> %in) {950; CHECK-LABEL: extract_nxv2f16_nxv8f16_0:951; CHECK: // %bb.0:952; CHECK-NEXT: uunpklo z0.s, z0.h953; CHECK-NEXT: uunpklo z0.d, z0.s954; CHECK-NEXT: ret955 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 0)956 ret <vscale x 2 x half> %res957}958 959define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_2(<vscale x 8 x half> %in) {960; CHECK-LABEL: extract_nxv2f16_nxv8f16_2:961; CHECK: // %bb.0:962; CHECK-NEXT: uunpklo z0.s, z0.h963; CHECK-NEXT: uunpkhi z0.d, z0.s964; CHECK-NEXT: ret965 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 2)966 ret <vscale x 2 x half> %res967}968 969define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_4(<vscale x 8 x half> %in) {970; CHECK-LABEL: extract_nxv2f16_nxv8f16_4:971; CHECK: // %bb.0:972; CHECK-NEXT: uunpkhi z0.s, z0.h973; CHECK-NEXT: uunpklo z0.d, z0.s974; CHECK-NEXT: ret975 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 4)976 ret <vscale x 2 x half> %res977}978 979define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_6(<vscale x 8 x half> %in) {980; CHECK-LABEL: extract_nxv2f16_nxv8f16_6:981; CHECK: // %bb.0:982; CHECK-NEXT: uunpkhi z0.s, z0.h983; CHECK-NEXT: uunpkhi z0.d, z0.s984; CHECK-NEXT: ret985 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 6)986 ret <vscale x 2 x half> %res987}988 989;990; Extract half bf16 vector that needs promotion from legal type.991;992define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv8bf16_0(<vscale x 8 x bfloat> %in) {993; CHECK-LABEL: extract_nxv4bf16_nxv8bf16_0:994; CHECK: // %bb.0:995; CHECK-NEXT: uunpklo z0.s, z0.h996; CHECK-NEXT: ret997 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 0)998 ret <vscale x 4 x bfloat> %res999}1000 1001define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv8bf16_4(<vscale x 8 x bfloat> %in) {1002; CHECK-LABEL: extract_nxv4bf16_nxv8bf16_4:1003; CHECK: // %bb.0:1004; CHECK-NEXT: uunpkhi z0.s, z0.h1005; CHECK-NEXT: ret1006 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 4)1007 ret <vscale x 4 x bfloat> %res1008}1009 1010;1011; Extract bf16 vector that needs widening from one that needs widening.1012;1013define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_0(<vscale x 12 x bfloat> %in) {1014; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_0:1015; CHECK: // %bb.0:1016; CHECK-NEXT: ret1017 %res = call <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 0)1018 ret <vscale x 6 x bfloat> %res1019}1020 1021define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_6(<vscale x 12 x bfloat> %in) {1022; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_6:1023; CHECK: // %bb.0:1024; CHECK-NEXT: uunpklo z1.s, z1.h1025; CHECK-NEXT: uunpkhi z0.s, z0.h1026; CHECK-NEXT: uunpkhi z2.d, z1.s1027; CHECK-NEXT: uunpklo z1.d, z1.s1028; CHECK-NEXT: uunpkhi z0.d, z0.s1029; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s1030; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s1031; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h1032; CHECK-NEXT: ret1033 %res = call <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 6)1034 ret <vscale x 6 x bfloat> %res1035}1036 1037;1038; Extract bf16 vector that needs promotion from one that needs widening.1039;1040define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_0(<vscale x 6 x bfloat> %in) {1041; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_0:1042; CHECK: // %bb.0:1043; CHECK-NEXT: uunpklo z0.s, z0.h1044; CHECK-NEXT: uunpklo z0.d, z0.s1045; CHECK-NEXT: ret1046 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 0)1047 ret <vscale x 2 x bfloat> %res1048}1049 1050define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_2(<vscale x 6 x bfloat> %in) {1051; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_2:1052; CHECK: // %bb.0:1053; CHECK-NEXT: uunpklo z0.s, z0.h1054; CHECK-NEXT: uunpkhi z0.d, z0.s1055; CHECK-NEXT: ret1056 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 2)1057 ret <vscale x 2 x bfloat> %res1058}1059 1060define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_4(<vscale x 6 x bfloat> %in) {1061; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_4:1062; CHECK: // %bb.0:1063; CHECK-NEXT: uunpkhi z0.s, z0.h1064; CHECK-NEXT: uunpklo z0.d, z0.s1065; CHECK-NEXT: ret1066 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 4)1067 ret <vscale x 2 x bfloat> %res1068}1069 1070;1071; Extract 1/4th bf16 vector that needs promotion from legal type.1072;1073define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_0(<vscale x 8 x bfloat> %in) {1074; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_0:1075; CHECK: // %bb.0:1076; CHECK-NEXT: uunpklo z0.s, z0.h1077; CHECK-NEXT: uunpklo z0.d, z0.s1078; CHECK-NEXT: ret1079 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 0)1080 ret <vscale x 2 x bfloat> %res1081}1082 1083define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_2(<vscale x 8 x bfloat> %in) {1084; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_2:1085; CHECK: // %bb.0:1086; CHECK-NEXT: uunpklo z0.s, z0.h1087; CHECK-NEXT: uunpkhi z0.d, z0.s1088; CHECK-NEXT: ret1089 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 2)1090 ret <vscale x 2 x bfloat> %res1091}1092 1093define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_4(<vscale x 8 x bfloat> %in) {1094; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_4:1095; CHECK: // %bb.0:1096; CHECK-NEXT: uunpkhi z0.s, z0.h1097; CHECK-NEXT: uunpklo z0.d, z0.s1098; CHECK-NEXT: ret1099 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 4)1100 ret <vscale x 2 x bfloat> %res1101}1102 1103define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_6(<vscale x 8 x bfloat> %in) {1104; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_6:1105; CHECK: // %bb.0:1106; CHECK-NEXT: uunpkhi z0.s, z0.h1107; CHECK-NEXT: uunpkhi z0.d, z0.s1108; CHECK-NEXT: ret1109 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 6)1110 ret <vscale x 2 x bfloat> %res1111}1112 1113;1114; Extract half bf16 vector that needs promotion from one that needs splitting.1115;1116define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_0(<vscale x 16 x bfloat> %in) {1117; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_0:1118; CHECK: // %bb.0:1119; CHECK-NEXT: uunpklo z0.s, z0.h1120; CHECK-NEXT: ret1121 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 0)1122 ret <vscale x 4 x bfloat> %res1123}1124 1125define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_4(<vscale x 16 x bfloat> %in) {1126; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_4:1127; CHECK: // %bb.0:1128; CHECK-NEXT: uunpkhi z0.s, z0.h1129; CHECK-NEXT: ret1130 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 4)1131 ret <vscale x 4 x bfloat> %res1132}1133 1134define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_8(<vscale x 16 x bfloat> %in) {1135; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_8:1136; CHECK: // %bb.0:1137; CHECK-NEXT: uunpklo z0.s, z1.h1138; CHECK-NEXT: ret1139 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 8)1140 ret <vscale x 4 x bfloat> %res1141}1142 1143define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_12(<vscale x 16 x bfloat> %in) {1144; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_12:1145; CHECK: // %bb.0:1146; CHECK-NEXT: uunpkhi z0.s, z1.h1147; CHECK-NEXT: ret1148 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 12)1149 ret <vscale x 4 x bfloat> %res1150}1151 1152;1153; Extract from a splat1154;1155define <vscale x 2 x float> @extract_nxv2f32_nxv4f32_splat(float %f) {1156; CHECK-LABEL: extract_nxv2f32_nxv4f32_splat:1157; CHECK: // %bb.0:1158; CHECK-NEXT: // kill: def $s0 killed $s0 def $z01159; CHECK-NEXT: mov z0.s, s01160; CHECK-NEXT: ret1161 %ins = insertelement <vscale x 4 x float> poison, float %f, i32 01162 %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer1163 %ext = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0)1164 ret <vscale x 2 x float> %ext1165}1166 1167define <vscale x 2 x float> @extract_nxv2f32_nxv4f32_splat_const() {1168; CHECK-LABEL: extract_nxv2f32_nxv4f32_splat_const:1169; CHECK: // %bb.0:1170; CHECK-NEXT: fmov z0.s, #1.000000001171; CHECK-NEXT: ret1172 %ext = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> splat(float 1.0), i64 0)1173 ret <vscale x 2 x float> %ext1174}1175 1176define <vscale x 4 x i32> @extract_nxv4i32_nxv8i32_splat_const() {1177; CHECK-LABEL: extract_nxv4i32_nxv8i32_splat_const:1178; CHECK: // %bb.0:1179; CHECK-NEXT: mov z0.s, #1 // =0x11180; CHECK-NEXT: ret1181 %ext = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> splat(i32 1), i64 0)1182 ret <vscale x 4 x i32> %ext1183}1184 1185define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_all_ones() {1186; CHECK-LABEL: extract_nxv2i1_nxv16i1_all_ones:1187; CHECK: // %bb.0:1188; CHECK-NEXT: ptrue p0.d1189; CHECK-NEXT: ret1190 %ext = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> splat(i1 true), i64 0)1191 ret <vscale x 2 x i1> %ext1192}1193 1194define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_all_zero() {1195; CHECK-LABEL: extract_nxv2i1_nxv16i1_all_zero:1196; CHECK: // %bb.0:1197; CHECK-NEXT: pfalse p0.b1198; CHECK-NEXT: ret1199 %ext = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> zeroinitializer, i64 0)1200 ret <vscale x 2 x i1> %ext1201}1202 1203;1204; Extract nxv1i1 type from: nxv2i11205;1206 1207define <vscale x 1 x i1> @extract_nxv1i1_nxv2i1_0(<vscale x 2 x i1> %in) {1208; CHECK-LABEL: extract_nxv1i1_nxv2i1_0:1209; CHECK: // %bb.0:1210; CHECK-NEXT: punpklo p0.h, p0.b1211; CHECK-NEXT: ret1212 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv2i1(<vscale x 2 x i1> %in, i64 0)1213 ret <vscale x 1 x i1> %res1214}1215 1216define <vscale x 1 x i1> @extract_nxv1i1_nxv2i1_1(<vscale x 2 x i1> %in) {1217; CHECK-LABEL: extract_nxv1i1_nxv2i1_1:1218; CHECK: // %bb.0:1219; CHECK-NEXT: punpkhi p0.h, p0.b1220; CHECK-NEXT: ret1221 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv2i1(<vscale x 2 x i1> %in, i64 1)1222 ret <vscale x 1 x i1> %res1223}1224 1225;1226; Extract nxv1i1 type from: nxv4i11227;1228 1229define <vscale x 1 x i1> @extract_nxv1i1_nxv4i1_0(<vscale x 4 x i1> %in) {1230; CHECK-LABEL: extract_nxv1i1_nxv4i1_0:1231; CHECK: // %bb.0:1232; CHECK-NEXT: punpklo p0.h, p0.b1233; CHECK-NEXT: punpklo p0.h, p0.b1234; CHECK-NEXT: ret1235 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv4i1(<vscale x 4 x i1> %in, i64 0)1236 ret <vscale x 1 x i1> %res1237}1238 1239define <vscale x 1 x i1> @extract_nxv1i1_nxv4i1_1(<vscale x 4 x i1> %in) {1240; CHECK-LABEL: extract_nxv1i1_nxv4i1_1:1241; CHECK: // %bb.0:1242; CHECK-NEXT: punpklo p0.h, p0.b1243; CHECK-NEXT: punpkhi p0.h, p0.b1244; CHECK-NEXT: ret1245 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv4i1(<vscale x 4 x i1> %in, i64 1)1246 ret <vscale x 1 x i1> %res1247}1248 1249define <vscale x 1 x i1> @extract_nxv1i1_nxv4i1_2(<vscale x 4 x i1> %in) {1250; CHECK-LABEL: extract_nxv1i1_nxv4i1_2:1251; CHECK: // %bb.0:1252; CHECK-NEXT: punpkhi p0.h, p0.b1253; CHECK-NEXT: punpklo p0.h, p0.b1254; CHECK-NEXT: ret1255 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv4i1(<vscale x 4 x i1> %in, i64 2)1256 ret <vscale x 1 x i1> %res1257}1258 1259define <vscale x 1 x i1> @extract_nxv1i1_nxv4i1_3(<vscale x 4 x i1> %in) {1260; CHECK-LABEL: extract_nxv1i1_nxv4i1_3:1261; CHECK: // %bb.0:1262; CHECK-NEXT: punpkhi p0.h, p0.b1263; CHECK-NEXT: punpkhi p0.h, p0.b1264; CHECK-NEXT: ret1265 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv4i1(<vscale x 4 x i1> %in, i64 3)1266 ret <vscale x 1 x i1> %res1267}1268 1269;1270; Extract nxv1i1 type from: nxv8i11271;1272 1273define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_0(<vscale x 8 x i1> %in) {1274; CHECK-LABEL: extract_nxv1i1_nxv8i1_0:1275; CHECK: // %bb.0:1276; CHECK-NEXT: punpklo p0.h, p0.b1277; CHECK-NEXT: punpklo p0.h, p0.b1278; CHECK-NEXT: punpklo p0.h, p0.b1279; CHECK-NEXT: ret1280 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 0)1281 ret <vscale x 1 x i1> %res1282}1283 1284define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_1(<vscale x 8 x i1> %in) {1285; CHECK-LABEL: extract_nxv1i1_nxv8i1_1:1286; CHECK: // %bb.0:1287; CHECK-NEXT: punpklo p0.h, p0.b1288; CHECK-NEXT: punpklo p0.h, p0.b1289; CHECK-NEXT: punpkhi p0.h, p0.b1290; CHECK-NEXT: ret1291 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 1)1292 ret <vscale x 1 x i1> %res1293}1294 1295define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_2(<vscale x 8 x i1> %in) {1296; CHECK-LABEL: extract_nxv1i1_nxv8i1_2:1297; CHECK: // %bb.0:1298; CHECK-NEXT: punpklo p0.h, p0.b1299; CHECK-NEXT: punpkhi p0.h, p0.b1300; CHECK-NEXT: punpklo p0.h, p0.b1301; CHECK-NEXT: ret1302 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 2)1303 ret <vscale x 1 x i1> %res1304}1305 1306define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_3(<vscale x 8 x i1> %in) {1307; CHECK-LABEL: extract_nxv1i1_nxv8i1_3:1308; CHECK: // %bb.0:1309; CHECK-NEXT: punpklo p0.h, p0.b1310; CHECK-NEXT: punpkhi p0.h, p0.b1311; CHECK-NEXT: punpkhi p0.h, p0.b1312; CHECK-NEXT: ret1313 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 3)1314 ret <vscale x 1 x i1> %res1315}1316 1317define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_4(<vscale x 8 x i1> %in) {1318; CHECK-LABEL: extract_nxv1i1_nxv8i1_4:1319; CHECK: // %bb.0:1320; CHECK-NEXT: punpkhi p0.h, p0.b1321; CHECK-NEXT: punpklo p0.h, p0.b1322; CHECK-NEXT: punpklo p0.h, p0.b1323; CHECK-NEXT: ret1324 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 4)1325 ret <vscale x 1 x i1> %res1326}1327 1328define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_5(<vscale x 8 x i1> %in) {1329; CHECK-LABEL: extract_nxv1i1_nxv8i1_5:1330; CHECK: // %bb.0:1331; CHECK-NEXT: punpkhi p0.h, p0.b1332; CHECK-NEXT: punpklo p0.h, p0.b1333; CHECK-NEXT: punpkhi p0.h, p0.b1334; CHECK-NEXT: ret1335 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 5)1336 ret <vscale x 1 x i1> %res1337}1338 1339define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_6(<vscale x 8 x i1> %in) {1340; CHECK-LABEL: extract_nxv1i1_nxv8i1_6:1341; CHECK: // %bb.0:1342; CHECK-NEXT: punpkhi p0.h, p0.b1343; CHECK-NEXT: punpkhi p0.h, p0.b1344; CHECK-NEXT: punpklo p0.h, p0.b1345; CHECK-NEXT: ret1346 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 6)1347 ret <vscale x 1 x i1> %res1348}1349 1350define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_7(<vscale x 8 x i1> %in) {1351; CHECK-LABEL: extract_nxv1i1_nxv8i1_7:1352; CHECK: // %bb.0:1353; CHECK-NEXT: punpkhi p0.h, p0.b1354; CHECK-NEXT: punpkhi p0.h, p0.b1355; CHECK-NEXT: punpkhi p0.h, p0.b1356; CHECK-NEXT: ret1357 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 7)1358 ret <vscale x 1 x i1> %res1359}1360 1361 1362;1363; Extract nxv1i1 type from: nxv16i11364;1365 1366define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_0(<vscale x 16 x i1> %in) {1367; CHECK-LABEL: extract_nxv1i1_nxv16i1_0:1368; CHECK: // %bb.0:1369; CHECK-NEXT: punpklo p0.h, p0.b1370; CHECK-NEXT: punpklo p0.h, p0.b1371; CHECK-NEXT: punpklo p0.h, p0.b1372; CHECK-NEXT: punpklo p0.h, p0.b1373; CHECK-NEXT: ret1374 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 0)1375 ret <vscale x 1 x i1> %res1376}1377 1378define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_1(<vscale x 16 x i1> %in) {1379; CHECK-LABEL: extract_nxv1i1_nxv16i1_1:1380; CHECK: // %bb.0:1381; CHECK-NEXT: punpklo p0.h, p0.b1382; CHECK-NEXT: punpklo p0.h, p0.b1383; CHECK-NEXT: punpklo p0.h, p0.b1384; CHECK-NEXT: punpkhi p0.h, p0.b1385; CHECK-NEXT: ret1386 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 1)1387 ret <vscale x 1 x i1> %res1388}1389 1390define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_2(<vscale x 16 x i1> %in) {1391; CHECK-LABEL: extract_nxv1i1_nxv16i1_2:1392; CHECK: // %bb.0:1393; CHECK-NEXT: punpklo p0.h, p0.b1394; CHECK-NEXT: punpklo p0.h, p0.b1395; CHECK-NEXT: punpkhi p0.h, p0.b1396; CHECK-NEXT: punpklo p0.h, p0.b1397; CHECK-NEXT: ret1398 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 2)1399 ret <vscale x 1 x i1> %res1400}1401 1402define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_3(<vscale x 16 x i1> %in) {1403; CHECK-LABEL: extract_nxv1i1_nxv16i1_3:1404; CHECK: // %bb.0:1405; CHECK-NEXT: punpklo p0.h, p0.b1406; CHECK-NEXT: punpklo p0.h, p0.b1407; CHECK-NEXT: punpkhi p0.h, p0.b1408; CHECK-NEXT: punpkhi p0.h, p0.b1409; CHECK-NEXT: ret1410 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 3)1411 ret <vscale x 1 x i1> %res1412}1413 1414define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_4(<vscale x 16 x i1> %in) {1415; CHECK-LABEL: extract_nxv1i1_nxv16i1_4:1416; CHECK: // %bb.0:1417; CHECK-NEXT: punpklo p0.h, p0.b1418; CHECK-NEXT: punpkhi p0.h, p0.b1419; CHECK-NEXT: punpklo p0.h, p0.b1420; CHECK-NEXT: punpklo p0.h, p0.b1421; CHECK-NEXT: ret1422 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 4)1423 ret <vscale x 1 x i1> %res1424}1425 1426define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_5(<vscale x 16 x i1> %in) {1427; CHECK-LABEL: extract_nxv1i1_nxv16i1_5:1428; CHECK: // %bb.0:1429; CHECK-NEXT: punpklo p0.h, p0.b1430; CHECK-NEXT: punpkhi p0.h, p0.b1431; CHECK-NEXT: punpklo p0.h, p0.b1432; CHECK-NEXT: punpkhi p0.h, p0.b1433; CHECK-NEXT: ret1434 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 5)1435 ret <vscale x 1 x i1> %res1436}1437 1438define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_6(<vscale x 16 x i1> %in) {1439; CHECK-LABEL: extract_nxv1i1_nxv16i1_6:1440; CHECK: // %bb.0:1441; CHECK-NEXT: punpklo p0.h, p0.b1442; CHECK-NEXT: punpkhi p0.h, p0.b1443; CHECK-NEXT: punpkhi p0.h, p0.b1444; CHECK-NEXT: punpklo p0.h, p0.b1445; CHECK-NEXT: ret1446 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 6)1447 ret <vscale x 1 x i1> %res1448}1449 1450define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_7(<vscale x 16 x i1> %in) {1451; CHECK-LABEL: extract_nxv1i1_nxv16i1_7:1452; CHECK: // %bb.0:1453; CHECK-NEXT: punpklo p0.h, p0.b1454; CHECK-NEXT: punpkhi p0.h, p0.b1455; CHECK-NEXT: punpkhi p0.h, p0.b1456; CHECK-NEXT: punpkhi p0.h, p0.b1457; CHECK-NEXT: ret1458 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 7)1459 ret <vscale x 1 x i1> %res1460}1461 1462define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_8(<vscale x 16 x i1> %in) {1463; CHECK-LABEL: extract_nxv1i1_nxv16i1_8:1464; CHECK: // %bb.0:1465; CHECK-NEXT: punpkhi p0.h, p0.b1466; CHECK-NEXT: punpklo p0.h, p0.b1467; CHECK-NEXT: punpklo p0.h, p0.b1468; CHECK-NEXT: punpklo p0.h, p0.b1469; CHECK-NEXT: ret1470 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 8)1471 ret <vscale x 1 x i1> %res1472}1473 1474define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_9(<vscale x 16 x i1> %in) {1475; CHECK-LABEL: extract_nxv1i1_nxv16i1_9:1476; CHECK: // %bb.0:1477; CHECK-NEXT: punpkhi p0.h, p0.b1478; CHECK-NEXT: punpklo p0.h, p0.b1479; CHECK-NEXT: punpklo p0.h, p0.b1480; CHECK-NEXT: punpkhi p0.h, p0.b1481; CHECK-NEXT: ret1482 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 9)1483 ret <vscale x 1 x i1> %res1484}1485 1486define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_10(<vscale x 16 x i1> %in) {1487; CHECK-LABEL: extract_nxv1i1_nxv16i1_10:1488; CHECK: // %bb.0:1489; CHECK-NEXT: punpkhi p0.h, p0.b1490; CHECK-NEXT: punpklo p0.h, p0.b1491; CHECK-NEXT: punpkhi p0.h, p0.b1492; CHECK-NEXT: punpklo p0.h, p0.b1493; CHECK-NEXT: ret1494 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 10)1495 ret <vscale x 1 x i1> %res1496}1497 1498define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_11(<vscale x 16 x i1> %in) {1499; CHECK-LABEL: extract_nxv1i1_nxv16i1_11:1500; CHECK: // %bb.0:1501; CHECK-NEXT: punpkhi p0.h, p0.b1502; CHECK-NEXT: punpklo p0.h, p0.b1503; CHECK-NEXT: punpkhi p0.h, p0.b1504; CHECK-NEXT: punpkhi p0.h, p0.b1505; CHECK-NEXT: ret1506 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 11)1507 ret <vscale x 1 x i1> %res1508}1509 1510define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_12(<vscale x 16 x i1> %in) {1511; CHECK-LABEL: extract_nxv1i1_nxv16i1_12:1512; CHECK: // %bb.0:1513; CHECK-NEXT: punpkhi p0.h, p0.b1514; CHECK-NEXT: punpkhi p0.h, p0.b1515; CHECK-NEXT: punpklo p0.h, p0.b1516; CHECK-NEXT: punpklo p0.h, p0.b1517; CHECK-NEXT: ret1518 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 12)1519 ret <vscale x 1 x i1> %res1520}1521 1522define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_13(<vscale x 16 x i1> %in) {1523; CHECK-LABEL: extract_nxv1i1_nxv16i1_13:1524; CHECK: // %bb.0:1525; CHECK-NEXT: punpkhi p0.h, p0.b1526; CHECK-NEXT: punpkhi p0.h, p0.b1527; CHECK-NEXT: punpklo p0.h, p0.b1528; CHECK-NEXT: punpkhi p0.h, p0.b1529; CHECK-NEXT: ret1530 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 13)1531 ret <vscale x 1 x i1> %res1532}1533 1534define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_14(<vscale x 16 x i1> %in) {1535; CHECK-LABEL: extract_nxv1i1_nxv16i1_14:1536; CHECK: // %bb.0:1537; CHECK-NEXT: punpkhi p0.h, p0.b1538; CHECK-NEXT: punpkhi p0.h, p0.b1539; CHECK-NEXT: punpkhi p0.h, p0.b1540; CHECK-NEXT: punpklo p0.h, p0.b1541; CHECK-NEXT: ret1542 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 14)1543 ret <vscale x 1 x i1> %res1544}1545 1546define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_15(<vscale x 16 x i1> %in) {1547; CHECK-LABEL: extract_nxv1i1_nxv16i1_15:1548; CHECK: // %bb.0:1549; CHECK-NEXT: punpkhi p0.h, p0.b1550; CHECK-NEXT: punpkhi p0.h, p0.b1551; CHECK-NEXT: punpkhi p0.h, p0.b1552; CHECK-NEXT: punpkhi p0.h, p0.b1553; CHECK-NEXT: ret1554 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 15)1555 ret <vscale x 1 x i1> %res1556}1557