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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; FP_EXTEND6;7 8define <vscale x 2 x float> @fcvts_nxv2f16(<vscale x 2 x half> %a) {9; CHECK-LABEL: fcvts_nxv2f16:10; CHECK: // %bb.0:11; CHECK-NEXT: ptrue p0.d12; CHECK-NEXT: fcvt z0.s, p0/m, z0.h13; CHECK-NEXT: ret14 %res = fpext <vscale x 2 x half> %a to <vscale x 2 x float>15 ret <vscale x 2 x float> %res16}17 18define <vscale x 3 x float> @fcvts_nxv3f16(<vscale x 3 x half> %a) {19; CHECK-LABEL: fcvts_nxv3f16:20; CHECK: // %bb.0:21; CHECK-NEXT: ptrue p0.s22; CHECK-NEXT: fcvt z0.s, p0/m, z0.h23; CHECK-NEXT: ret24 %res = fpext <vscale x 3 x half> %a to <vscale x 3 x float>25 ret <vscale x 3 x float> %res26}27 28define <vscale x 4 x float> @fcvts_nxv4f16(<vscale x 4 x half> %a) {29; CHECK-LABEL: fcvts_nxv4f16:30; CHECK: // %bb.0:31; CHECK-NEXT: ptrue p0.s32; CHECK-NEXT: fcvt z0.s, p0/m, z0.h33; CHECK-NEXT: ret34 %res = fpext <vscale x 4 x half> %a to <vscale x 4 x float>35 ret <vscale x 4 x float> %res36}37 38define <vscale x 2 x double> @fcvtd_nxv2f16(<vscale x 2 x half> %a) {39; CHECK-LABEL: fcvtd_nxv2f16:40; CHECK: // %bb.0:41; CHECK-NEXT: ptrue p0.d42; CHECK-NEXT: fcvt z0.d, p0/m, z0.h43; CHECK-NEXT: ret44 %res = fpext <vscale x 2 x half> %a to <vscale x 2 x double>45 ret <vscale x 2 x double> %res46}47 48define <vscale x 2 x double> @fcvtd_nxv2f32(<vscale x 2 x float> %a) {49; CHECK-LABEL: fcvtd_nxv2f32:50; CHECK: // %bb.0:51; CHECK-NEXT: ptrue p0.d52; CHECK-NEXT: fcvt z0.d, p0/m, z0.s53; CHECK-NEXT: ret54 %res = fpext <vscale x 2 x float> %a to <vscale x 2 x double>55 ret <vscale x 2 x double> %res56}57 58;59; FP_ROUND60;61 62define <vscale x 2 x half> @fcvth_nxv2f32(<vscale x 2 x float> %a) {63; CHECK-LABEL: fcvth_nxv2f32:64; CHECK: // %bb.0:65; CHECK-NEXT: ptrue p0.d66; CHECK-NEXT: fcvt z0.h, p0/m, z0.s67; CHECK-NEXT: ret68 %res = fptrunc <vscale x 2 x float> %a to <vscale x 2 x half>69 ret <vscale x 2 x half> %res70}71 72define <vscale x 3 x half> @fcvth_nxv3f32(<vscale x 3 x float> %a) {73; CHECK-LABEL: fcvth_nxv3f32:74; CHECK: // %bb.0:75; CHECK-NEXT: ptrue p0.s76; CHECK-NEXT: fcvt z0.h, p0/m, z0.s77; CHECK-NEXT: ret78 %res = fptrunc <vscale x 3 x float> %a to <vscale x 3 x half>79 ret <vscale x 3 x half> %res80}81 82define <vscale x 4 x half> @fcvth_nxv4f32(<vscale x 4 x float> %a) {83; CHECK-LABEL: fcvth_nxv4f32:84; CHECK: // %bb.0:85; CHECK-NEXT: ptrue p0.s86; CHECK-NEXT: fcvt z0.h, p0/m, z0.s87; CHECK-NEXT: ret88 %res = fptrunc <vscale x 4 x float> %a to <vscale x 4 x half>89 ret <vscale x 4 x half> %res90}91 92define <vscale x 2 x half> @fcvth_nxv2f64(<vscale x 2 x double> %a) {93; CHECK-LABEL: fcvth_nxv2f64:94; CHECK: // %bb.0:95; CHECK-NEXT: ptrue p0.d96; CHECK-NEXT: fcvt z0.h, p0/m, z0.d97; CHECK-NEXT: ret98 %res = fptrunc <vscale x 2 x double> %a to <vscale x 2 x half>99 ret <vscale x 2 x half> %res100}101 102define <vscale x 2 x float> @fcvts_nxv2f64(<vscale x 2 x double> %a) {103; CHECK-LABEL: fcvts_nxv2f64:104; CHECK: // %bb.0:105; CHECK-NEXT: ptrue p0.d106; CHECK-NEXT: fcvt z0.s, p0/m, z0.d107; CHECK-NEXT: ret108 %res = fptrunc <vscale x 2 x double> %a to <vscale x 2 x float>109 ret <vscale x 2 x float> %res110}111 112;113; FP_TO_SINT114;115 116define <vscale x 2 x i1> @fcvtzs_nxv2f16_to_nxv2i1(<vscale x 2 x half> %a) {117; CHECK-LABEL: fcvtzs_nxv2f16_to_nxv2i1:118; CHECK: // %bb.0:119; CHECK-NEXT: ptrue p0.d120; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h121; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0122; CHECK-NEXT: ret123 %res = fptosi <vscale x 2 x half> %a to <vscale x 2 x i1>124 ret <vscale x 2 x i1> %res125}126 127define <vscale x 2 x i1> @fcvtzs_nxv2f32_to_nxv2i1(<vscale x 2 x float> %a) {128; CHECK-LABEL: fcvtzs_nxv2f32_to_nxv2i1:129; CHECK: // %bb.0:130; CHECK-NEXT: ptrue p0.d131; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s132; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0133; CHECK-NEXT: ret134 %res = fptosi <vscale x 2 x float> %a to <vscale x 2 x i1>135 ret <vscale x 2 x i1> %res136}137 138define <vscale x 2 x i1> @fcvtzs_nxv2f64_to_nxv2i1(<vscale x 2 x double> %a) {139; CHECK-LABEL: fcvtzs_nxv2f64_to_nxv2i1:140; CHECK: // %bb.0:141; CHECK-NEXT: ptrue p0.d142; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d143; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0144; CHECK-NEXT: ret145 %res = fptosi <vscale x 2 x double> %a to <vscale x 2 x i1>146 ret <vscale x 2 x i1> %res147}148 149define <vscale x 4 x i1> @fcvtzs_nxv4f16_to_nxv4i1(<vscale x 4 x half> %a) {150; CHECK-LABEL: fcvtzs_nxv4f16_to_nxv4i1:151; CHECK: // %bb.0:152; CHECK-NEXT: ptrue p0.s153; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h154; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0155; CHECK-NEXT: ret156 %res = fptosi <vscale x 4 x half> %a to <vscale x 4 x i1>157 ret <vscale x 4 x i1> %res158}159 160define <vscale x 4 x i1> @fcvtzs_nxv4f32_to_nxv4i1(<vscale x 4 x float> %a) {161; CHECK-LABEL: fcvtzs_nxv4f32_to_nxv4i1:162; CHECK: // %bb.0:163; CHECK-NEXT: ptrue p0.s164; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s165; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0166; CHECK-NEXT: ret167 %res = fptosi <vscale x 4 x float> %a to <vscale x 4 x i1>168 ret <vscale x 4 x i1> %res169}170 171define <vscale x 4 x i1> @fcvtzs_nxv4f64_to_nxv4i1(<vscale x 4 x double> %a) {172; CHECK-LABEL: fcvtzs_nxv4f64_to_nxv4i1:173; CHECK: // %bb.0:174; CHECK-NEXT: ptrue p0.d175; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d176; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d177; CHECK-NEXT: cmpne p1.d, p0/z, z1.d, #0178; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0179; CHECK-NEXT: uzp1 p0.s, p0.s, p1.s180; CHECK-NEXT: ret181 %res = fptosi <vscale x 4 x double> %a to <vscale x 4 x i1>182 ret <vscale x 4 x i1> %res183}184 185define <vscale x 8 x i1> @fcvtzs_nxv8f16_to_nxv8i1(<vscale x 8 x half> %a) {186; CHECK-LABEL: fcvtzs_nxv8f16_to_nxv8i1:187; CHECK: // %bb.0:188; CHECK-NEXT: ptrue p0.h189; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h190; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0191; CHECK-NEXT: ret192 %res = fptosi <vscale x 8 x half> %a to <vscale x 8 x i1>193 ret <vscale x 8 x i1> %res194}195 196define <vscale x 8 x i1> @fcvtzs_nxv8f32_to_nxv8i1(<vscale x 8 x float> %a) {197; CHECK-LABEL: fcvtzs_nxv8f32_to_nxv8i1:198; CHECK: // %bb.0:199; CHECK-NEXT: ptrue p0.s200; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s201; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s202; CHECK-NEXT: cmpne p1.s, p0/z, z1.s, #0203; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0204; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h205; CHECK-NEXT: ret206 %res = fptosi <vscale x 8 x float> %a to <vscale x 8 x i1>207 ret <vscale x 8 x i1> %res208}209 210define <vscale x 8 x i1> @fcvtzs_nxv8f64_to_nxv8i1(<vscale x 8 x double> %a) {211; CHECK-LABEL: fcvtzs_nxv8f64_to_nxv8i1:212; CHECK: // %bb.0:213; CHECK-NEXT: ptrue p0.d214; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d215; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d216; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d217; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d218; CHECK-NEXT: cmpne p1.d, p0/z, z3.d, #0219; CHECK-NEXT: cmpne p2.d, p0/z, z2.d, #0220; CHECK-NEXT: cmpne p3.d, p0/z, z1.d, #0221; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0222; CHECK-NEXT: uzp1 p1.s, p2.s, p1.s223; CHECK-NEXT: uzp1 p0.s, p0.s, p3.s224; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h225; CHECK-NEXT: ret226 %res = fptosi <vscale x 8 x double> %a to <vscale x 8 x i1>227 ret <vscale x 8 x i1> %res228}229 230define <vscale x 2 x i16> @fcvtzs_h_nxv2f16(<vscale x 2 x half> %a) {231; CHECK-LABEL: fcvtzs_h_nxv2f16:232; CHECK: // %bb.0:233; CHECK-NEXT: ptrue p0.d234; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h235; CHECK-NEXT: ret236 %res = fptosi <vscale x 2 x half> %a to <vscale x 2 x i16>237 ret <vscale x 2 x i16> %res238}239 240define <vscale x 2 x i16> @fcvtzs_h_nxv2f32(<vscale x 2 x float> %a) {241; CHECK-LABEL: fcvtzs_h_nxv2f32:242; CHECK: // %bb.0:243; CHECK-NEXT: ptrue p0.d244; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s245; CHECK-NEXT: ret246 %res = fptosi <vscale x 2 x float> %a to <vscale x 2 x i16>247 ret <vscale x 2 x i16> %res248}249 250define <vscale x 2 x i16> @fcvtzs_h_nxv2f64(<vscale x 2 x double> %a) {251; CHECK-LABEL: fcvtzs_h_nxv2f64:252; CHECK: // %bb.0:253; CHECK-NEXT: ptrue p0.d254; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d255; CHECK-NEXT: ret256 %res = fptosi <vscale x 2 x double> %a to <vscale x 2 x i16>257 ret <vscale x 2 x i16> %res258}259 260define <vscale x 4 x i16> @fcvtzs_h_nxv4f16(<vscale x 4 x half> %a) {261; CHECK-LABEL: fcvtzs_h_nxv4f16:262; CHECK: // %bb.0:263; CHECK-NEXT: ptrue p0.s264; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h265; CHECK-NEXT: ret266 %res = fptosi <vscale x 4 x half> %a to <vscale x 4 x i16>267 ret <vscale x 4 x i16> %res268}269 270define <vscale x 4 x i16> @fcvtzs_h_nxv4f32(<vscale x 4 x float> %a) {271; CHECK-LABEL: fcvtzs_h_nxv4f32:272; CHECK: // %bb.0:273; CHECK-NEXT: ptrue p0.s274; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s275; CHECK-NEXT: ret276 %res = fptosi <vscale x 4 x float> %a to <vscale x 4 x i16>277 ret <vscale x 4 x i16> %res278}279 280define <vscale x 7 x i16> @fcvtzs_h_nxv7f16(<vscale x 7 x half> %a) {281; CHECK-LABEL: fcvtzs_h_nxv7f16:282; CHECK: // %bb.0:283; CHECK-NEXT: ptrue p0.h284; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h285; CHECK-NEXT: ret286 %res = fptosi <vscale x 7 x half> %a to <vscale x 7 x i16>287 ret <vscale x 7 x i16> %res288}289 290define <vscale x 8 x i16> @fcvtzs_h_nxv8f16(<vscale x 8 x half> %a) {291; CHECK-LABEL: fcvtzs_h_nxv8f16:292; CHECK: // %bb.0:293; CHECK-NEXT: ptrue p0.h294; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h295; CHECK-NEXT: ret296 %res = fptosi <vscale x 8 x half> %a to <vscale x 8 x i16>297 ret <vscale x 8 x i16> %res298}299 300define <vscale x 2 x i32> @fcvtzs_s_nxv2f16(<vscale x 2 x half> %a) {301; CHECK-LABEL: fcvtzs_s_nxv2f16:302; CHECK: // %bb.0:303; CHECK-NEXT: ptrue p0.d304; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h305; CHECK-NEXT: ret306 %res = fptosi <vscale x 2 x half> %a to <vscale x 2 x i32>307 ret <vscale x 2 x i32> %res308}309 310define <vscale x 2 x i32> @fcvtzs_s_nxv2f32(<vscale x 2 x float> %a) {311; CHECK-LABEL: fcvtzs_s_nxv2f32:312; CHECK: // %bb.0:313; CHECK-NEXT: ptrue p0.d314; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s315; CHECK-NEXT: ret316 %res = fptosi <vscale x 2 x float> %a to <vscale x 2 x i32>317 ret <vscale x 2 x i32> %res318}319 320define <vscale x 2 x i32> @fcvtzs_s_nxv2f64(<vscale x 2 x double> %a) {321; CHECK-LABEL: fcvtzs_s_nxv2f64:322; CHECK: // %bb.0:323; CHECK-NEXT: ptrue p0.d324; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d325; CHECK-NEXT: ret326 %res = fptosi <vscale x 2 x double> %a to <vscale x 2 x i32>327 ret <vscale x 2 x i32> %res328}329 330define <vscale x 4 x i32> @fcvtzs_s_nxv4f16(<vscale x 4 x half> %a) {331; CHECK-LABEL: fcvtzs_s_nxv4f16:332; CHECK: // %bb.0:333; CHECK-NEXT: ptrue p0.s334; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h335; CHECK-NEXT: ret336 %res = fptosi <vscale x 4 x half> %a to <vscale x 4 x i32>337 ret <vscale x 4 x i32> %res338}339 340define <vscale x 3 x i32> @fcvtzs_s_nxv3f16(<vscale x 3 x half> %a) {341; CHECK-LABEL: fcvtzs_s_nxv3f16:342; CHECK: // %bb.0:343; CHECK-NEXT: ptrue p0.s344; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h345; CHECK-NEXT: ret346 %res = fptosi <vscale x 3 x half> %a to <vscale x 3 x i32>347 ret <vscale x 3 x i32> %res348}349 350define <vscale x 4 x i32> @fcvtzs_s_nxv4f32(<vscale x 4 x float> %a) {351; CHECK-LABEL: fcvtzs_s_nxv4f32:352; CHECK: // %bb.0:353; CHECK-NEXT: ptrue p0.s354; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s355; CHECK-NEXT: ret356 %res = fptosi <vscale x 4 x float> %a to <vscale x 4 x i32>357 ret <vscale x 4 x i32> %res358}359 360define <vscale x 2 x i64> @fcvtzs_d_nxv2f16(<vscale x 2 x half> %a) {361; CHECK-LABEL: fcvtzs_d_nxv2f16:362; CHECK: // %bb.0:363; CHECK-NEXT: ptrue p0.d364; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h365; CHECK-NEXT: ret366 %res = fptosi <vscale x 2 x half> %a to <vscale x 2 x i64>367 ret <vscale x 2 x i64> %res368}369 370define <vscale x 2 x i64> @fcvtzs_d_nxv2f32(<vscale x 2 x float> %a) {371; CHECK-LABEL: fcvtzs_d_nxv2f32:372; CHECK: // %bb.0:373; CHECK-NEXT: ptrue p0.d374; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s375; CHECK-NEXT: ret376 %res = fptosi <vscale x 2 x float> %a to <vscale x 2 x i64>377 ret <vscale x 2 x i64> %res378}379 380define <vscale x 2 x i64> @fcvtzs_d_nxv2f64(<vscale x 2 x double> %a) {381; CHECK-LABEL: fcvtzs_d_nxv2f64:382; CHECK: // %bb.0:383; CHECK-NEXT: ptrue p0.d384; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d385; CHECK-NEXT: ret386 %res = fptosi <vscale x 2 x double> %a to <vscale x 2 x i64>387 ret <vscale x 2 x i64> %res388}389 390;391; FP_TO_UINT392;393 394define <vscale x 2 x i1> @fcvtzu_nxv2f16_to_nxv2i1(<vscale x 2 x half> %a) {395; CHECK-LABEL: fcvtzu_nxv2f16_to_nxv2i1:396; CHECK: // %bb.0:397; CHECK-NEXT: ptrue p0.d398; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h399; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0400; CHECK-NEXT: ret401 %res = fptoui <vscale x 2 x half> %a to <vscale x 2 x i1>402 ret <vscale x 2 x i1> %res403}404 405define <vscale x 2 x i1> @fcvtzu_nxv2f32_to_nxv2i1(<vscale x 2 x float> %a) {406; CHECK-LABEL: fcvtzu_nxv2f32_to_nxv2i1:407; CHECK: // %bb.0:408; CHECK-NEXT: ptrue p0.d409; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s410; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0411; CHECK-NEXT: ret412 %res = fptoui <vscale x 2 x float> %a to <vscale x 2 x i1>413 ret <vscale x 2 x i1> %res414}415 416define <vscale x 2 x i1> @fcvtzu_nxv2f64_to_nxv2i1(<vscale x 2 x double> %a) {417; CHECK-LABEL: fcvtzu_nxv2f64_to_nxv2i1:418; CHECK: // %bb.0:419; CHECK-NEXT: ptrue p0.d420; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d421; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0422; CHECK-NEXT: ret423 %res = fptoui <vscale x 2 x double> %a to <vscale x 2 x i1>424 ret <vscale x 2 x i1> %res425}426 427define <vscale x 4 x i1> @fcvtzu_nxv4f16_to_nxv4i1(<vscale x 4 x half> %a) {428; CHECK-LABEL: fcvtzu_nxv4f16_to_nxv4i1:429; CHECK: // %bb.0:430; CHECK-NEXT: ptrue p0.s431; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h432; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0433; CHECK-NEXT: ret434 %res = fptoui <vscale x 4 x half> %a to <vscale x 4 x i1>435 ret <vscale x 4 x i1> %res436}437 438define <vscale x 4 x i1> @fcvtzu_nxv4f32_to_nxv4i1(<vscale x 4 x float> %a) {439; CHECK-LABEL: fcvtzu_nxv4f32_to_nxv4i1:440; CHECK: // %bb.0:441; CHECK-NEXT: ptrue p0.s442; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s443; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0444; CHECK-NEXT: ret445 %res = fptoui <vscale x 4 x float> %a to <vscale x 4 x i1>446 ret <vscale x 4 x i1> %res447}448 449define <vscale x 4 x i1> @fcvtzu_nxv4f64_to_nxv4i1(<vscale x 4 x double> %a) {450; CHECK-LABEL: fcvtzu_nxv4f64_to_nxv4i1:451; CHECK: // %bb.0:452; CHECK-NEXT: ptrue p0.d453; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d454; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d455; CHECK-NEXT: cmpne p1.d, p0/z, z1.d, #0456; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0457; CHECK-NEXT: uzp1 p0.s, p0.s, p1.s458; CHECK-NEXT: ret459 %res = fptoui <vscale x 4 x double> %a to <vscale x 4 x i1>460 ret <vscale x 4 x i1> %res461}462 463define <vscale x 8 x i1> @fcvtzu_nxv8f16_to_nxv8i1(<vscale x 8 x half> %a) {464; CHECK-LABEL: fcvtzu_nxv8f16_to_nxv8i1:465; CHECK: // %bb.0:466; CHECK-NEXT: ptrue p0.h467; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h468; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0469; CHECK-NEXT: ret470 %res = fptoui <vscale x 8 x half> %a to <vscale x 8 x i1>471 ret <vscale x 8 x i1> %res472}473 474define <vscale x 8 x i1> @fcvtzu_nxv8f32_to_nxv8i1(<vscale x 8 x float> %a) {475; CHECK-LABEL: fcvtzu_nxv8f32_to_nxv8i1:476; CHECK: // %bb.0:477; CHECK-NEXT: ptrue p0.s478; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s479; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s480; CHECK-NEXT: cmpne p1.s, p0/z, z1.s, #0481; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0482; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h483; CHECK-NEXT: ret484 %res = fptoui <vscale x 8 x float> %a to <vscale x 8 x i1>485 ret <vscale x 8 x i1> %res486}487 488define <vscale x 8 x i1> @fcvtzu_nxv8f64_to_nxv8i1(<vscale x 8 x double> %a) {489; CHECK-LABEL: fcvtzu_nxv8f64_to_nxv8i1:490; CHECK: // %bb.0:491; CHECK-NEXT: ptrue p0.d492; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.d493; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.d494; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d495; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d496; CHECK-NEXT: cmpne p1.d, p0/z, z3.d, #0497; CHECK-NEXT: cmpne p2.d, p0/z, z2.d, #0498; CHECK-NEXT: cmpne p3.d, p0/z, z1.d, #0499; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0500; CHECK-NEXT: uzp1 p1.s, p2.s, p1.s501; CHECK-NEXT: uzp1 p0.s, p0.s, p3.s502; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h503; CHECK-NEXT: ret504 %res = fptoui <vscale x 8 x double> %a to <vscale x 8 x i1>505 ret <vscale x 8 x i1> %res506}507 508; NOTE: Using fcvtzs is safe as fptoui overflow is considered poison and a509; 64bit signed value encompasses the entire range of a 16bit unsigned value510define <vscale x 2 x i16> @fcvtzu_h_nxv2f16(<vscale x 2 x half> %a) {511; CHECK-LABEL: fcvtzu_h_nxv2f16:512; CHECK: // %bb.0:513; CHECK-NEXT: ptrue p0.d514; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h515; CHECK-NEXT: ret516 %res = fptoui <vscale x 2 x half> %a to <vscale x 2 x i16>517 ret <vscale x 2 x i16> %res518}519 520define <vscale x 2 x i16> @fcvtzu_h_nxv2f32(<vscale x 2 x float> %a) {521; CHECK-LABEL: fcvtzu_h_nxv2f32:522; CHECK: // %bb.0:523; CHECK-NEXT: ptrue p0.d524; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s525; CHECK-NEXT: ret526 %res = fptoui <vscale x 2 x float> %a to <vscale x 2 x i16>527 ret <vscale x 2 x i16> %res528}529 530define <vscale x 2 x i16> @fcvtzu_h_nxv2f64(<vscale x 2 x double> %a) {531; CHECK-LABEL: fcvtzu_h_nxv2f64:532; CHECK: // %bb.0:533; CHECK-NEXT: ptrue p0.d534; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d535; CHECK-NEXT: ret536 %res = fptoui <vscale x 2 x double> %a to <vscale x 2 x i16>537 ret <vscale x 2 x i16> %res538}539 540define <vscale x 4 x i16> @fcvtzu_h_nxv4f16(<vscale x 4 x half> %a) {541; CHECK-LABEL: fcvtzu_h_nxv4f16:542; CHECK: // %bb.0:543; CHECK-NEXT: ptrue p0.s544; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h545; CHECK-NEXT: ret546 %res = fptoui <vscale x 4 x half> %a to <vscale x 4 x i16>547 ret <vscale x 4 x i16> %res548}549 550define <vscale x 4 x i16> @fcvtzu_h_nxv4f32(<vscale x 4 x float> %a) {551; CHECK-LABEL: fcvtzu_h_nxv4f32:552; CHECK: // %bb.0:553; CHECK-NEXT: ptrue p0.s554; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s555; CHECK-NEXT: ret556 %res = fptosi <vscale x 4 x float> %a to <vscale x 4 x i16>557 ret <vscale x 4 x i16> %res558}559 560define <vscale x 7 x i16> @fcvtzu_h_nxv7f16(<vscale x 7 x half> %a) {561; CHECK-LABEL: fcvtzu_h_nxv7f16:562; CHECK: // %bb.0:563; CHECK-NEXT: ptrue p0.h564; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h565; CHECK-NEXT: ret566 %res = fptoui <vscale x 7 x half> %a to <vscale x 7 x i16>567 ret <vscale x 7 x i16> %res568}569 570define <vscale x 8 x i16> @fcvtzu_h_nxv8f16(<vscale x 8 x half> %a) {571; CHECK-LABEL: fcvtzu_h_nxv8f16:572; CHECK: // %bb.0:573; CHECK-NEXT: ptrue p0.h574; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h575; CHECK-NEXT: ret576 %res = fptoui <vscale x 8 x half> %a to <vscale x 8 x i16>577 ret <vscale x 8 x i16> %res578}579 580define <vscale x 2 x i32> @fcvtzu_s_nxv2f16(<vscale x 2 x half> %a) {581; CHECK-LABEL: fcvtzu_s_nxv2f16:582; CHECK: // %bb.0:583; CHECK-NEXT: ptrue p0.d584; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h585; CHECK-NEXT: ret586 %res = fptoui <vscale x 2 x half> %a to <vscale x 2 x i32>587 ret <vscale x 2 x i32> %res588}589 590define <vscale x 2 x i32> @fcvtzu_s_nxv2f32(<vscale x 2 x float> %a) {591; CHECK-LABEL: fcvtzu_s_nxv2f32:592; CHECK: // %bb.0:593; CHECK-NEXT: ptrue p0.d594; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s595; CHECK-NEXT: ret596 %res = fptoui <vscale x 2 x float> %a to <vscale x 2 x i32>597 ret <vscale x 2 x i32> %res598}599 600define <vscale x 2 x i32> @fcvtzu_s_nxv2f64(<vscale x 2 x double> %a) {601; CHECK-LABEL: fcvtzu_s_nxv2f64:602; CHECK: // %bb.0:603; CHECK-NEXT: ptrue p0.d604; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d605; CHECK-NEXT: ret606 %res = fptoui <vscale x 2 x double> %a to <vscale x 2 x i32>607 ret <vscale x 2 x i32> %res608}609 610define <vscale x 3 x i32> @fcvtzu_s_nxv3f16(<vscale x 3 x half> %a) {611; CHECK-LABEL: fcvtzu_s_nxv3f16:612; CHECK: // %bb.0:613; CHECK-NEXT: ptrue p0.s614; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h615; CHECK-NEXT: ret616 %res = fptoui <vscale x 3 x half> %a to <vscale x 3 x i32>617 ret <vscale x 3 x i32> %res618}619 620define <vscale x 3 x i32> @fcvtzu_s_nxv3f32(<vscale x 3 x float> %a) {621; CHECK-LABEL: fcvtzu_s_nxv3f32:622; CHECK: // %bb.0:623; CHECK-NEXT: ptrue p0.s624; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s625; CHECK-NEXT: ret626 %res = fptoui <vscale x 3 x float> %a to <vscale x 3 x i32>627 ret <vscale x 3 x i32> %res628}629 630define <vscale x 4 x i32> @fcvtzu_s_nxv4f16(<vscale x 4 x half> %a) {631; CHECK-LABEL: fcvtzu_s_nxv4f16:632; CHECK: // %bb.0:633; CHECK-NEXT: ptrue p0.s634; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h635; CHECK-NEXT: ret636 %res = fptoui <vscale x 4 x half> %a to <vscale x 4 x i32>637 ret <vscale x 4 x i32> %res638}639 640define <vscale x 4 x i32> @fcvtzu_s_nxv4f32(<vscale x 4 x float> %a) {641; CHECK-LABEL: fcvtzu_s_nxv4f32:642; CHECK: // %bb.0:643; CHECK-NEXT: ptrue p0.s644; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s645; CHECK-NEXT: ret646 %res = fptoui <vscale x 4 x float> %a to <vscale x 4 x i32>647 ret <vscale x 4 x i32> %res648}649 650define <vscale x 2 x i64> @fcvtzu_d_nxv2f16(<vscale x 2 x half> %a) {651; CHECK-LABEL: fcvtzu_d_nxv2f16:652; CHECK: // %bb.0:653; CHECK-NEXT: ptrue p0.d654; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h655; CHECK-NEXT: ret656 %res = fptoui <vscale x 2 x half> %a to <vscale x 2 x i64>657 ret <vscale x 2 x i64> %res658}659 660define <vscale x 2 x i64> @fcvtzu_d_nxv2f32(<vscale x 2 x float> %a) {661; CHECK-LABEL: fcvtzu_d_nxv2f32:662; CHECK: // %bb.0:663; CHECK-NEXT: ptrue p0.d664; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s665; CHECK-NEXT: ret666 %res = fptoui <vscale x 2 x float> %a to <vscale x 2 x i64>667 ret <vscale x 2 x i64> %res668}669 670define <vscale x 2 x i64> @fcvtzu_d_nxv2f64(<vscale x 2 x double> %a) {671; CHECK-LABEL: fcvtzu_d_nxv2f64:672; CHECK: // %bb.0:673; CHECK-NEXT: ptrue p0.d674; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d675; CHECK-NEXT: ret676 %res = fptoui <vscale x 2 x double> %a to <vscale x 2 x i64>677 ret <vscale x 2 x i64> %res678}679 680; SINT_TO_FP681 682define <vscale x 2 x half> @scvtf_h_nxv2i1(<vscale x 2 x i1> %a) {683; CHECK-LABEL: scvtf_h_nxv2i1:684; CHECK: // %bb.0:685; CHECK-NEXT: movi v0.2d, #0000000000000000686; CHECK-NEXT: fmov z0.h, p0/m, #-1.00000000687; CHECK-NEXT: ret688 %res = sitofp <vscale x 2 x i1> %a to <vscale x 2 x half>689 ret <vscale x 2 x half> %res690}691 692define <vscale x 2 x half> @scvtf_h_nxv2i16(<vscale x 2 x i16> %a) {693; CHECK-LABEL: scvtf_h_nxv2i16:694; CHECK: // %bb.0:695; CHECK-NEXT: ptrue p0.d696; CHECK-NEXT: scvtf z0.h, p0/m, z0.h697; CHECK-NEXT: ret698 %res = sitofp <vscale x 2 x i16> %a to <vscale x 2 x half>699 ret <vscale x 2 x half> %res700}701 702define <vscale x 2 x half> @scvtf_h_nxv2i32(<vscale x 2 x i32> %a) {703; CHECK-LABEL: scvtf_h_nxv2i32:704; CHECK: // %bb.0:705; CHECK-NEXT: ptrue p0.d706; CHECK-NEXT: scvtf z0.h, p0/m, z0.s707; CHECK-NEXT: ret708 %res = sitofp <vscale x 2 x i32> %a to <vscale x 2 x half>709 ret <vscale x 2 x half> %res710}711 712define <vscale x 2 x half> @scvtf_h_nxv2i64(<vscale x 2 x i64> %a) {713; CHECK-LABEL: scvtf_h_nxv2i64:714; CHECK: // %bb.0:715; CHECK-NEXT: ptrue p0.d716; CHECK-NEXT: scvtf z0.h, p0/m, z0.d717; CHECK-NEXT: ret718 %res = sitofp <vscale x 2 x i64> %a to <vscale x 2 x half>719 ret <vscale x 2 x half> %res720}721 722define <vscale x 3 x half> @scvtf_h_nxv3i1(<vscale x 3 x i1> %a) {723; CHECK-LABEL: scvtf_h_nxv3i1:724; CHECK: // %bb.0:725; CHECK-NEXT: movi v0.2d, #0000000000000000726; CHECK-NEXT: fmov z0.h, p0/m, #-1.00000000727; CHECK-NEXT: ret728 %res = sitofp <vscale x 3 x i1> %a to <vscale x 3 x half>729 ret <vscale x 3 x half> %res730}731 732define <vscale x 3 x half> @scvtf_h_nxv3i16(<vscale x 3 x i16> %a) {733; CHECK-LABEL: scvtf_h_nxv3i16:734; CHECK: // %bb.0:735; CHECK-NEXT: ptrue p0.s736; CHECK-NEXT: scvtf z0.h, p0/m, z0.h737; CHECK-NEXT: ret738 %res = sitofp <vscale x 3 x i16> %a to <vscale x 3 x half>739 ret <vscale x 3 x half> %res740}741 742define <vscale x 4 x half> @scvtf_h_nxv4i1(<vscale x 4 x i1> %a) {743; CHECK-LABEL: scvtf_h_nxv4i1:744; CHECK: // %bb.0:745; CHECK-NEXT: movi v0.2d, #0000000000000000746; CHECK-NEXT: fmov z0.h, p0/m, #-1.00000000747; CHECK-NEXT: ret748 %res = sitofp <vscale x 4 x i1> %a to <vscale x 4 x half>749 ret <vscale x 4 x half> %res750}751 752define <vscale x 4 x half> @scvtf_h_nxv4i16(<vscale x 4 x i16> %a) {753; CHECK-LABEL: scvtf_h_nxv4i16:754; CHECK: // %bb.0:755; CHECK-NEXT: ptrue p0.s756; CHECK-NEXT: scvtf z0.h, p0/m, z0.h757; CHECK-NEXT: ret758 %res = sitofp <vscale x 4 x i16> %a to <vscale x 4 x half>759 ret <vscale x 4 x half> %res760}761 762define <vscale x 4 x half> @scvtf_h_nxv4i32(<vscale x 4 x i32> %a) {763; CHECK-LABEL: scvtf_h_nxv4i32:764; CHECK: // %bb.0:765; CHECK-NEXT: ptrue p0.s766; CHECK-NEXT: scvtf z0.h, p0/m, z0.s767; CHECK-NEXT: ret768 %res = sitofp <vscale x 4 x i32> %a to <vscale x 4 x half>769 ret <vscale x 4 x half> %res770}771 772define <vscale x 7 x half> @scvtf_h_nxv7i1(<vscale x 7 x i1> %a) {773; CHECK-LABEL: scvtf_h_nxv7i1:774; CHECK: // %bb.0:775; CHECK-NEXT: movi v0.2d, #0000000000000000776; CHECK-NEXT: fmov z0.h, p0/m, #-1.00000000777; CHECK-NEXT: ret778 %res = sitofp <vscale x 7 x i1> %a to <vscale x 7 x half>779 ret <vscale x 7 x half> %res780}781 782define <vscale x 7 x half> @scvtf_h_nxv7i16(<vscale x 7 x i16> %a) {783; CHECK-LABEL: scvtf_h_nxv7i16:784; CHECK: // %bb.0:785; CHECK-NEXT: ptrue p0.h786; CHECK-NEXT: scvtf z0.h, p0/m, z0.h787; CHECK-NEXT: ret788 %res = sitofp <vscale x 7 x i16> %a to <vscale x 7 x half>789 ret <vscale x 7 x half> %res790}791 792define <vscale x 8 x half> @scvtf_h_nxv8i1(<vscale x 8 x i1> %a) {793; CHECK-LABEL: scvtf_h_nxv8i1:794; CHECK: // %bb.0:795; CHECK-NEXT: movi v0.2d, #0000000000000000796; CHECK-NEXT: fmov z0.h, p0/m, #-1.00000000797; CHECK-NEXT: ret798 %res = sitofp <vscale x 8 x i1> %a to <vscale x 8 x half>799 ret <vscale x 8 x half> %res800}801 802define <vscale x 8 x half> @scvtf_h_nxv8i16(<vscale x 8 x i16> %a) {803; CHECK-LABEL: scvtf_h_nxv8i16:804; CHECK: // %bb.0:805; CHECK-NEXT: ptrue p0.h806; CHECK-NEXT: scvtf z0.h, p0/m, z0.h807; CHECK-NEXT: ret808 %res = sitofp <vscale x 8 x i16> %a to <vscale x 8 x half>809 ret <vscale x 8 x half> %res810}811 812define <vscale x 2 x float> @scvtf_s_nxv2i1(<vscale x 2 x i1> %a) {813; CHECK-LABEL: scvtf_s_nxv2i1:814; CHECK: // %bb.0:815; CHECK-NEXT: movi v0.2d, #0000000000000000816; CHECK-NEXT: fmov z0.s, p0/m, #-1.00000000817; CHECK-NEXT: ret818 %res = sitofp <vscale x 2 x i1> %a to <vscale x 2 x float>819 ret <vscale x 2 x float> %res820}821 822define <vscale x 2 x float> @scvtf_s_nxv2i32(<vscale x 2 x i32> %a) {823; CHECK-LABEL: scvtf_s_nxv2i32:824; CHECK: // %bb.0:825; CHECK-NEXT: ptrue p0.d826; CHECK-NEXT: scvtf z0.s, p0/m, z0.s827; CHECK-NEXT: ret828 %res = sitofp <vscale x 2 x i32> %a to <vscale x 2 x float>829 ret <vscale x 2 x float> %res830}831 832define <vscale x 2 x float> @scvtf_s_nxv2i64(<vscale x 2 x i64> %a) {833; CHECK-LABEL: scvtf_s_nxv2i64:834; CHECK: // %bb.0:835; CHECK-NEXT: ptrue p0.d836; CHECK-NEXT: scvtf z0.s, p0/m, z0.d837; CHECK-NEXT: ret838 %res = sitofp <vscale x 2 x i64> %a to <vscale x 2 x float>839 ret <vscale x 2 x float> %res840}841 842define <vscale x 3 x float> @scvtf_s_nxv3i1(<vscale x 3 x i1> %a) {843; CHECK-LABEL: scvtf_s_nxv3i1:844; CHECK: // %bb.0:845; CHECK-NEXT: movi v0.2d, #0000000000000000846; CHECK-NEXT: fmov z0.s, p0/m, #-1.00000000847; CHECK-NEXT: ret848 %res = sitofp <vscale x 3 x i1> %a to <vscale x 3 x float>849 ret <vscale x 3 x float> %res850}851 852define <vscale x 3 x float> @scvtf_s_nxv3i32(<vscale x 3 x i32> %a) {853; CHECK-LABEL: scvtf_s_nxv3i32:854; CHECK: // %bb.0:855; CHECK-NEXT: ptrue p0.s856; CHECK-NEXT: scvtf z0.s, p0/m, z0.s857; CHECK-NEXT: ret858 %res = sitofp <vscale x 3 x i32> %a to <vscale x 3 x float>859 ret <vscale x 3 x float> %res860}861 862define <vscale x 4 x float> @scvtf_s_nxv4i1(<vscale x 4 x i1> %a) {863; CHECK-LABEL: scvtf_s_nxv4i1:864; CHECK: // %bb.0:865; CHECK-NEXT: movi v0.2d, #0000000000000000866; CHECK-NEXT: fmov z0.s, p0/m, #-1.00000000867; CHECK-NEXT: ret868 %res = sitofp <vscale x 4 x i1> %a to <vscale x 4 x float>869 ret <vscale x 4 x float> %res870}871 872define <vscale x 4 x float> @scvtf_s_nxv4i32(<vscale x 4 x i32> %a) {873; CHECK-LABEL: scvtf_s_nxv4i32:874; CHECK: // %bb.0:875; CHECK-NEXT: ptrue p0.s876; CHECK-NEXT: scvtf z0.s, p0/m, z0.s877; CHECK-NEXT: ret878 %res = sitofp <vscale x 4 x i32> %a to <vscale x 4 x float>879 ret <vscale x 4 x float> %res880}881 882define <vscale x 2 x double> @scvtf_d_nxv2i1(<vscale x 2 x i1> %a) {883; CHECK-LABEL: scvtf_d_nxv2i1:884; CHECK: // %bb.0:885; CHECK-NEXT: movi v0.2d, #0000000000000000886; CHECK-NEXT: fmov z0.d, p0/m, #-1.00000000887; CHECK-NEXT: ret888 %res = sitofp <vscale x 2 x i1> %a to <vscale x 2 x double>889 ret <vscale x 2 x double> %res890}891 892define <vscale x 2 x double> @scvtf_d_nxv2i32(<vscale x 2 x i32> %a) {893; CHECK-LABEL: scvtf_d_nxv2i32:894; CHECK: // %bb.0:895; CHECK-NEXT: ptrue p0.d896; CHECK-NEXT: scvtf z0.d, p0/m, z0.s897; CHECK-NEXT: ret898 %res = sitofp <vscale x 2 x i32> %a to <vscale x 2 x double>899 ret <vscale x 2 x double> %res900}901 902define <vscale x 2 x double> @scvtf_d_nxv2i64(<vscale x 2 x i64> %a) {903; CHECK-LABEL: scvtf_d_nxv2i64:904; CHECK: // %bb.0:905; CHECK-NEXT: ptrue p0.d906; CHECK-NEXT: scvtf z0.d, p0/m, z0.d907; CHECK-NEXT: ret908 %res = sitofp <vscale x 2 x i64> %a to <vscale x 2 x double>909 ret <vscale x 2 x double> %res910}911 912; UINT_TO_FP913 914define <vscale x 2 x half> @ucvtf_h_nxv2i1(<vscale x 2 x i1> %a) {915; CHECK-LABEL: ucvtf_h_nxv2i1:916; CHECK: // %bb.0:917; CHECK-NEXT: movi v0.2d, #0000000000000000918; CHECK-NEXT: fmov z0.h, p0/m, #1.00000000919; CHECK-NEXT: ret920 %res = uitofp <vscale x 2 x i1> %a to <vscale x 2 x half>921 ret <vscale x 2 x half> %res922}923 924define <vscale x 2 x half> @ucvtf_h_nxv2i16(<vscale x 2 x i16> %a) {925; CHECK-LABEL: ucvtf_h_nxv2i16:926; CHECK: // %bb.0:927; CHECK-NEXT: ptrue p0.d928; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h929; CHECK-NEXT: ret930 %res = uitofp <vscale x 2 x i16> %a to <vscale x 2 x half>931 ret <vscale x 2 x half> %res932}933 934define <vscale x 2 x half> @ucvtf_h_nxv2i32(<vscale x 2 x i32> %a) {935; CHECK-LABEL: ucvtf_h_nxv2i32:936; CHECK: // %bb.0:937; CHECK-NEXT: ptrue p0.d938; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s939; CHECK-NEXT: ret940 %res = uitofp <vscale x 2 x i32> %a to <vscale x 2 x half>941 ret <vscale x 2 x half> %res942}943 944define <vscale x 2 x half> @ucvtf_h_nxv2i64(<vscale x 2 x i64> %a) {945; CHECK-LABEL: ucvtf_h_nxv2i64:946; CHECK: // %bb.0:947; CHECK-NEXT: ptrue p0.d948; CHECK-NEXT: ucvtf z0.h, p0/m, z0.d949; CHECK-NEXT: ret950 %res = uitofp <vscale x 2 x i64> %a to <vscale x 2 x half>951 ret <vscale x 2 x half> %res952}953 954define <vscale x 3 x half> @ucvtf_h_nxv3i1(<vscale x 3 x i1> %a) {955; CHECK-LABEL: ucvtf_h_nxv3i1:956; CHECK: // %bb.0:957; CHECK-NEXT: movi v0.2d, #0000000000000000958; CHECK-NEXT: fmov z0.h, p0/m, #1.00000000959; CHECK-NEXT: ret960 %res = uitofp <vscale x 3 x i1> %a to <vscale x 3 x half>961 ret <vscale x 3 x half> %res962}963 964define <vscale x 3 x half> @ucvtf_h_nxv3i16(<vscale x 3 x i16> %a) {965; CHECK-LABEL: ucvtf_h_nxv3i16:966; CHECK: // %bb.0:967; CHECK-NEXT: ptrue p0.s968; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h969; CHECK-NEXT: ret970 %res = uitofp <vscale x 3 x i16> %a to <vscale x 3 x half>971 ret <vscale x 3 x half> %res972}973 974define <vscale x 3 x half> @ucvtf_h_nxv3i32(<vscale x 3 x i32> %a) {975; CHECK-LABEL: ucvtf_h_nxv3i32:976; CHECK: // %bb.0:977; CHECK-NEXT: ptrue p0.s978; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s979; CHECK-NEXT: ret980 %res = uitofp <vscale x 3 x i32> %a to <vscale x 3 x half>981 ret <vscale x 3 x half> %res982}983 984define <vscale x 4 x half> @ucvtf_h_nxv4i1(<vscale x 4 x i1> %a) {985; CHECK-LABEL: ucvtf_h_nxv4i1:986; CHECK: // %bb.0:987; CHECK-NEXT: movi v0.2d, #0000000000000000988; CHECK-NEXT: fmov z0.h, p0/m, #1.00000000989; CHECK-NEXT: ret990 %res = uitofp <vscale x 4 x i1> %a to <vscale x 4 x half>991 ret <vscale x 4 x half> %res992}993 994define <vscale x 4 x half> @ucvtf_h_nxv4i16(<vscale x 4 x i16> %a) {995; CHECK-LABEL: ucvtf_h_nxv4i16:996; CHECK: // %bb.0:997; CHECK-NEXT: ptrue p0.s998; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h999; CHECK-NEXT: ret1000 %res = uitofp <vscale x 4 x i16> %a to <vscale x 4 x half>1001 ret <vscale x 4 x half> %res1002}1003 1004define <vscale x 4 x half> @ucvtf_h_nxv4i32(<vscale x 4 x i32> %a) {1005; CHECK-LABEL: ucvtf_h_nxv4i32:1006; CHECK: // %bb.0:1007; CHECK-NEXT: ptrue p0.s1008; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s1009; CHECK-NEXT: ret1010 %res = uitofp <vscale x 4 x i32> %a to <vscale x 4 x half>1011 ret <vscale x 4 x half> %res1012}1013 1014define <vscale x 8 x half> @ucvtf_h_nxv8i1(<vscale x 8 x i1> %a) {1015; CHECK-LABEL: ucvtf_h_nxv8i1:1016; CHECK: // %bb.0:1017; CHECK-NEXT: movi v0.2d, #00000000000000001018; CHECK-NEXT: fmov z0.h, p0/m, #1.000000001019; CHECK-NEXT: ret1020 %res = uitofp <vscale x 8 x i1> %a to <vscale x 8 x half>1021 ret <vscale x 8 x half> %res1022}1023 1024define <vscale x 8 x half> @ucvtf_h_nxv8i16(<vscale x 8 x i16> %a) {1025; CHECK-LABEL: ucvtf_h_nxv8i16:1026; CHECK: // %bb.0:1027; CHECK-NEXT: ptrue p0.h1028; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h1029; CHECK-NEXT: ret1030 %res = uitofp <vscale x 8 x i16> %a to <vscale x 8 x half>1031 ret <vscale x 8 x half> %res1032}1033 1034define <vscale x 2 x float> @ucvtf_s_nxv2i1(<vscale x 2 x i1> %a) {1035; CHECK-LABEL: ucvtf_s_nxv2i1:1036; CHECK: // %bb.0:1037; CHECK-NEXT: movi v0.2d, #00000000000000001038; CHECK-NEXT: fmov z0.s, p0/m, #1.000000001039; CHECK-NEXT: ret1040 %res = uitofp <vscale x 2 x i1> %a to <vscale x 2 x float>1041 ret <vscale x 2 x float> %res1042}1043 1044define <vscale x 2 x float> @ucvtf_s_nxv2i32(<vscale x 2 x i32> %a) {1045; CHECK-LABEL: ucvtf_s_nxv2i32:1046; CHECK: // %bb.0:1047; CHECK-NEXT: ptrue p0.d1048; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s1049; CHECK-NEXT: ret1050 %res = uitofp <vscale x 2 x i32> %a to <vscale x 2 x float>1051 ret <vscale x 2 x float> %res1052}1053 1054define <vscale x 2 x float> @ucvtf_s_nxv2i64(<vscale x 2 x i64> %a) {1055; CHECK-LABEL: ucvtf_s_nxv2i64:1056; CHECK: // %bb.0:1057; CHECK-NEXT: ptrue p0.d1058; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d1059; CHECK-NEXT: ret1060 %res = uitofp <vscale x 2 x i64> %a to <vscale x 2 x float>1061 ret <vscale x 2 x float> %res1062}1063 1064define <vscale x 4 x float> @ucvtf_s_nxv4i1(<vscale x 4 x i1> %a) {1065; CHECK-LABEL: ucvtf_s_nxv4i1:1066; CHECK: // %bb.0:1067; CHECK-NEXT: movi v0.2d, #00000000000000001068; CHECK-NEXT: fmov z0.s, p0/m, #1.000000001069; CHECK-NEXT: ret1070 %res = uitofp <vscale x 4 x i1> %a to <vscale x 4 x float>1071 ret <vscale x 4 x float> %res1072}1073 1074define <vscale x 4 x float> @ucvtf_s_nxv4i32(<vscale x 4 x i32> %a) {1075; CHECK-LABEL: ucvtf_s_nxv4i32:1076; CHECK: // %bb.0:1077; CHECK-NEXT: ptrue p0.s1078; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s1079; CHECK-NEXT: ret1080 %res = uitofp <vscale x 4 x i32> %a to <vscale x 4 x float>1081 ret <vscale x 4 x float> %res1082}1083 1084define <vscale x 2 x double> @ucvtf_d_nxv2i1(<vscale x 2 x i1> %a) {1085; CHECK-LABEL: ucvtf_d_nxv2i1:1086; CHECK: // %bb.0:1087; CHECK-NEXT: movi v0.2d, #00000000000000001088; CHECK-NEXT: fmov z0.d, p0/m, #1.000000001089; CHECK-NEXT: ret1090 %res = uitofp <vscale x 2 x i1> %a to <vscale x 2 x double>1091 ret <vscale x 2 x double> %res1092}1093 1094define <vscale x 2 x double> @ucvtf_d_nxv2i32(<vscale x 2 x i32> %a) {1095; CHECK-LABEL: ucvtf_d_nxv2i32:1096; CHECK: // %bb.0:1097; CHECK-NEXT: ptrue p0.d1098; CHECK-NEXT: ucvtf z0.d, p0/m, z0.s1099; CHECK-NEXT: ret1100 %res = uitofp <vscale x 2 x i32> %a to <vscale x 2 x double>1101 ret <vscale x 2 x double> %res1102}1103 1104define <vscale x 2 x double> @ucvtf_d_nxv2i64(<vscale x 2 x i64> %a) {1105; CHECK-LABEL: ucvtf_d_nxv2i64:1106; CHECK: // %bb.0:1107; CHECK-NEXT: ptrue p0.d1108; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d1109; CHECK-NEXT: ret1110 %res = uitofp <vscale x 2 x i64> %a to <vscale x 2 x double>1111 ret <vscale x 2 x double> %res1112}1113 1114define <vscale x 4 x float> @fcvt_htos_movprfx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {1115; CHECK-LABEL: fcvt_htos_movprfx:1116; CHECK: // %bb.0:1117; CHECK-NEXT: ptrue p0.s1118; CHECK-NEXT: movprfx z0, z11119; CHECK-NEXT: fcvt z0.s, p0/m, z1.h1120; CHECK-NEXT: ret1121 %res = fpext <vscale x 4 x half> %b to <vscale x 4 x float>1122 ret <vscale x 4 x float> %res1123}1124 1125define <vscale x 2 x double> @fcvt_htod_movprfx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {1126; CHECK-LABEL: fcvt_htod_movprfx:1127; CHECK: // %bb.0:1128; CHECK-NEXT: ptrue p0.d1129; CHECK-NEXT: movprfx z0, z11130; CHECK-NEXT: fcvt z0.d, p0/m, z1.h1131; CHECK-NEXT: ret1132 %res = fpext <vscale x 2 x half> %b to <vscale x 2 x double>1133 ret <vscale x 2 x double> %res1134}1135 1136define <vscale x 2 x double> @fcvt_stod_movprfx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {1137; CHECK-LABEL: fcvt_stod_movprfx:1138; CHECK: // %bb.0:1139; CHECK-NEXT: ptrue p0.d1140; CHECK-NEXT: movprfx z0, z11141; CHECK-NEXT: fcvt z0.d, p0/m, z1.s1142; CHECK-NEXT: ret1143 %res = fpext <vscale x 2 x float> %b to <vscale x 2 x double>1144 ret <vscale x 2 x double> %res1145}1146 1147define <vscale x 4 x half> @fcvt_stoh_movprfx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {1148; CHECK-LABEL: fcvt_stoh_movprfx:1149; CHECK: // %bb.0:1150; CHECK-NEXT: ptrue p0.s1151; CHECK-NEXT: movprfx z0, z11152; CHECK-NEXT: fcvt z0.h, p0/m, z1.s1153; CHECK-NEXT: ret1154 %res = fptrunc <vscale x 4 x float> %b to <vscale x 4 x half>1155 ret <vscale x 4 x half> %res1156}1157 1158define <vscale x 2 x half> @fcvt_dtoh_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {1159; CHECK-LABEL: fcvt_dtoh_movprfx:1160; CHECK: // %bb.0:1161; CHECK-NEXT: ptrue p0.d1162; CHECK-NEXT: movprfx z0, z11163; CHECK-NEXT: fcvt z0.h, p0/m, z1.d1164; CHECK-NEXT: ret1165 %res = fptrunc <vscale x 2 x double> %b to <vscale x 2 x half>1166 ret <vscale x 2 x half> %res1167}1168 1169define <vscale x 2 x float> @fcvt_dtos_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {1170; CHECK-LABEL: fcvt_dtos_movprfx:1171; CHECK: // %bb.0:1172; CHECK-NEXT: ptrue p0.d1173; CHECK-NEXT: movprfx z0, z11174; CHECK-NEXT: fcvt z0.s, p0/m, z1.d1175; CHECK-NEXT: ret1176 %res = fptrunc <vscale x 2 x double> %b to <vscale x 2 x float>1177 ret <vscale x 2 x float> %res1178}1179 1180define <vscale x 8 x half> @scvtf_htoh_movprfx(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {1181; CHECK-LABEL: scvtf_htoh_movprfx:1182; CHECK: // %bb.0:1183; CHECK-NEXT: ptrue p0.h1184; CHECK-NEXT: movprfx z0, z11185; CHECK-NEXT: scvtf z0.h, p0/m, z1.h1186; CHECK-NEXT: ret1187 %res = sitofp <vscale x 8 x i16> %b to <vscale x 8 x half>1188 ret <vscale x 8 x half> %res1189}1190 1191define <vscale x 4 x float> @scvtf_stos_movprfx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1192; CHECK-LABEL: scvtf_stos_movprfx:1193; CHECK: // %bb.0:1194; CHECK-NEXT: ptrue p0.s1195; CHECK-NEXT: movprfx z0, z11196; CHECK-NEXT: scvtf z0.s, p0/m, z1.s1197; CHECK-NEXT: ret1198 %res = sitofp <vscale x 4 x i32> %b to <vscale x 4 x float>1199 ret <vscale x 4 x float> %res1200}1201 1202define <vscale x 2 x double> @scvtf_stod_movprfx(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {1203; CHECK-LABEL: scvtf_stod_movprfx:1204; CHECK: // %bb.0:1205; CHECK-NEXT: ptrue p0.d1206; CHECK-NEXT: movprfx z0, z11207; CHECK-NEXT: scvtf z0.d, p0/m, z1.s1208; CHECK-NEXT: ret1209 %res = sitofp <vscale x 2 x i32> %b to <vscale x 2 x double>1210 ret <vscale x 2 x double> %res1211}1212 1213define <vscale x 2 x float> @scvtf_dtos_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1214; CHECK-LABEL: scvtf_dtos_movprfx:1215; CHECK: // %bb.0:1216; CHECK-NEXT: ptrue p0.d1217; CHECK-NEXT: movprfx z0, z11218; CHECK-NEXT: scvtf z0.s, p0/m, z1.d1219; CHECK-NEXT: ret1220 %res = sitofp <vscale x 2 x i64> %b to <vscale x 2 x float>1221 ret <vscale x 2 x float> %res1222}1223 1224define <vscale x 4 x half> @scvtf_stoh_movprfx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1225; CHECK-LABEL: scvtf_stoh_movprfx:1226; CHECK: // %bb.0:1227; CHECK-NEXT: ptrue p0.s1228; CHECK-NEXT: movprfx z0, z11229; CHECK-NEXT: scvtf z0.h, p0/m, z1.s1230; CHECK-NEXT: ret1231 %res = sitofp <vscale x 4 x i32> %b to <vscale x 4 x half>1232 ret <vscale x 4 x half> %res1233}1234 1235define <vscale x 2 x half> @scvtf_dtoh_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1236; CHECK-LABEL: scvtf_dtoh_movprfx:1237; CHECK: // %bb.0:1238; CHECK-NEXT: ptrue p0.d1239; CHECK-NEXT: movprfx z0, z11240; CHECK-NEXT: scvtf z0.h, p0/m, z1.d1241; CHECK-NEXT: ret1242 %res = sitofp <vscale x 2 x i64> %b to <vscale x 2 x half>1243 ret <vscale x 2 x half> %res1244}1245 1246define <vscale x 2 x double> @scvtf_dtod_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1247; CHECK-LABEL: scvtf_dtod_movprfx:1248; CHECK: // %bb.0:1249; CHECK-NEXT: ptrue p0.d1250; CHECK-NEXT: movprfx z0, z11251; CHECK-NEXT: scvtf z0.d, p0/m, z1.d1252; CHECK-NEXT: ret1253 %res = sitofp <vscale x 2 x i64> %b to <vscale x 2 x double>1254 ret <vscale x 2 x double> %res1255}1256 1257define <vscale x 4 x float> @ucvtf_stos_movprfx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1258; CHECK-LABEL: ucvtf_stos_movprfx:1259; CHECK: // %bb.0:1260; CHECK-NEXT: ptrue p0.s1261; CHECK-NEXT: movprfx z0, z11262; CHECK-NEXT: ucvtf z0.s, p0/m, z1.s1263; CHECK-NEXT: ret1264 %res = uitofp <vscale x 4 x i32> %b to <vscale x 4 x float>1265 ret <vscale x 4 x float> %res1266}1267 1268define <vscale x 8 x half> @ucvtf_htoh_movprfx(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {1269; CHECK-LABEL: ucvtf_htoh_movprfx:1270; CHECK: // %bb.0:1271; CHECK-NEXT: ptrue p0.h1272; CHECK-NEXT: movprfx z0, z11273; CHECK-NEXT: ucvtf z0.h, p0/m, z1.h1274; CHECK-NEXT: ret1275 %res = uitofp <vscale x 8 x i16> %b to <vscale x 8 x half>1276 ret <vscale x 8 x half> %res1277}1278 1279define <vscale x 2 x double> @ucvtf_stod_movprfx(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {1280; CHECK-LABEL: ucvtf_stod_movprfx:1281; CHECK: // %bb.0:1282; CHECK-NEXT: ptrue p0.d1283; CHECK-NEXT: movprfx z0, z11284; CHECK-NEXT: ucvtf z0.d, p0/m, z1.s1285; CHECK-NEXT: ret1286 %res = uitofp <vscale x 2 x i32> %b to <vscale x 2 x double>1287 ret <vscale x 2 x double> %res1288}1289 1290define <vscale x 4 x half> @ucvtf_stoh_movprfx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1291; CHECK-LABEL: ucvtf_stoh_movprfx:1292; CHECK: // %bb.0:1293; CHECK-NEXT: ptrue p0.s1294; CHECK-NEXT: movprfx z0, z11295; CHECK-NEXT: ucvtf z0.h, p0/m, z1.s1296; CHECK-NEXT: ret1297 %res = uitofp <vscale x 4 x i32> %b to <vscale x 4 x half>1298 ret <vscale x 4 x half> %res1299}1300 1301define <vscale x 2 x float> @ucvtf_dtos_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1302; CHECK-LABEL: ucvtf_dtos_movprfx:1303; CHECK: // %bb.0:1304; CHECK-NEXT: ptrue p0.d1305; CHECK-NEXT: movprfx z0, z11306; CHECK-NEXT: ucvtf z0.s, p0/m, z1.d1307; CHECK-NEXT: ret1308 %res = uitofp <vscale x 2 x i64> %b to <vscale x 2 x float>1309 ret <vscale x 2 x float> %res1310}1311 1312define <vscale x 2 x half> @ucvtf_dtoh_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1313; CHECK-LABEL: ucvtf_dtoh_movprfx:1314; CHECK: // %bb.0:1315; CHECK-NEXT: ptrue p0.d1316; CHECK-NEXT: movprfx z0, z11317; CHECK-NEXT: ucvtf z0.h, p0/m, z1.d1318; CHECK-NEXT: ret1319 %res = uitofp <vscale x 2 x i64> %b to <vscale x 2 x half>1320 ret <vscale x 2 x half> %res1321}1322 1323define <vscale x 2 x double> @ucvtf_dtod_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1324; CHECK-LABEL: ucvtf_dtod_movprfx:1325; CHECK: // %bb.0:1326; CHECK-NEXT: ptrue p0.d1327; CHECK-NEXT: movprfx z0, z11328; CHECK-NEXT: ucvtf z0.d, p0/m, z1.d1329; CHECK-NEXT: ret1330 %res = uitofp <vscale x 2 x i64> %b to <vscale x 2 x double>1331 ret <vscale x 2 x double> %res1332}1333 1334define <vscale x 8 x i16> @fcvtzs_htoh_movprfx(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {1335; CHECK-LABEL: fcvtzs_htoh_movprfx:1336; CHECK: // %bb.0:1337; CHECK-NEXT: ptrue p0.h1338; CHECK-NEXT: movprfx z0, z11339; CHECK-NEXT: fcvtzs z0.h, p0/m, z1.h1340; CHECK-NEXT: ret1341 %res = fptosi <vscale x 8 x half> %b to <vscale x 8 x i16>1342 ret <vscale x 8 x i16> %res1343}1344 1345define <vscale x 4 x i32> @fcvtzs_stos_movprfx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {1346; CHECK-LABEL: fcvtzs_stos_movprfx:1347; CHECK: // %bb.0:1348; CHECK-NEXT: ptrue p0.s1349; CHECK-NEXT: movprfx z0, z11350; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.s1351; CHECK-NEXT: ret1352 %res = fptosi <vscale x 4 x float> %b to <vscale x 4 x i32>1353 ret <vscale x 4 x i32> %res1354}1355 1356define <vscale x 2 x i32> @fcvtzs_dtos_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {1357; CHECK-LABEL: fcvtzs_dtos_movprfx:1358; CHECK: // %bb.0:1359; CHECK-NEXT: ptrue p0.d1360; CHECK-NEXT: movprfx z0, z11361; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.d1362; CHECK-NEXT: ret1363 %res = fptosi <vscale x 2 x double> %b to <vscale x 2 x i32>1364 ret <vscale x 2 x i32> %res1365}1366 1367define <vscale x 2 x i64> @fcvtzs_stod_movprfx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {1368; CHECK-LABEL: fcvtzs_stod_movprfx:1369; CHECK: // %bb.0:1370; CHECK-NEXT: ptrue p0.d1371; CHECK-NEXT: movprfx z0, z11372; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s1373; CHECK-NEXT: ret1374 %res = fptosi <vscale x 2 x float> %b to <vscale x 2 x i64>1375 ret <vscale x 2 x i64> %res1376}1377 1378define <vscale x 4 x i32> @fcvtzs_htos_movprfx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {1379; CHECK-LABEL: fcvtzs_htos_movprfx:1380; CHECK: // %bb.0:1381; CHECK-NEXT: ptrue p0.s1382; CHECK-NEXT: movprfx z0, z11383; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.h1384; CHECK-NEXT: ret1385 %res = fptosi <vscale x 4 x half> %b to <vscale x 4 x i32>1386 ret <vscale x 4 x i32> %res1387}1388 1389define <vscale x 2 x i64> @fcvtzs_htod_movprfx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {1390; CHECK-LABEL: fcvtzs_htod_movprfx:1391; CHECK: // %bb.0:1392; CHECK-NEXT: ptrue p0.d1393; CHECK-NEXT: movprfx z0, z11394; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.h1395; CHECK-NEXT: ret1396 %res = fptosi <vscale x 2 x half> %b to <vscale x 2 x i64>1397 ret <vscale x 2 x i64> %res1398}1399 1400define <vscale x 2 x i64> @fcvtzs_dtod_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {1401; CHECK-LABEL: fcvtzs_dtod_movprfx:1402; CHECK: // %bb.0:1403; CHECK-NEXT: ptrue p0.d1404; CHECK-NEXT: movprfx z0, z11405; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.d1406; CHECK-NEXT: ret1407 %res = fptosi <vscale x 2 x double> %b to <vscale x 2 x i64>1408 ret <vscale x 2 x i64> %res1409}1410 1411define <vscale x 8 x i16> @fcvtzu_htoh_movprfx(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {1412; CHECK-LABEL: fcvtzu_htoh_movprfx:1413; CHECK: // %bb.0:1414; CHECK-NEXT: ptrue p0.h1415; CHECK-NEXT: movprfx z0, z11416; CHECK-NEXT: fcvtzu z0.h, p0/m, z1.h1417; CHECK-NEXT: ret1418 %res = fptoui <vscale x 8 x half> %b to <vscale x 8 x i16>1419 ret <vscale x 8 x i16> %res1420}1421 1422define <vscale x 4 x i32> @fcvtzu_stos_movprfx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {1423; CHECK-LABEL: fcvtzu_stos_movprfx:1424; CHECK: // %bb.0:1425; CHECK-NEXT: ptrue p0.s1426; CHECK-NEXT: movprfx z0, z11427; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.s1428; CHECK-NEXT: ret1429 %res = fptoui <vscale x 4 x float> %b to <vscale x 4 x i32>1430 ret <vscale x 4 x i32> %res1431}1432 1433define <vscale x 2 x i32> @fcvtzu_dtos_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {1434; CHECK-LABEL: fcvtzu_dtos_movprfx:1435; CHECK: // %bb.0:1436; CHECK-NEXT: ptrue p0.d1437; CHECK-NEXT: movprfx z0, z11438; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.d1439; CHECK-NEXT: ret1440 %res = fptoui <vscale x 2 x double> %b to <vscale x 2 x i32>1441 ret <vscale x 2 x i32> %res1442}1443 1444define <vscale x 2 x i64> @fcvtzu_stod_movprfx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {1445; CHECK-LABEL: fcvtzu_stod_movprfx:1446; CHECK: // %bb.0:1447; CHECK-NEXT: ptrue p0.d1448; CHECK-NEXT: movprfx z0, z11449; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.s1450; CHECK-NEXT: ret1451 %res = fptoui <vscale x 2 x float> %b to <vscale x 2 x i64>1452 ret <vscale x 2 x i64> %res1453}1454 1455define <vscale x 4 x i32> @fcvtzu_htos_movprfx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {1456; CHECK-LABEL: fcvtzu_htos_movprfx:1457; CHECK: // %bb.0:1458; CHECK-NEXT: ptrue p0.s1459; CHECK-NEXT: movprfx z0, z11460; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.h1461; CHECK-NEXT: ret1462 %res = fptoui <vscale x 4 x half> %b to <vscale x 4 x i32>1463 ret <vscale x 4 x i32> %res1464}1465 1466define <vscale x 2 x i64> @fcvtzu_htod_movprfx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {1467; CHECK-LABEL: fcvtzu_htod_movprfx:1468; CHECK: // %bb.0:1469; CHECK-NEXT: ptrue p0.d1470; CHECK-NEXT: movprfx z0, z11471; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.h1472; CHECK-NEXT: ret1473 %res = fptoui <vscale x 2 x half> %b to <vscale x 2 x i64>1474 ret <vscale x 2 x i64> %res1475}1476 1477define <vscale x 2 x i64> @fcvtzu_dtod_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {1478; CHECK-LABEL: fcvtzu_dtod_movprfx:1479; CHECK: // %bb.0:1480; CHECK-NEXT: ptrue p0.d1481; CHECK-NEXT: movprfx z0, z11482; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.d1483; CHECK-NEXT: ret1484 %res = fptoui <vscale x 2 x double> %b to <vscale x 2 x i64>1485 ret <vscale x 2 x i64> %res1486}1487