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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s3; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s4 5target triple = "aarch64-unknown-linux-gnu"6 7define void @masked_gather_base_plus_stride_v8f32(ptr %dst, ptr %src) #0 {8; CHECK-LABEL: masked_gather_base_plus_stride_v8f32:9; CHECK: // %bb.0:10; CHECK-NEXT: index z0.s, #0, #711; CHECK-NEXT: ptrue p0.s, vl812; CHECK-NEXT: ld1w { z0.s }, p0/z, [x1, z0.s, sxtw #2]13; CHECK-NEXT: st1w { z0.s }, p0, [x0]14; CHECK-NEXT: ret15 %ptrs = getelementptr float, ptr %src, <8 x i64> <i64 0, i64 7, i64 14, i64 21, i64 28, i64 35, i64 42, i64 49>16 %data = tail call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x float> poison)17 store <8 x float> %data, ptr %dst, align 418 ret void19}20 21define void @masked_gather_base_plus_stride_v4f64(ptr %dst, ptr %src) #0 {22; CHECK-LABEL: masked_gather_base_plus_stride_v4f64:23; CHECK: // %bb.0:24; CHECK-NEXT: mov x8, #-32 // =0xffffffffffffffe025; CHECK-NEXT: ptrue p0.d, vl426; CHECK-NEXT: index z0.d, #-2, x827; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1, z0.d, lsl #3]28; CHECK-NEXT: st1d { z0.d }, p0, [x0]29; CHECK-NEXT: ret30 %ptrs = getelementptr double, ptr %src, <4 x i64> <i64 -2, i64 -34, i64 -66, i64 -98>31 %data = tail call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 true), <4 x double> poison)32 store <4 x double> %data, ptr %dst, align 833 ret void34}35 36define void @masked_scatter_base_plus_stride_v8f32(ptr %dst, ptr %src) #0 {37; CHECK-LABEL: masked_scatter_base_plus_stride_v8f32:38; CHECK: // %bb.0:39; CHECK-NEXT: ptrue p0.s, vl840; CHECK-NEXT: index z0.s, #0, #-741; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]42; CHECK-NEXT: st1w { z1.s }, p0, [x0, z0.s, sxtw #2]43; CHECK-NEXT: ret44 %data = load <8 x float>, ptr %src, align 445 %ptrs = getelementptr float, ptr %dst, <8 x i64> <i64 0, i64 -7, i64 -14, i64 -21, i64 -28, i64 -35, i64 -42, i64 -49>46 tail call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %data, <8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true))47 ret void48}49 50define void @masked_scatter_base_plus_stride_v4f64(ptr %dst, ptr %src) #0 {51; CHECK-LABEL: masked_scatter_base_plus_stride_v4f64:52; CHECK: // %bb.0:53; CHECK-NEXT: ptrue p0.d, vl454; CHECK-NEXT: index z0.d, #-2, #355; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]56; CHECK-NEXT: st1d { z1.d }, p0, [x0, z0.d, lsl #3]57; CHECK-NEXT: ret58 %data = load <4 x double>, ptr %src, align 859 %ptrs = getelementptr double, ptr %dst, <4 x i64> <i64 -2, i64 1, i64 4, i64 7>60 tail call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> %data, <4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 true))61 ret void62}63 64declare <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr>, i32 immarg, <8 x i1>, <8 x float>)65declare <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr>, i32 immarg, <4 x i1>, <4 x double>)66 67declare void @llvm.masked.scatter.v8f32.v8p0(<8 x float>, <8 x ptr>, i32 immarg, <8 x i1>)68declare void @llvm.masked.scatter.v4f64.v4p0(<4 x double>, <4 x ptr>, i32 immarg, <4 x i1>)69 70attributes #0 = { "target-features"="+sve" }71