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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=1024 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_10243; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_20484 5target triple = "aarch64-unknown-linux-gnu"6 7define <4 x i32> @load_zext_v4i16i32(ptr %ap) vscale_range(2,0) #0 {8; CHECK-LABEL: load_zext_v4i16i32:9; CHECK: // %bb.0:10; CHECK-NEXT: ldp s0, s1, [x0]11; CHECK-NEXT: ushll v0.4s, v0.4h, #012; CHECK-NEXT: ushll v1.4s, v1.4h, #013; CHECK-NEXT: mov v0.d[1], v1.d[0]14; CHECK-NEXT: ret15 %a = load <4 x i16>, ptr %ap16 %val = zext <4 x i16> %a to <4 x i32>17 ret <4 x i32> %val18}19 20; Don't try to use SVE for irregular types.21define <2 x i256> @load_zext_v2i64i256(ptr %ap) #0 {22; CHECK-LABEL: load_zext_v2i64i256:23; CHECK: // %bb.0:24; CHECK-NEXT: ldp x0, x4, [x0]25; CHECK-NEXT: mov x1, xzr26; CHECK-NEXT: mov x2, xzr27; CHECK-NEXT: mov x3, xzr28; CHECK-NEXT: mov x5, xzr29; CHECK-NEXT: mov x6, xzr30; CHECK-NEXT: mov x7, xzr31; CHECK-NEXT: ret32 %a = load <2 x i64>, ptr %ap33 %val = zext <2 x i64> %a to <2 x i256>34 ret <2 x i256> %val35}36 37define void @load_zext_v8i16i32(ptr %ap, ptr %b) vscale_range(2,0) #0 {38; CHECK-LABEL: load_zext_v8i16i32:39; CHECK: // %bb.0:40; CHECK-NEXT: ptrue p0.s, vl841; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]42; CHECK-NEXT: st1w { z0.s }, p0, [x1]43; CHECK-NEXT: ret44 %a = load <8 x i16>, ptr %ap45 %val = zext <8 x i16> %a to <8 x i32>46 store <8 x i32> %val, ptr %b47 ret void48}49 50define void @load_zext_v16i16i32(ptr %ap, ptr %b) vscale_range(4,0) #0 {51; CHECK-LABEL: load_zext_v16i16i32:52; CHECK: // %bb.0:53; CHECK-NEXT: ptrue p0.s, vl1654; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]55; CHECK-NEXT: st1w { z0.s }, p0, [x1]56; CHECK-NEXT: ret57 %a = load <16 x i16>, ptr %ap58 %val = zext <16 x i16> %a to <16 x i32>59 store <16 x i32> %val, ptr %b60 ret void61}62 63define void @load_zext_v32i16i32(ptr %ap, ptr %b) vscale_range(8,0) #0 {64; CHECK-LABEL: load_zext_v32i16i32:65; CHECK: // %bb.0:66; CHECK-NEXT: ptrue p0.s, vl3267; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]68; CHECK-NEXT: st1w { z0.s }, p0, [x1]69; CHECK-NEXT: ret70 %a = load <32 x i16>, ptr %ap71 %val = zext <32 x i16> %a to <32 x i32>72 store <32 x i32> %val, ptr %b73 ret void74}75 76define void @load_zext_v64i16i32(ptr %ap, ptr %b) #0 {77; VBITS_GE_1024-LABEL: load_zext_v64i16i32:78; VBITS_GE_1024: // %bb.0:79; VBITS_GE_1024-NEXT: ptrue p0.s, vl3280; VBITS_GE_1024-NEXT: mov x8, #32 // =0x2081; VBITS_GE_1024-NEXT: ld1h { z0.s }, p0/z, [x0, x8, lsl #1]82; VBITS_GE_1024-NEXT: ld1h { z1.s }, p0/z, [x0]83; VBITS_GE_1024-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]84; VBITS_GE_1024-NEXT: st1w { z1.s }, p0, [x1]85; VBITS_GE_1024-NEXT: ret86;87; VBITS_GE_2048-LABEL: load_zext_v64i16i32:88; VBITS_GE_2048: // %bb.0:89; VBITS_GE_2048-NEXT: ptrue p0.s, vl6490; VBITS_GE_2048-NEXT: ld1h { z0.s }, p0/z, [x0]91; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x1]92; VBITS_GE_2048-NEXT: ret93 %a = load <64 x i16>, ptr %ap94 %val = zext <64 x i16> %a to <64 x i32>95 store <64 x i32> %val, ptr %b96 ret void97}98 99define <4 x i32> @load_sext_v4i16i32(ptr %ap) vscale_range(2,0) #0 {100; CHECK-LABEL: load_sext_v4i16i32:101; CHECK: // %bb.0:102; CHECK-NEXT: ldp s0, s1, [x0]103; CHECK-NEXT: sshll v0.4s, v0.4h, #0104; CHECK-NEXT: sshll v1.4s, v1.4h, #0105; CHECK-NEXT: mov v0.d[1], v1.d[0]106; CHECK-NEXT: ret107 %a = load <4 x i16>, ptr %ap108 %val = sext <4 x i16> %a to <4 x i32>109 ret <4 x i32> %val110}111 112define void @load_sext_v8i16i32(ptr %ap, ptr %b) vscale_range(2,0) #0 {113; CHECK-LABEL: load_sext_v8i16i32:114; CHECK: // %bb.0:115; CHECK-NEXT: ptrue p0.s, vl8116; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0]117; CHECK-NEXT: st1w { z0.s }, p0, [x1]118; CHECK-NEXT: ret119 %a = load <8 x i16>, ptr %ap120 %val = sext <8 x i16> %a to <8 x i32>121 store <8 x i32> %val, ptr %b122 ret void123}124 125define void @load_sext_v16i16i32(ptr %ap, ptr %b) vscale_range(4,0) #0 {126; CHECK-LABEL: load_sext_v16i16i32:127; CHECK: // %bb.0:128; CHECK-NEXT: ptrue p0.s, vl16129; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0]130; CHECK-NEXT: st1w { z0.s }, p0, [x1]131; CHECK-NEXT: ret132 %a = load <16 x i16>, ptr %ap133 %val = sext <16 x i16> %a to <16 x i32>134 store <16 x i32> %val, ptr %b135 ret void136}137 138define void @load_sext_v32i16i32(ptr %ap, ptr %b) vscale_range(8,0) #0 {139; CHECK-LABEL: load_sext_v32i16i32:140; CHECK: // %bb.0:141; CHECK-NEXT: ptrue p0.s, vl32142; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0]143; CHECK-NEXT: st1w { z0.s }, p0, [x1]144; CHECK-NEXT: ret145 %a = load <32 x i16>, ptr %ap146 %val = sext <32 x i16> %a to <32 x i32>147 store <32 x i32> %val, ptr %b148 ret void149}150 151define void @load_sext_v64i16i32(ptr %ap, ptr %b) #0 {152; VBITS_GE_1024-LABEL: load_sext_v64i16i32:153; VBITS_GE_1024: // %bb.0:154; VBITS_GE_1024-NEXT: ptrue p0.s, vl32155; VBITS_GE_1024-NEXT: mov x8, #32 // =0x20156; VBITS_GE_1024-NEXT: ld1sh { z0.s }, p0/z, [x0, x8, lsl #1]157; VBITS_GE_1024-NEXT: ld1sh { z1.s }, p0/z, [x0]158; VBITS_GE_1024-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]159; VBITS_GE_1024-NEXT: st1w { z1.s }, p0, [x1]160; VBITS_GE_1024-NEXT: ret161;162; VBITS_GE_2048-LABEL: load_sext_v64i16i32:163; VBITS_GE_2048: // %bb.0:164; VBITS_GE_2048-NEXT: ptrue p0.s, vl64165; VBITS_GE_2048-NEXT: ld1sh { z0.s }, p0/z, [x0]166; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x1]167; VBITS_GE_2048-NEXT: ret168 %a = load <64 x i16>, ptr %ap169 %val = sext <64 x i16> %a to <64 x i32>170 store <64 x i32> %val, ptr %b171 ret void172}173 174define void @load_zext_v32i8i64(ptr %ap, ptr %b) #0 {175; VBITS_GE_1024-LABEL: load_zext_v32i8i64:176; VBITS_GE_1024: // %bb.0:177; VBITS_GE_1024-NEXT: ptrue p0.d, vl16178; VBITS_GE_1024-NEXT: mov w8, #16 // =0x10179; VBITS_GE_1024-NEXT: ld1b { z0.d }, p0/z, [x0, x8]180; VBITS_GE_1024-NEXT: ld1b { z1.d }, p0/z, [x0]181; VBITS_GE_1024-NEXT: mov x8, #16 // =0x10182; VBITS_GE_1024-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]183; VBITS_GE_1024-NEXT: st1d { z1.d }, p0, [x1]184; VBITS_GE_1024-NEXT: ret185;186; VBITS_GE_2048-LABEL: load_zext_v32i8i64:187; VBITS_GE_2048: // %bb.0:188; VBITS_GE_2048-NEXT: ptrue p0.d, vl32189; VBITS_GE_2048-NEXT: ld1b { z0.d }, p0/z, [x0]190; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x1]191; VBITS_GE_2048-NEXT: ret192 %a = load <32 x i8>, ptr %ap193 %val = zext <32 x i8> %a to <32 x i64>194 store <32 x i64> %val, ptr %b195 ret void196}197 198define void @load_sext_v32i8i64(ptr %ap, ptr %b) #0 {199; VBITS_GE_1024-LABEL: load_sext_v32i8i64:200; VBITS_GE_1024: // %bb.0:201; VBITS_GE_1024-NEXT: ptrue p0.d, vl16202; VBITS_GE_1024-NEXT: mov w8, #16 // =0x10203; VBITS_GE_1024-NEXT: ld1sb { z0.d }, p0/z, [x0, x8]204; VBITS_GE_1024-NEXT: ld1sb { z1.d }, p0/z, [x0]205; VBITS_GE_1024-NEXT: mov x8, #16 // =0x10206; VBITS_GE_1024-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]207; VBITS_GE_1024-NEXT: st1d { z1.d }, p0, [x1]208; VBITS_GE_1024-NEXT: ret209;210; VBITS_GE_2048-LABEL: load_sext_v32i8i64:211; VBITS_GE_2048: // %bb.0:212; VBITS_GE_2048-NEXT: ptrue p0.d, vl32213; VBITS_GE_2048-NEXT: ld1sb { z0.d }, p0/z, [x0]214; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x1]215; VBITS_GE_2048-NEXT: ret216 %a = load <32 x i8>, ptr %ap217 %val = sext <32 x i8> %a to <32 x i64>218 store <32 x i64> %val, ptr %b219 ret void220}221 222define void @load_zext_v32i16i64(ptr %ap, ptr %b) #0 {223; VBITS_GE_1024-LABEL: load_zext_v32i16i64:224; VBITS_GE_1024: // %bb.0:225; VBITS_GE_1024-NEXT: ptrue p0.d, vl16226; VBITS_GE_1024-NEXT: mov x8, #16 // =0x10227; VBITS_GE_1024-NEXT: ld1h { z0.d }, p0/z, [x0, x8, lsl #1]228; VBITS_GE_1024-NEXT: ld1h { z1.d }, p0/z, [x0]229; VBITS_GE_1024-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]230; VBITS_GE_1024-NEXT: st1d { z1.d }, p0, [x1]231; VBITS_GE_1024-NEXT: ret232;233; VBITS_GE_2048-LABEL: load_zext_v32i16i64:234; VBITS_GE_2048: // %bb.0:235; VBITS_GE_2048-NEXT: ptrue p0.d, vl32236; VBITS_GE_2048-NEXT: ld1h { z0.d }, p0/z, [x0]237; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x1]238; VBITS_GE_2048-NEXT: ret239 %a = load <32 x i16>, ptr %ap240 %val = zext <32 x i16> %a to <32 x i64>241 store <32 x i64> %val, ptr %b242 ret void243}244 245define void @load_sext_v32i16i64(ptr %ap, ptr %b) #0 {246; VBITS_GE_1024-LABEL: load_sext_v32i16i64:247; VBITS_GE_1024: // %bb.0:248; VBITS_GE_1024-NEXT: ptrue p0.d, vl16249; VBITS_GE_1024-NEXT: mov x8, #16 // =0x10250; VBITS_GE_1024-NEXT: ld1sh { z0.d }, p0/z, [x0, x8, lsl #1]251; VBITS_GE_1024-NEXT: ld1sh { z1.d }, p0/z, [x0]252; VBITS_GE_1024-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]253; VBITS_GE_1024-NEXT: st1d { z1.d }, p0, [x1]254; VBITS_GE_1024-NEXT: ret255;256; VBITS_GE_2048-LABEL: load_sext_v32i16i64:257; VBITS_GE_2048: // %bb.0:258; VBITS_GE_2048-NEXT: ptrue p0.d, vl32259; VBITS_GE_2048-NEXT: ld1sh { z0.d }, p0/z, [x0]260; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x1]261; VBITS_GE_2048-NEXT: ret262 %a = load <32 x i16>, ptr %ap263 %val = sext <32 x i16> %a to <32 x i64>264 store <32 x i64> %val, ptr %b265 ret void266}267 268define void @load_zext_v32i32i64(ptr %ap, ptr %b) #0 {269; VBITS_GE_1024-LABEL: load_zext_v32i32i64:270; VBITS_GE_1024: // %bb.0:271; VBITS_GE_1024-NEXT: ptrue p0.d, vl16272; VBITS_GE_1024-NEXT: mov x8, #16 // =0x10273; VBITS_GE_1024-NEXT: ld1w { z0.d }, p0/z, [x0, x8, lsl #2]274; VBITS_GE_1024-NEXT: ld1w { z1.d }, p0/z, [x0]275; VBITS_GE_1024-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]276; VBITS_GE_1024-NEXT: st1d { z1.d }, p0, [x1]277; VBITS_GE_1024-NEXT: ret278;279; VBITS_GE_2048-LABEL: load_zext_v32i32i64:280; VBITS_GE_2048: // %bb.0:281; VBITS_GE_2048-NEXT: ptrue p0.d, vl32282; VBITS_GE_2048-NEXT: ld1w { z0.d }, p0/z, [x0]283; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x1]284; VBITS_GE_2048-NEXT: ret285 %a = load <32 x i32>, ptr %ap286 %val = zext <32 x i32> %a to <32 x i64>287 store <32 x i64> %val, ptr %b288 ret void289}290 291define void @load_sext_v32i32i64(ptr %ap, ptr %b) #0 {292; VBITS_GE_1024-LABEL: load_sext_v32i32i64:293; VBITS_GE_1024: // %bb.0:294; VBITS_GE_1024-NEXT: ptrue p0.d, vl16295; VBITS_GE_1024-NEXT: mov x8, #16 // =0x10296; VBITS_GE_1024-NEXT: ld1sw { z0.d }, p0/z, [x0, x8, lsl #2]297; VBITS_GE_1024-NEXT: ld1sw { z1.d }, p0/z, [x0]298; VBITS_GE_1024-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]299; VBITS_GE_1024-NEXT: st1d { z1.d }, p0, [x1]300; VBITS_GE_1024-NEXT: ret301;302; VBITS_GE_2048-LABEL: load_sext_v32i32i64:303; VBITS_GE_2048: // %bb.0:304; VBITS_GE_2048-NEXT: ptrue p0.d, vl32305; VBITS_GE_2048-NEXT: ld1sw { z0.d }, p0/z, [x0]306; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x1]307; VBITS_GE_2048-NEXT: ret308 %a = load <32 x i32>, ptr %ap309 %val = sext <32 x i32> %a to <32 x i64>310 store <32 x i64> %val, ptr %b311 ret void312}313 314attributes #0 = { "target-features"="+sve" }315