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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; extractelement10;11 12; Don't use SVE for 64-bit vectors.13define half @extractelement_v4f16(<4 x half> %op1) vscale_range(2,0) #0 {14; CHECK-LABEL: extractelement_v4f16:15; CHECK: // %bb.0:16; CHECK-NEXT: // kill: def $d0 killed $d0 def $q017; CHECK-NEXT: mov h0, v0.h[3]18; CHECK-NEXT: ret19 %r = extractelement <4 x half> %op1, i64 320 ret half %r21}22 23; Don't use SVE for 128-bit vectors.24define half @extractelement_v8f16(<8 x half> %op1) vscale_range(2,0) #0 {25; CHECK-LABEL: extractelement_v8f16:26; CHECK: // %bb.0:27; CHECK-NEXT: mov h0, v0.h[7]28; CHECK-NEXT: ret29 %r = extractelement <8 x half> %op1, i64 730 ret half %r31}32 33define half @extractelement_v16f16(ptr %a) vscale_range(2,0) #0 {34; CHECK-LABEL: extractelement_v16f16:35; CHECK: // %bb.0:36; CHECK-NEXT: ptrue p0.h, vl1637; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]38; CHECK-NEXT: mov z0.h, z0.h[15]39; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z040; CHECK-NEXT: ret41 %op1 = load <16 x half>, ptr %a42 %r = extractelement <16 x half> %op1, i64 1543 ret half %r44}45 46define half @extractelement_v32f16(ptr %a) #0 {47; VBITS_GE_256-LABEL: extractelement_v32f16:48; VBITS_GE_256: // %bb.0:49; VBITS_GE_256-NEXT: ptrue p0.h, vl1650; VBITS_GE_256-NEXT: mov x8, #16 // =0x1051; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]52; VBITS_GE_256-NEXT: mov z0.h, z0.h[15]53; VBITS_GE_256-NEXT: // kill: def $h0 killed $h0 killed $z054; VBITS_GE_256-NEXT: ret55;56; VBITS_GE_512-LABEL: extractelement_v32f16:57; VBITS_GE_512: // %bb.0:58; VBITS_GE_512-NEXT: ptrue p0.h, vl3259; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]60; VBITS_GE_512-NEXT: mov z0.h, z0.h[31]61; VBITS_GE_512-NEXT: // kill: def $h0 killed $h0 killed $z062; VBITS_GE_512-NEXT: ret63 %op1 = load <32 x half>, ptr %a64 %r = extractelement <32 x half> %op1, i64 3165 ret half %r66}67 68define half @extractelement_v64f16(ptr %a) vscale_range(8,0) #0 {69; CHECK-LABEL: extractelement_v64f16:70; CHECK: // %bb.0:71; CHECK-NEXT: ptrue p0.h, vl6472; CHECK-NEXT: mov w8, #63 // =0x3f73; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]74; CHECK-NEXT: whilels p0.h, xzr, x875; CHECK-NEXT: lastb h0, p0, z0.h76; CHECK-NEXT: ret77 %op1 = load <64 x half>, ptr %a78 %r = extractelement <64 x half> %op1, i64 6379 ret half %r80}81 82define half @extractelement_v128f16(ptr %a) vscale_range(16,0) #0 {83; CHECK-LABEL: extractelement_v128f16:84; CHECK: // %bb.0:85; CHECK-NEXT: ptrue p0.h, vl12886; CHECK-NEXT: mov w8, #127 // =0x7f87; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]88; CHECK-NEXT: whilels p0.h, xzr, x889; CHECK-NEXT: lastb h0, p0, z0.h90; CHECK-NEXT: ret91 %op1 = load <128 x half>, ptr %a92 %r = extractelement <128 x half> %op1, i64 12793 ret half %r94}95 96; Don't use SVE for 64-bit vectors.97define float @extractelement_v2f32(<2 x float> %op1) vscale_range(2,0) #0 {98; CHECK-LABEL: extractelement_v2f32:99; CHECK: // %bb.0:100; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0101; CHECK-NEXT: mov s0, v0.s[1]102; CHECK-NEXT: ret103 %r = extractelement <2 x float> %op1, i64 1104 ret float %r105}106 107; Don't use SVE for 128-bit vectors.108define float @extractelement_v4f32(<4 x float> %op1) vscale_range(2,0) #0 {109; CHECK-LABEL: extractelement_v4f32:110; CHECK: // %bb.0:111; CHECK-NEXT: mov s0, v0.s[3]112; CHECK-NEXT: ret113 %r = extractelement <4 x float> %op1, i64 3114 ret float %r115}116 117define float @extractelement_v8f32(ptr %a) vscale_range(2,0) #0 {118; CHECK-LABEL: extractelement_v8f32:119; CHECK: // %bb.0:120; CHECK-NEXT: ptrue p0.s, vl8121; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]122; CHECK-NEXT: mov z0.s, z0.s[7]123; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0124; CHECK-NEXT: ret125 %op1 = load <8 x float>, ptr %a126 %r = extractelement <8 x float> %op1, i64 7127 ret float %r128}129 130define float @extractelement_v16f32(ptr %a) #0 {131; VBITS_GE_256-LABEL: extractelement_v16f32:132; VBITS_GE_256: // %bb.0:133; VBITS_GE_256-NEXT: ptrue p0.s, vl8134; VBITS_GE_256-NEXT: mov x8, #8 // =0x8135; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]136; VBITS_GE_256-NEXT: mov z0.s, z0.s[7]137; VBITS_GE_256-NEXT: // kill: def $s0 killed $s0 killed $z0138; VBITS_GE_256-NEXT: ret139;140; VBITS_GE_512-LABEL: extractelement_v16f32:141; VBITS_GE_512: // %bb.0:142; VBITS_GE_512-NEXT: ptrue p0.s, vl16143; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]144; VBITS_GE_512-NEXT: mov z0.s, z0.s[15]145; VBITS_GE_512-NEXT: // kill: def $s0 killed $s0 killed $z0146; VBITS_GE_512-NEXT: ret147 %op1 = load <16 x float>, ptr %a148 %r = extractelement <16 x float> %op1, i64 15149 ret float %r150}151 152define float @extractelement_v32f32(ptr %a) vscale_range(8,0) #0 {153; CHECK-LABEL: extractelement_v32f32:154; CHECK: // %bb.0:155; CHECK-NEXT: ptrue p0.s, vl32156; CHECK-NEXT: mov w8, #31 // =0x1f157; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]158; CHECK-NEXT: whilels p0.s, xzr, x8159; CHECK-NEXT: lastb s0, p0, z0.s160; CHECK-NEXT: ret161 %op1 = load <32 x float>, ptr %a162 %r = extractelement <32 x float> %op1, i64 31163 ret float %r164}165 166define float @extractelement_v64f32(ptr %a) vscale_range(16,0) #0 {167; CHECK-LABEL: extractelement_v64f32:168; CHECK: // %bb.0:169; CHECK-NEXT: ptrue p0.s, vl64170; CHECK-NEXT: mov w8, #63 // =0x3f171; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]172; CHECK-NEXT: whilels p0.s, xzr, x8173; CHECK-NEXT: lastb s0, p0, z0.s174; CHECK-NEXT: ret175 %op1 = load <64 x float>, ptr %a176 %r = extractelement <64 x float> %op1, i64 63177 ret float %r178}179 180; Don't use SVE for 64-bit vectors.181define double @extractelement_v1f64(<1 x double> %op1) vscale_range(2,0) #0 {182; CHECK-LABEL: extractelement_v1f64:183; CHECK: // %bb.0:184; CHECK-NEXT: ret185 %r = extractelement <1 x double> %op1, i64 0186 ret double %r187}188 189; Don't use SVE for 128-bit vectors.190define double @extractelement_v2f64(<2 x double> %op1) vscale_range(2,0) #0 {191; CHECK-LABEL: extractelement_v2f64:192; CHECK: // %bb.0:193; CHECK-NEXT: mov d0, v0.d[1]194; CHECK-NEXT: ret195 %r = extractelement <2 x double> %op1, i64 1196 ret double %r197}198 199define double @extractelement_v4f64(ptr %a) vscale_range(2,0) #0 {200; CHECK-LABEL: extractelement_v4f64:201; CHECK: // %bb.0:202; CHECK-NEXT: ptrue p0.d, vl4203; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]204; CHECK-NEXT: mov z0.d, z0.d[3]205; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0206; CHECK-NEXT: ret207 %op1 = load <4 x double>, ptr %a208 %r = extractelement <4 x double> %op1, i64 3209 ret double %r210}211 212define double @extractelement_v8f64(ptr %a) #0 {213; VBITS_GE_256-LABEL: extractelement_v8f64:214; VBITS_GE_256: // %bb.0:215; VBITS_GE_256-NEXT: ptrue p0.d, vl4216; VBITS_GE_256-NEXT: mov x8, #4 // =0x4217; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]218; VBITS_GE_256-NEXT: mov z0.d, z0.d[3]219; VBITS_GE_256-NEXT: // kill: def $d0 killed $d0 killed $z0220; VBITS_GE_256-NEXT: ret221;222; VBITS_GE_512-LABEL: extractelement_v8f64:223; VBITS_GE_512: // %bb.0:224; VBITS_GE_512-NEXT: ptrue p0.d, vl8225; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]226; VBITS_GE_512-NEXT: mov z0.d, z0.d[7]227; VBITS_GE_512-NEXT: // kill: def $d0 killed $d0 killed $z0228; VBITS_GE_512-NEXT: ret229 %op1 = load <8 x double>, ptr %a230 %r = extractelement <8 x double> %op1, i64 7231 ret double %r232}233 234define double @extractelement_v16f64(ptr %a) vscale_range(8,0) #0 {235; CHECK-LABEL: extractelement_v16f64:236; CHECK: // %bb.0:237; CHECK-NEXT: ptrue p0.d, vl16238; CHECK-NEXT: mov w8, #15 // =0xf239; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]240; CHECK-NEXT: whilels p0.d, xzr, x8241; CHECK-NEXT: lastb d0, p0, z0.d242; CHECK-NEXT: ret243 %op1 = load <16 x double>, ptr %a244 %r = extractelement <16 x double> %op1, i64 15245 ret double %r246}247 248define double @extractelement_v32f64(ptr %a) vscale_range(16,0) #0 {249; CHECK-LABEL: extractelement_v32f64:250; CHECK: // %bb.0:251; CHECK-NEXT: ptrue p0.d, vl32252; CHECK-NEXT: mov w8, #31 // =0x1f253; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]254; CHECK-NEXT: whilels p0.d, xzr, x8255; CHECK-NEXT: lastb d0, p0, z0.d256; CHECK-NEXT: ret257 %op1 = load <32 x double>, ptr %a258 %r = extractelement <32 x double> %op1, i64 31259 ret double %r260}261 262attributes #0 = { "target-features"="+sve" }263