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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"7 8target triple = "aarch64-unknown-linux-gnu"9 10;============ f1611 12define void @test_copysign_v4f16_v4f16(ptr %ap, ptr %bp) vscale_range(2,0) #0 {13; CHECK-LABEL: test_copysign_v4f16_v4f16:14; CHECK: // %bb.0:15; CHECK-NEXT: mvni v0.4h, #128, lsl #816; CHECK-NEXT: ldr d1, [x0]17; CHECK-NEXT: ldr d2, [x1]18; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b19; CHECK-NEXT: str d0, [x0]20; CHECK-NEXT: ret21 %a = load <4 x half>, ptr %ap22 %b = load <4 x half>, ptr %bp23 %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b)24 store <4 x half> %r, ptr %ap25 ret void26}27 28define void @test_copysign_v8f16_v8f16(ptr %ap, ptr %bp) vscale_range(2,0) #0 {29; CHECK-LABEL: test_copysign_v8f16_v8f16:30; CHECK: // %bb.0:31; CHECK-NEXT: mvni v0.8h, #128, lsl #832; CHECK-NEXT: ldr q1, [x0]33; CHECK-NEXT: ldr q2, [x1]34; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b35; CHECK-NEXT: str q0, [x0]36; CHECK-NEXT: ret37 %a = load <8 x half>, ptr %ap38 %b = load <8 x half>, ptr %bp39 %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b)40 store <8 x half> %r, ptr %ap41 ret void42}43 44define void @test_copysign_v16f16_v16f16(ptr %ap, ptr %bp) vscale_range(2,0) #0 {45; CHECK-LABEL: test_copysign_v16f16_v16f16:46; CHECK: // %bb.0:47; CHECK-NEXT: ptrue p0.h, vl1648; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]49; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]50; CHECK-NEXT: and z1.h, z1.h, #0x800051; CHECK-NEXT: and z0.h, z0.h, #0x7fff52; CHECK-NEXT: orr z0.d, z0.d, z1.d53; CHECK-NEXT: st1h { z0.h }, p0, [x0]54; CHECK-NEXT: ret55 %a = load <16 x half>, ptr %ap56 %b = load <16 x half>, ptr %bp57 %r = call <16 x half> @llvm.copysign.v16f16(<16 x half> %a, <16 x half> %b)58 store <16 x half> %r, ptr %ap59 ret void60}61 62define void @test_copysign_v32f16_v32f16(ptr %ap, ptr %bp) #0 {63; VBITS_GE_256-LABEL: test_copysign_v32f16_v32f16:64; VBITS_GE_256: // %bb.0:65; VBITS_GE_256-NEXT: ptrue p0.h, vl1666; VBITS_GE_256-NEXT: mov x8, #16 // =0x1067; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]68; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]69; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]70; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]71; VBITS_GE_256-NEXT: and z1.h, z1.h, #0x800072; VBITS_GE_256-NEXT: and z0.h, z0.h, #0x7fff73; VBITS_GE_256-NEXT: and z2.h, z2.h, #0x7fff74; VBITS_GE_256-NEXT: and z3.h, z3.h, #0x800075; VBITS_GE_256-NEXT: orr z0.d, z0.d, z1.d76; VBITS_GE_256-NEXT: orr z1.d, z2.d, z3.d77; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]78; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x0]79; VBITS_GE_256-NEXT: ret80;81; VBITS_GE_512-LABEL: test_copysign_v32f16_v32f16:82; VBITS_GE_512: // %bb.0:83; VBITS_GE_512-NEXT: ptrue p0.h, vl3284; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]85; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]86; VBITS_GE_512-NEXT: and z1.h, z1.h, #0x800087; VBITS_GE_512-NEXT: and z0.h, z0.h, #0x7fff88; VBITS_GE_512-NEXT: orr z0.d, z0.d, z1.d89; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]90; VBITS_GE_512-NEXT: ret91 %a = load <32 x half>, ptr %ap92 %b = load <32 x half>, ptr %bp93 %r = call <32 x half> @llvm.copysign.v32f16(<32 x half> %a, <32 x half> %b)94 store <32 x half> %r, ptr %ap95 ret void96}97 98define void @test_copysign_v64f16_v64f16(ptr %ap, ptr %bp) vscale_range(8,0) #0 {99; CHECK-LABEL: test_copysign_v64f16_v64f16:100; CHECK: // %bb.0:101; CHECK-NEXT: ptrue p0.h, vl64102; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]103; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]104; CHECK-NEXT: and z1.h, z1.h, #0x8000105; CHECK-NEXT: and z0.h, z0.h, #0x7fff106; CHECK-NEXT: orr z0.d, z0.d, z1.d107; CHECK-NEXT: st1h { z0.h }, p0, [x0]108; CHECK-NEXT: ret109 %a = load <64 x half>, ptr %ap110 %b = load <64 x half>, ptr %bp111 %r = call <64 x half> @llvm.copysign.v64f16(<64 x half> %a, <64 x half> %b)112 store <64 x half> %r, ptr %ap113 ret void114}115 116define void @test_copysign_v128f16_v128f16(ptr %ap, ptr %bp) vscale_range(16,0) #0 {117; CHECK-LABEL: test_copysign_v128f16_v128f16:118; CHECK: // %bb.0:119; CHECK-NEXT: ptrue p0.h, vl128120; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]121; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]122; CHECK-NEXT: and z1.h, z1.h, #0x8000123; CHECK-NEXT: and z0.h, z0.h, #0x7fff124; CHECK-NEXT: orr z0.d, z0.d, z1.d125; CHECK-NEXT: st1h { z0.h }, p0, [x0]126; CHECK-NEXT: ret127 %a = load <128 x half>, ptr %ap128 %b = load <128 x half>, ptr %bp129 %r = call <128 x half> @llvm.copysign.v128f16(<128 x half> %a, <128 x half> %b)130 store <128 x half> %r, ptr %ap131 ret void132}133 134;============ f32135 136define void @test_copysign_v2f32_v2f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {137; CHECK-LABEL: test_copysign_v2f32_v2f32:138; CHECK: // %bb.0:139; CHECK-NEXT: mvni v0.2s, #128, lsl #24140; CHECK-NEXT: ldr d1, [x0]141; CHECK-NEXT: ldr d2, [x1]142; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b143; CHECK-NEXT: str d0, [x0]144; CHECK-NEXT: ret145 %a = load <2 x float>, ptr %ap146 %b = load <2 x float>, ptr %bp147 %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b)148 store <2 x float> %r, ptr %ap149 ret void150}151 152define void @test_copysign_v4f32_v4f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {153; CHECK-LABEL: test_copysign_v4f32_v4f32:154; CHECK: // %bb.0:155; CHECK-NEXT: mvni v0.4s, #128, lsl #24156; CHECK-NEXT: ldr q1, [x0]157; CHECK-NEXT: ldr q2, [x1]158; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b159; CHECK-NEXT: str q0, [x0]160; CHECK-NEXT: ret161 %a = load <4 x float>, ptr %ap162 %b = load <4 x float>, ptr %bp163 %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b)164 store <4 x float> %r, ptr %ap165 ret void166}167 168define void @test_copysign_v8f32_v8f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {169; CHECK-LABEL: test_copysign_v8f32_v8f32:170; CHECK: // %bb.0:171; CHECK-NEXT: ptrue p0.s, vl8172; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]173; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]174; CHECK-NEXT: and z1.s, z1.s, #0x80000000175; CHECK-NEXT: and z0.s, z0.s, #0x7fffffff176; CHECK-NEXT: orr z0.d, z0.d, z1.d177; CHECK-NEXT: st1w { z0.s }, p0, [x0]178; CHECK-NEXT: ret179 %a = load <8 x float>, ptr %ap180 %b = load <8 x float>, ptr %bp181 %r = call <8 x float> @llvm.copysign.v8f32(<8 x float> %a, <8 x float> %b)182 store <8 x float> %r, ptr %ap183 ret void184}185 186define void @test_copysign_v16f32_v16f32(ptr %ap, ptr %bp) #0 {187; VBITS_GE_256-LABEL: test_copysign_v16f32_v16f32:188; VBITS_GE_256: // %bb.0:189; VBITS_GE_256-NEXT: ptrue p0.s, vl8190; VBITS_GE_256-NEXT: mov x8, #8 // =0x8191; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]192; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]193; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]194; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]195; VBITS_GE_256-NEXT: and z1.s, z1.s, #0x80000000196; VBITS_GE_256-NEXT: and z0.s, z0.s, #0x7fffffff197; VBITS_GE_256-NEXT: and z2.s, z2.s, #0x7fffffff198; VBITS_GE_256-NEXT: and z3.s, z3.s, #0x80000000199; VBITS_GE_256-NEXT: orr z0.d, z0.d, z1.d200; VBITS_GE_256-NEXT: orr z1.d, z2.d, z3.d201; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]202; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]203; VBITS_GE_256-NEXT: ret204;205; VBITS_GE_512-LABEL: test_copysign_v16f32_v16f32:206; VBITS_GE_512: // %bb.0:207; VBITS_GE_512-NEXT: ptrue p0.s, vl16208; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]209; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]210; VBITS_GE_512-NEXT: and z1.s, z1.s, #0x80000000211; VBITS_GE_512-NEXT: and z0.s, z0.s, #0x7fffffff212; VBITS_GE_512-NEXT: orr z0.d, z0.d, z1.d213; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]214; VBITS_GE_512-NEXT: ret215 %a = load <16 x float>, ptr %ap216 %b = load <16 x float>, ptr %bp217 %r = call <16 x float> @llvm.copysign.v16f32(<16 x float> %a, <16 x float> %b)218 store <16 x float> %r, ptr %ap219 ret void220}221 222define void @test_copysign_v32f32_v32f32(ptr %ap, ptr %bp) vscale_range(8,0) #0 {223; CHECK-LABEL: test_copysign_v32f32_v32f32:224; CHECK: // %bb.0:225; CHECK-NEXT: ptrue p0.s, vl32226; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]227; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]228; CHECK-NEXT: and z1.s, z1.s, #0x80000000229; CHECK-NEXT: and z0.s, z0.s, #0x7fffffff230; CHECK-NEXT: orr z0.d, z0.d, z1.d231; CHECK-NEXT: st1w { z0.s }, p0, [x0]232; CHECK-NEXT: ret233 %a = load <32 x float>, ptr %ap234 %b = load <32 x float>, ptr %bp235 %r = call <32 x float> @llvm.copysign.v32f32(<32 x float> %a, <32 x float> %b)236 store <32 x float> %r, ptr %ap237 ret void238}239 240define void @test_copysign_v64f32_v64f32(ptr %ap, ptr %bp) vscale_range(16,0) #0 {241; CHECK-LABEL: test_copysign_v64f32_v64f32:242; CHECK: // %bb.0:243; CHECK-NEXT: ptrue p0.s, vl64244; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]245; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]246; CHECK-NEXT: and z1.s, z1.s, #0x80000000247; CHECK-NEXT: and z0.s, z0.s, #0x7fffffff248; CHECK-NEXT: orr z0.d, z0.d, z1.d249; CHECK-NEXT: st1w { z0.s }, p0, [x0]250; CHECK-NEXT: ret251 %a = load <64 x float>, ptr %ap252 %b = load <64 x float>, ptr %bp253 %r = call <64 x float> @llvm.copysign.v64f32(<64 x float> %a, <64 x float> %b)254 store <64 x float> %r, ptr %ap255 ret void256}257 258;============ f64259 260define void @test_copysign_v2f64_v2f64(ptr %ap, ptr %bp) vscale_range(2,0) #0 {261; CHECK-LABEL: test_copysign_v2f64_v2f64:262; CHECK: // %bb.0:263; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff264; CHECK-NEXT: ldr q1, [x0]265; CHECK-NEXT: ldr q2, [x1]266; CHECK-NEXT: fneg v0.2d, v0.2d267; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b268; CHECK-NEXT: str q0, [x0]269; CHECK-NEXT: ret270 %a = load <2 x double>, ptr %ap271 %b = load <2 x double>, ptr %bp272 %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b)273 store <2 x double> %r, ptr %ap274 ret void275}276 277define void @test_copysign_v4f64_v4f64(ptr %ap, ptr %bp) vscale_range(2,0) #0 {278; CHECK-LABEL: test_copysign_v4f64_v4f64:279; CHECK: // %bb.0:280; CHECK-NEXT: ptrue p0.d, vl4281; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]282; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]283; CHECK-NEXT: and z1.d, z1.d, #0x8000000000000000284; CHECK-NEXT: and z0.d, z0.d, #0x7fffffffffffffff285; CHECK-NEXT: orr z0.d, z0.d, z1.d286; CHECK-NEXT: st1d { z0.d }, p0, [x0]287; CHECK-NEXT: ret288 %a = load <4 x double>, ptr %ap289 %b = load <4 x double>, ptr %bp290 %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b)291 store <4 x double> %r, ptr %ap292 ret void293}294 295define void @test_copysign_v8f64_v8f64(ptr %ap, ptr %bp) #0 {296; VBITS_GE_256-LABEL: test_copysign_v8f64_v8f64:297; VBITS_GE_256: // %bb.0:298; VBITS_GE_256-NEXT: ptrue p0.d, vl4299; VBITS_GE_256-NEXT: mov x8, #4 // =0x4300; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]301; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]302; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]303; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]304; VBITS_GE_256-NEXT: and z1.d, z1.d, #0x8000000000000000305; VBITS_GE_256-NEXT: and z0.d, z0.d, #0x7fffffffffffffff306; VBITS_GE_256-NEXT: and z2.d, z2.d, #0x7fffffffffffffff307; VBITS_GE_256-NEXT: and z3.d, z3.d, #0x8000000000000000308; VBITS_GE_256-NEXT: orr z0.d, z0.d, z1.d309; VBITS_GE_256-NEXT: orr z1.d, z2.d, z3.d310; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]311; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]312; VBITS_GE_256-NEXT: ret313;314; VBITS_GE_512-LABEL: test_copysign_v8f64_v8f64:315; VBITS_GE_512: // %bb.0:316; VBITS_GE_512-NEXT: ptrue p0.d, vl8317; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]318; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]319; VBITS_GE_512-NEXT: and z1.d, z1.d, #0x8000000000000000320; VBITS_GE_512-NEXT: and z0.d, z0.d, #0x7fffffffffffffff321; VBITS_GE_512-NEXT: orr z0.d, z0.d, z1.d322; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]323; VBITS_GE_512-NEXT: ret324 %a = load <8 x double>, ptr %ap325 %b = load <8 x double>, ptr %bp326 %r = call <8 x double> @llvm.copysign.v8f64(<8 x double> %a, <8 x double> %b)327 store <8 x double> %r, ptr %ap328 ret void329}330 331define void @test_copysign_v16f64_v16f64(ptr %ap, ptr %bp) vscale_range(8,0) #0 {332; CHECK-LABEL: test_copysign_v16f64_v16f64:333; CHECK: // %bb.0:334; CHECK-NEXT: ptrue p0.d, vl16335; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]336; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]337; CHECK-NEXT: and z1.d, z1.d, #0x8000000000000000338; CHECK-NEXT: and z0.d, z0.d, #0x7fffffffffffffff339; CHECK-NEXT: orr z0.d, z0.d, z1.d340; CHECK-NEXT: st1d { z0.d }, p0, [x0]341; CHECK-NEXT: ret342 %a = load <16 x double>, ptr %ap343 %b = load <16 x double>, ptr %bp344 %r = call <16 x double> @llvm.copysign.v16f64(<16 x double> %a, <16 x double> %b)345 store <16 x double> %r, ptr %ap346 ret void347}348 349define void @test_copysign_v32f64_v32f64(ptr %ap, ptr %bp) vscale_range(16,0) #0 {350; CHECK-LABEL: test_copysign_v32f64_v32f64:351; CHECK: // %bb.0:352; CHECK-NEXT: ptrue p0.d, vl32353; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]354; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]355; CHECK-NEXT: and z1.d, z1.d, #0x8000000000000000356; CHECK-NEXT: and z0.d, z0.d, #0x7fffffffffffffff357; CHECK-NEXT: orr z0.d, z0.d, z1.d358; CHECK-NEXT: st1d { z0.d }, p0, [x0]359; CHECK-NEXT: ret360 %a = load <32 x double>, ptr %ap361 %b = load <32 x double>, ptr %bp362 %r = call <32 x double> @llvm.copysign.v32f64(<32 x double> %a, <32 x double> %b)363 store <32 x double> %r, ptr %ap364 ret void365}366 367;============ v2f32368 369define void @test_copysign_v2f32_v2f64(ptr %ap, ptr %bp) vscale_range(2,0) #0 {370; CHECK-LABEL: test_copysign_v2f32_v2f64:371; CHECK: // %bb.0:372; CHECK-NEXT: ldr q0, [x1]373; CHECK-NEXT: mvni v1.2s, #128, lsl #24374; CHECK-NEXT: ldr d2, [x0]375; CHECK-NEXT: fcvtn v0.2s, v0.2d376; CHECK-NEXT: bit v0.8b, v2.8b, v1.8b377; CHECK-NEXT: str d0, [x0]378; CHECK-NEXT: ret379 %a = load <2 x float>, ptr %ap380 %b = load <2 x double>, ptr %bp381 %tmp0 = fptrunc <2 x double> %b to <2 x float>382 %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %tmp0)383 store <2 x float> %r, ptr %ap384 ret void385}386 387;============ v4f32388 389; SplitVecOp #1390define void @test_copysign_v4f32_v4f64(ptr %ap, ptr %bp) vscale_range(2,0) #0 {391; CHECK-LABEL: test_copysign_v4f32_v4f64:392; CHECK: // %bb.0:393; CHECK-NEXT: ptrue p0.d, vl4394; CHECK-NEXT: mvni v1.4s, #128, lsl #24395; CHECK-NEXT: ldr q2, [x0]396; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]397; CHECK-NEXT: ptrue p0.d398; CHECK-NEXT: fcvt z0.s, p0/m, z0.d399; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s400; CHECK-NEXT: bit v0.16b, v2.16b, v1.16b401; CHECK-NEXT: str q0, [x0]402; CHECK-NEXT: ret403 %a = load <4 x float>, ptr %ap404 %b = load <4 x double>, ptr %bp405 %tmp0 = fptrunc <4 x double> %b to <4 x float>406 %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %tmp0)407 store <4 x float> %r, ptr %ap408 ret void409}410 411;============ v2f64412 413define void @test_copysign_v2f64_v2f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {414; CHECK-LABEL: test_copysign_v2f64_v2f32:415; CHECK: // %bb.0:416; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff417; CHECK-NEXT: ldr d1, [x1]418; CHECK-NEXT: ldr q2, [x0]419; CHECK-NEXT: fcvtl v1.2d, v1.2s420; CHECK-NEXT: fneg v0.2d, v0.2d421; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b422; CHECK-NEXT: str q0, [x0]423; CHECK-NEXT: ret424 %a = load <2 x double>, ptr %ap425 %b = load < 2 x float>, ptr %bp426 %tmp0 = fpext <2 x float> %b to <2 x double>427 %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %tmp0)428 store <2 x double> %r, ptr %ap429 ret void430}431 432;============ v4f64433 434; SplitVecRes mismatched435define void @test_copysign_v4f64_v4f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {436; CHECK-LABEL: test_copysign_v4f64_v4f32:437; CHECK: // %bb.0:438; CHECK-NEXT: ptrue p0.d, vl4439; CHECK-NEXT: ld1w { z0.d }, p0/z, [x1]440; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]441; CHECK-NEXT: fcvt z0.d, p0/m, z0.s442; CHECK-NEXT: and z1.d, z1.d, #0x7fffffffffffffff443; CHECK-NEXT: and z0.d, z0.d, #0x8000000000000000444; CHECK-NEXT: orr z0.d, z1.d, z0.d445; CHECK-NEXT: st1d { z0.d }, p0, [x0]446; CHECK-NEXT: ret447 %a = load <4 x double>, ptr %ap448 %b = load <4 x float>, ptr %bp449 %tmp0 = fpext <4 x float> %b to <4 x double>450 %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %tmp0)451 store <4 x double> %r, ptr %ap452 ret void453}454 455;============ v4f16456 457define void @test_copysign_v4f16_v4f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {458; CHECK-LABEL: test_copysign_v4f16_v4f32:459; CHECK: // %bb.0:460; CHECK-NEXT: ldr q0, [x1]461; CHECK-NEXT: mvni v1.4h, #128, lsl #8462; CHECK-NEXT: ldr d2, [x0]463; CHECK-NEXT: fcvtn v0.4h, v0.4s464; CHECK-NEXT: bit v0.8b, v2.8b, v1.8b465; CHECK-NEXT: str d0, [x0]466; CHECK-NEXT: ret467 %a = load <4 x half>, ptr %ap468 %b = load <4 x float>, ptr %bp469 %tmp0 = fptrunc <4 x float> %b to <4 x half>470 %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0)471 store <4 x half> %r, ptr %ap472 ret void473}474 475define void @test_copysign_v4f16_v4f64(ptr %ap, ptr %bp) vscale_range(2,0) #0 {476; CHECK-LABEL: test_copysign_v4f16_v4f64:477; CHECK: // %bb.0:478; CHECK-NEXT: ptrue p0.d, vl4479; CHECK-NEXT: mvni v1.4h, #128, lsl #8480; CHECK-NEXT: ldr d2, [x0]481; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]482; CHECK-NEXT: ptrue p0.d483; CHECK-NEXT: fcvt z0.h, p0/m, z0.d484; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s485; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h486; CHECK-NEXT: bit v0.8b, v2.8b, v1.8b487; CHECK-NEXT: str d0, [x0]488; CHECK-NEXT: ret489 %a = load <4 x half>, ptr %ap490 %b = load <4 x double>, ptr %bp491 %tmp0 = fptrunc <4 x double> %b to <4 x half>492 %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0)493 store <4 x half> %r, ptr %ap494 ret void495}496 497declare <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b) #0498 499;============ v8f16500 501 502define void @test_copysign_v8f16_v8f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {503; CHECK-LABEL: test_copysign_v8f16_v8f32:504; CHECK: // %bb.0:505; CHECK-NEXT: ptrue p0.s, vl8506; CHECK-NEXT: mvni v1.8h, #128, lsl #8507; CHECK-NEXT: ldr q2, [x0]508; CHECK-NEXT: ld1w { z0.s }, p0/z, [x1]509; CHECK-NEXT: ptrue p0.s510; CHECK-NEXT: fcvt z0.h, p0/m, z0.s511; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h512; CHECK-NEXT: bit v0.16b, v2.16b, v1.16b513; CHECK-NEXT: str q0, [x0]514; CHECK-NEXT: ret515 %a = load <8 x half>, ptr %ap516 %b = load <8 x float>, ptr %bp517 %tmp0 = fptrunc <8 x float> %b to <8 x half>518 %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %tmp0)519 store <8 x half> %r, ptr %ap520 ret void521}522 523declare <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b) #0524declare <16 x half> @llvm.copysign.v16f16(<16 x half> %a, <16 x half> %b) #0525declare <32 x half> @llvm.copysign.v32f16(<32 x half> %a, <32 x half> %b) #0526declare <64 x half> @llvm.copysign.v64f16(<64 x half> %a, <64 x half> %b) #0527declare <128 x half> @llvm.copysign.v128f16(<128 x half> %a, <128 x half> %b) #0528 529declare <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b) #0530declare <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b) #0531declare <8 x float> @llvm.copysign.v8f32(<8 x float> %a, <8 x float> %b) #0532declare <16 x float> @llvm.copysign.v16f32(<16 x float> %a, <16 x float> %b) #0533declare <32 x float> @llvm.copysign.v32f32(<32 x float> %a, <32 x float> %b) #0534declare <64 x float> @llvm.copysign.v64f32(<64 x float> %a, <64 x float> %b) #0535 536declare <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) #0537declare <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b) #0538declare <8 x double> @llvm.copysign.v8f64(<8 x double> %a, <8 x double> %b) #0539declare <16 x double> @llvm.copysign.v16f64(<16 x double> %a, <16 x double> %b) #0540declare <32 x double> @llvm.copysign.v32f64(<32 x double> %a, <32 x double> %b) #0541 542attributes #0 = { "target-features"="+sve" }543