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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; FCMP OEQ10;11 12; Don't use SVE for 64-bit vectors.13define <4 x i16> @fcmp_oeq_v4f16(<4 x half> %op1, <4 x half> %op2) vscale_range(2,0) #0 {14; CHECK-LABEL: fcmp_oeq_v4f16:15; CHECK: // %bb.0:16; CHECK-NEXT: fcmeq v0.4h, v0.4h, v1.4h17; CHECK-NEXT: ret18 %cmp = fcmp oeq <4 x half> %op1, %op219 %sext = sext <4 x i1> %cmp to <4 x i16>20 ret <4 x i16> %sext21}22 23; Don't use SVE for 128-bit vectors.24define <8 x i16> @fcmp_oeq_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0) #0 {25; CHECK-LABEL: fcmp_oeq_v8f16:26; CHECK: // %bb.0:27; CHECK-NEXT: fcmeq v0.8h, v0.8h, v1.8h28; CHECK-NEXT: ret29 %cmp = fcmp oeq <8 x half> %op1, %op230 %sext = sext <8 x i1> %cmp to <8 x i16>31 ret <8 x i16> %sext32}33 34define void @fcmp_oeq_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {35; CHECK-LABEL: fcmp_oeq_v16f16:36; CHECK: // %bb.0:37; CHECK-NEXT: ptrue p0.h, vl1638; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]39; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]40; CHECK-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h41; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff42; CHECK-NEXT: st1h { z0.h }, p0, [x2]43; CHECK-NEXT: ret44 %op1 = load <16 x half>, ptr %a45 %op2 = load <16 x half>, ptr %b46 %cmp = fcmp oeq <16 x half> %op1, %op247 %sext = sext <16 x i1> %cmp to <16 x i16>48 store <16 x i16> %sext, ptr %c49 ret void50}51 52define void @fcmp_oeq_v32f16(ptr %a, ptr %b, ptr %c) #0 {53; VBITS_GE_256-LABEL: fcmp_oeq_v32f16:54; VBITS_GE_256: // %bb.0:55; VBITS_GE_256-NEXT: ptrue p0.h, vl1656; VBITS_GE_256-NEXT: mov x8, #16 // =0x1057; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]58; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]59; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]60; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]61; VBITS_GE_256-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h62; VBITS_GE_256-NEXT: fcmeq p2.h, p0/z, z2.h, z3.h63; VBITS_GE_256-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff64; VBITS_GE_256-NEXT: mov z1.h, p2/z, #-1 // =0xffffffffffffffff65; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x2, x8, lsl #1]66; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x2]67; VBITS_GE_256-NEXT: ret68;69; VBITS_GE_512-LABEL: fcmp_oeq_v32f16:70; VBITS_GE_512: // %bb.0:71; VBITS_GE_512-NEXT: ptrue p0.h, vl3272; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]73; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]74; VBITS_GE_512-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h75; VBITS_GE_512-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff76; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x2]77; VBITS_GE_512-NEXT: ret78 %op1 = load <32 x half>, ptr %a79 %op2 = load <32 x half>, ptr %b80 %cmp = fcmp oeq <32 x half> %op1, %op281 %sext = sext <32 x i1> %cmp to <32 x i16>82 store <32 x i16> %sext, ptr %c83 ret void84}85 86define void @fcmp_oeq_v64f16(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 {87; CHECK-LABEL: fcmp_oeq_v64f16:88; CHECK: // %bb.0:89; CHECK-NEXT: ptrue p0.h, vl6490; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]91; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]92; CHECK-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h93; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff94; CHECK-NEXT: st1h { z0.h }, p0, [x2]95; CHECK-NEXT: ret96 %op1 = load <64 x half>, ptr %a97 %op2 = load <64 x half>, ptr %b98 %cmp = fcmp oeq <64 x half> %op1, %op299 %sext = sext <64 x i1> %cmp to <64 x i16>100 store <64 x i16> %sext, ptr %c101 ret void102}103 104define void @fcmp_oeq_v128f16(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 {105; CHECK-LABEL: fcmp_oeq_v128f16:106; CHECK: // %bb.0:107; CHECK-NEXT: ptrue p0.h, vl128108; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]109; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]110; CHECK-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h111; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff112; CHECK-NEXT: st1h { z0.h }, p0, [x2]113; CHECK-NEXT: ret114 %op1 = load <128 x half>, ptr %a115 %op2 = load <128 x half>, ptr %b116 %cmp = fcmp oeq <128 x half> %op1, %op2117 %sext = sext <128 x i1> %cmp to <128 x i16>118 store <128 x i16> %sext, ptr %c119 ret void120}121 122; Don't use SVE for 64-bit vectors.123define <2 x i32> @fcmp_oeq_v2f32(<2 x float> %op1, <2 x float> %op2) vscale_range(2,0) #0 {124; CHECK-LABEL: fcmp_oeq_v2f32:125; CHECK: // %bb.0:126; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s127; CHECK-NEXT: ret128 %cmp = fcmp oeq <2 x float> %op1, %op2129 %sext = sext <2 x i1> %cmp to <2 x i32>130 ret <2 x i32> %sext131}132 133; Don't use SVE for 128-bit vectors.134define <4 x i32> @fcmp_oeq_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range(2,0) #0 {135; CHECK-LABEL: fcmp_oeq_v4f32:136; CHECK: // %bb.0:137; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s138; CHECK-NEXT: ret139 %cmp = fcmp oeq <4 x float> %op1, %op2140 %sext = sext <4 x i1> %cmp to <4 x i32>141 ret <4 x i32> %sext142}143 144define void @fcmp_oeq_v8f32(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {145; CHECK-LABEL: fcmp_oeq_v8f32:146; CHECK: // %bb.0:147; CHECK-NEXT: ptrue p0.s, vl8148; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]149; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]150; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s151; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff152; CHECK-NEXT: st1w { z0.s }, p0, [x2]153; CHECK-NEXT: ret154 %op1 = load <8 x float>, ptr %a155 %op2 = load <8 x float>, ptr %b156 %cmp = fcmp oeq <8 x float> %op1, %op2157 %sext = sext <8 x i1> %cmp to <8 x i32>158 store <8 x i32> %sext, ptr %c159 ret void160}161 162define void @fcmp_oeq_v16f32(ptr %a, ptr %b, ptr %c) #0 {163; VBITS_GE_256-LABEL: fcmp_oeq_v16f32:164; VBITS_GE_256: // %bb.0:165; VBITS_GE_256-NEXT: ptrue p0.s, vl8166; VBITS_GE_256-NEXT: mov x8, #8 // =0x8167; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]168; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]169; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]170; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]171; VBITS_GE_256-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s172; VBITS_GE_256-NEXT: fcmeq p2.s, p0/z, z2.s, z3.s173; VBITS_GE_256-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff174; VBITS_GE_256-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff175; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x2, x8, lsl #2]176; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x2]177; VBITS_GE_256-NEXT: ret178;179; VBITS_GE_512-LABEL: fcmp_oeq_v16f32:180; VBITS_GE_512: // %bb.0:181; VBITS_GE_512-NEXT: ptrue p0.s, vl16182; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]183; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]184; VBITS_GE_512-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s185; VBITS_GE_512-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff186; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x2]187; VBITS_GE_512-NEXT: ret188 %op1 = load <16 x float>, ptr %a189 %op2 = load <16 x float>, ptr %b190 %cmp = fcmp oeq <16 x float> %op1, %op2191 %sext = sext <16 x i1> %cmp to <16 x i32>192 store <16 x i32> %sext, ptr %c193 ret void194}195 196define void @fcmp_oeq_v32f32(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 {197; CHECK-LABEL: fcmp_oeq_v32f32:198; CHECK: // %bb.0:199; CHECK-NEXT: ptrue p0.s, vl32200; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]201; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]202; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s203; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff204; CHECK-NEXT: st1w { z0.s }, p0, [x2]205; CHECK-NEXT: ret206 %op1 = load <32 x float>, ptr %a207 %op2 = load <32 x float>, ptr %b208 %cmp = fcmp oeq <32 x float> %op1, %op2209 %sext = sext <32 x i1> %cmp to <32 x i32>210 store <32 x i32> %sext, ptr %c211 ret void212}213 214define void @fcmp_oeq_v64f32(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 {215; CHECK-LABEL: fcmp_oeq_v64f32:216; CHECK: // %bb.0:217; CHECK-NEXT: ptrue p0.s, vl64218; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]219; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]220; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s221; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff222; CHECK-NEXT: st1w { z0.s }, p0, [x2]223; CHECK-NEXT: ret224 %op1 = load <64 x float>, ptr %a225 %op2 = load <64 x float>, ptr %b226 %cmp = fcmp oeq <64 x float> %op1, %op2227 %sext = sext <64 x i1> %cmp to <64 x i32>228 store <64 x i32> %sext, ptr %c229 ret void230}231 232; Don't use SVE for 64-bit vectors.233define <1 x i64> @fcmp_oeq_v1f64(<1 x double> %op1, <1 x double> %op2) vscale_range(2,0) #0 {234; CHECK-LABEL: fcmp_oeq_v1f64:235; CHECK: // %bb.0:236; CHECK-NEXT: fcmeq d0, d0, d1237; CHECK-NEXT: ret238 %cmp = fcmp oeq <1 x double> %op1, %op2239 %sext = sext <1 x i1> %cmp to <1 x i64>240 ret <1 x i64> %sext241}242 243; Don't use SVE for 128-bit vectors.244define <2 x i64> @fcmp_oeq_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_range(2,0) #0 {245; CHECK-LABEL: fcmp_oeq_v2f64:246; CHECK: // %bb.0:247; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d248; CHECK-NEXT: ret249 %cmp = fcmp oeq <2 x double> %op1, %op2250 %sext = sext <2 x i1> %cmp to <2 x i64>251 ret <2 x i64> %sext252}253 254define void @fcmp_oeq_v4f64(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {255; CHECK-LABEL: fcmp_oeq_v4f64:256; CHECK: // %bb.0:257; CHECK-NEXT: ptrue p0.d, vl4258; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]259; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]260; CHECK-NEXT: fcmeq p1.d, p0/z, z0.d, z1.d261; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff262; CHECK-NEXT: st1d { z0.d }, p0, [x2]263; CHECK-NEXT: ret264 %op1 = load <4 x double>, ptr %a265 %op2 = load <4 x double>, ptr %b266 %cmp = fcmp oeq <4 x double> %op1, %op2267 %sext = sext <4 x i1> %cmp to <4 x i64>268 store <4 x i64> %sext, ptr %c269 ret void270}271 272define void @fcmp_oeq_v8f64(ptr %a, ptr %b, ptr %c) #0 {273; VBITS_GE_256-LABEL: fcmp_oeq_v8f64:274; VBITS_GE_256: // %bb.0:275; VBITS_GE_256-NEXT: ptrue p0.d, vl4276; VBITS_GE_256-NEXT: mov x8, #4 // =0x4277; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]278; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]279; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]280; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]281; VBITS_GE_256-NEXT: fcmeq p1.d, p0/z, z0.d, z1.d282; VBITS_GE_256-NEXT: fcmeq p2.d, p0/z, z2.d, z3.d283; VBITS_GE_256-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff284; VBITS_GE_256-NEXT: mov z1.d, p2/z, #-1 // =0xffffffffffffffff285; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x2, x8, lsl #3]286; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x2]287; VBITS_GE_256-NEXT: ret288;289; VBITS_GE_512-LABEL: fcmp_oeq_v8f64:290; VBITS_GE_512: // %bb.0:291; VBITS_GE_512-NEXT: ptrue p0.d, vl8292; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]293; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]294; VBITS_GE_512-NEXT: fcmeq p1.d, p0/z, z0.d, z1.d295; VBITS_GE_512-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff296; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x2]297; VBITS_GE_512-NEXT: ret298 %op1 = load <8 x double>, ptr %a299 %op2 = load <8 x double>, ptr %b300 %cmp = fcmp oeq <8 x double> %op1, %op2301 %sext = sext <8 x i1> %cmp to <8 x i64>302 store <8 x i64> %sext, ptr %c303 ret void304}305 306define void @fcmp_oeq_v16f64(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 {307; CHECK-LABEL: fcmp_oeq_v16f64:308; CHECK: // %bb.0:309; CHECK-NEXT: ptrue p0.d, vl16310; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]311; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]312; CHECK-NEXT: fcmeq p1.d, p0/z, z0.d, z1.d313; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff314; CHECK-NEXT: st1d { z0.d }, p0, [x2]315; CHECK-NEXT: ret316 %op1 = load <16 x double>, ptr %a317 %op2 = load <16 x double>, ptr %b318 %cmp = fcmp oeq <16 x double> %op1, %op2319 %sext = sext <16 x i1> %cmp to <16 x i64>320 store <16 x i64> %sext, ptr %c321 ret void322}323 324define void @fcmp_oeq_v32f64(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 {325; CHECK-LABEL: fcmp_oeq_v32f64:326; CHECK: // %bb.0:327; CHECK-NEXT: ptrue p0.d, vl32328; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]329; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]330; CHECK-NEXT: fcmeq p1.d, p0/z, z0.d, z1.d331; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff332; CHECK-NEXT: st1d { z0.d }, p0, [x2]333; CHECK-NEXT: ret334 %op1 = load <32 x double>, ptr %a335 %op2 = load <32 x double>, ptr %b336 %cmp = fcmp oeq <32 x double> %op1, %op2337 %sext = sext <32 x i1> %cmp to <32 x i64>338 store <32 x i64> %sext, ptr %c339 ret void340}341 342;343; FCMP UEQ344;345 346define void @fcmp_ueq_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {347; CHECK-LABEL: fcmp_ueq_v16f16:348; CHECK: // %bb.0:349; CHECK-NEXT: ptrue p0.h, vl16350; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]351; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]352; CHECK-NEXT: fcmuo p1.h, p0/z, z0.h, z1.h353; CHECK-NEXT: fcmeq p2.h, p0/z, z0.h, z1.h354; CHECK-NEXT: mov p1.b, p2/m, p2.b355; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff356; CHECK-NEXT: st1h { z0.h }, p0, [x2]357; CHECK-NEXT: ret358 %op1 = load <16 x half>, ptr %a359 %op2 = load <16 x half>, ptr %b360 %cmp = fcmp ueq <16 x half> %op1, %op2361 %sext = sext <16 x i1> %cmp to <16 x i16>362 store <16 x i16> %sext, ptr %c363 ret void364}365 366;367; FCMP ONE368;369 370define void @fcmp_one_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {371; CHECK-LABEL: fcmp_one_v16f16:372; CHECK: // %bb.0:373; CHECK-NEXT: ptrue p0.h, vl16374; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]375; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]376; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z0.h377; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z1.h378; CHECK-NEXT: mov p1.b, p2/m, p2.b379; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff380; CHECK-NEXT: st1h { z0.h }, p0, [x2]381; CHECK-NEXT: ret382 %op1 = load <16 x half>, ptr %a383 %op2 = load <16 x half>, ptr %b384 %cmp = fcmp one <16 x half> %op1, %op2385 %sext = sext <16 x i1> %cmp to <16 x i16>386 store <16 x i16> %sext, ptr %c387 ret void388}389 390;391; FCMP UNE392;393 394define void @fcmp_une_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {395; CHECK-LABEL: fcmp_une_v16f16:396; CHECK: // %bb.0:397; CHECK-NEXT: ptrue p0.h, vl16398; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]399; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]400; CHECK-NEXT: fcmne p1.h, p0/z, z0.h, z1.h401; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff402; CHECK-NEXT: st1h { z0.h }, p0, [x2]403; CHECK-NEXT: ret404 %op1 = load <16 x half>, ptr %a405 %op2 = load <16 x half>, ptr %b406 %cmp = fcmp une <16 x half> %op1, %op2407 %sext = sext <16 x i1> %cmp to <16 x i16>408 store <16 x i16> %sext, ptr %c409 ret void410}411 412;413; FCMP OGT414;415 416define void @fcmp_ogt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {417; CHECK-LABEL: fcmp_ogt_v16f16:418; CHECK: // %bb.0:419; CHECK-NEXT: ptrue p0.h, vl16420; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]421; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]422; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h423; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff424; CHECK-NEXT: st1h { z0.h }, p0, [x2]425; CHECK-NEXT: ret426 %op1 = load <16 x half>, ptr %a427 %op2 = load <16 x half>, ptr %b428 %cmp = fcmp ogt <16 x half> %op1, %op2429 %sext = sext <16 x i1> %cmp to <16 x i16>430 store <16 x i16> %sext, ptr %c431 ret void432}433 434;435; FCMP UGT436;437 438define void @fcmp_ugt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {439; CHECK-LABEL: fcmp_ugt_v16f16:440; CHECK: // %bb.0:441; CHECK-NEXT: ptrue p0.h, vl16442; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]443; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]444; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z0.h445; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff446; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff447; CHECK-NEXT: eor z0.d, z0.d, z1.d448; CHECK-NEXT: st1h { z0.h }, p0, [x2]449; CHECK-NEXT: ret450 %op1 = load <16 x half>, ptr %a451 %op2 = load <16 x half>, ptr %b452 %cmp = fcmp ugt <16 x half> %op1, %op2453 %sext = sext <16 x i1> %cmp to <16 x i16>454 store <16 x i16> %sext, ptr %c455 ret void456}457 458;459; FCMP OLT460;461 462define void @fcmp_olt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {463; CHECK-LABEL: fcmp_olt_v16f16:464; CHECK: // %bb.0:465; CHECK-NEXT: ptrue p0.h, vl16466; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]467; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]468; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z0.h469; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff470; CHECK-NEXT: st1h { z0.h }, p0, [x2]471; CHECK-NEXT: ret472 %op1 = load <16 x half>, ptr %a473 %op2 = load <16 x half>, ptr %b474 %cmp = fcmp olt <16 x half> %op1, %op2475 %sext = sext <16 x i1> %cmp to <16 x i16>476 store <16 x i16> %sext, ptr %c477 ret void478}479 480;481; FCMP ULT482;483 484define void @fcmp_ult_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {485; CHECK-LABEL: fcmp_ult_v16f16:486; CHECK: // %bb.0:487; CHECK-NEXT: ptrue p0.h, vl16488; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]489; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]490; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h491; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff492; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff493; CHECK-NEXT: eor z0.d, z0.d, z1.d494; CHECK-NEXT: st1h { z0.h }, p0, [x2]495; CHECK-NEXT: ret496 %op1 = load <16 x half>, ptr %a497 %op2 = load <16 x half>, ptr %b498 %cmp = fcmp ult <16 x half> %op1, %op2499 %sext = sext <16 x i1> %cmp to <16 x i16>500 store <16 x i16> %sext, ptr %c501 ret void502}503 504;505; FCMP OGE506;507 508define void @fcmp_oge_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {509; CHECK-LABEL: fcmp_oge_v16f16:510; CHECK: // %bb.0:511; CHECK-NEXT: ptrue p0.h, vl16512; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]513; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]514; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h515; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff516; CHECK-NEXT: st1h { z0.h }, p0, [x2]517; CHECK-NEXT: ret518 %op1 = load <16 x half>, ptr %a519 %op2 = load <16 x half>, ptr %b520 %cmp = fcmp oge <16 x half> %op1, %op2521 %sext = sext <16 x i1> %cmp to <16 x i16>522 store <16 x i16> %sext, ptr %c523 ret void524}525 526;527; FCMP UGE528;529 530define void @fcmp_uge_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {531; CHECK-LABEL: fcmp_uge_v16f16:532; CHECK: // %bb.0:533; CHECK-NEXT: ptrue p0.h, vl16534; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]535; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]536; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z0.h537; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff538; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff539; CHECK-NEXT: eor z0.d, z0.d, z1.d540; CHECK-NEXT: st1h { z0.h }, p0, [x2]541; CHECK-NEXT: ret542 %op1 = load <16 x half>, ptr %a543 %op2 = load <16 x half>, ptr %b544 %cmp = fcmp uge <16 x half> %op1, %op2545 %sext = sext <16 x i1> %cmp to <16 x i16>546 store <16 x i16> %sext, ptr %c547 ret void548}549 550;551; FCMP OLE552;553 554define void @fcmp_ole_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {555; CHECK-LABEL: fcmp_ole_v16f16:556; CHECK: // %bb.0:557; CHECK-NEXT: ptrue p0.h, vl16558; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]559; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]560; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z0.h561; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff562; CHECK-NEXT: st1h { z0.h }, p0, [x2]563; CHECK-NEXT: ret564 %op1 = load <16 x half>, ptr %a565 %op2 = load <16 x half>, ptr %b566 %cmp = fcmp ole <16 x half> %op1, %op2567 %sext = sext <16 x i1> %cmp to <16 x i16>568 store <16 x i16> %sext, ptr %c569 ret void570}571 572;573; FCMP ULE574;575 576define void @fcmp_ule_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {577; CHECK-LABEL: fcmp_ule_v16f16:578; CHECK: // %bb.0:579; CHECK-NEXT: ptrue p0.h, vl16580; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]581; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]582; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h583; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff584; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff585; CHECK-NEXT: eor z0.d, z0.d, z1.d586; CHECK-NEXT: st1h { z0.h }, p0, [x2]587; CHECK-NEXT: ret588 %op1 = load <16 x half>, ptr %a589 %op2 = load <16 x half>, ptr %b590 %cmp = fcmp ule <16 x half> %op1, %op2591 %sext = sext <16 x i1> %cmp to <16 x i16>592 store <16 x i16> %sext, ptr %c593 ret void594}595 596;597; FCMP UNO598;599 600define void @fcmp_uno_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {601; CHECK-LABEL: fcmp_uno_v16f16:602; CHECK: // %bb.0:603; CHECK-NEXT: ptrue p0.h, vl16604; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]605; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]606; CHECK-NEXT: fcmuo p1.h, p0/z, z0.h, z1.h607; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff608; CHECK-NEXT: st1h { z0.h }, p0, [x2]609; CHECK-NEXT: ret610 %op1 = load <16 x half>, ptr %a611 %op2 = load <16 x half>, ptr %b612 %cmp = fcmp uno <16 x half> %op1, %op2613 %sext = sext <16 x i1> %cmp to <16 x i16>614 store <16 x i16> %sext, ptr %c615 ret void616}617 618;619; FCMP ORD620;621 622define void @fcmp_ord_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {623; CHECK-LABEL: fcmp_ord_v16f16:624; CHECK: // %bb.0:625; CHECK-NEXT: ptrue p0.h, vl16626; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]627; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]628; CHECK-NEXT: fcmuo p1.h, p0/z, z0.h, z1.h629; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff630; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff631; CHECK-NEXT: eor z0.d, z0.d, z1.d632; CHECK-NEXT: st1h { z0.h }, p0, [x2]633; CHECK-NEXT: ret634 %op1 = load <16 x half>, ptr %a635 %op2 = load <16 x half>, ptr %b636 %cmp = fcmp ord <16 x half> %op1, %op2637 %sext = sext <16 x i1> %cmp to <16 x i16>638 store <16 x i16> %sext, ptr %c639 ret void640}641 642;643; FCMP EQ644;645 646define void @fcmp_eq_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {647; CHECK-LABEL: fcmp_eq_v16f16:648; CHECK: // %bb.0:649; CHECK-NEXT: ptrue p0.h, vl16650; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]651; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]652; CHECK-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h653; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff654; CHECK-NEXT: st1h { z0.h }, p0, [x2]655; CHECK-NEXT: ret656 %op1 = load <16 x half>, ptr %a657 %op2 = load <16 x half>, ptr %b658 %cmp = fcmp fast oeq <16 x half> %op1, %op2659 %sext = sext <16 x i1> %cmp to <16 x i16>660 store <16 x i16> %sext, ptr %c661 ret void662}663 664;665; FCMP NE666;667 668define void @fcmp_ne_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {669; CHECK-LABEL: fcmp_ne_v16f16:670; CHECK: // %bb.0:671; CHECK-NEXT: ptrue p0.h, vl16672; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]673; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]674; CHECK-NEXT: fcmne p1.h, p0/z, z0.h, z1.h675; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff676; CHECK-NEXT: st1h { z0.h }, p0, [x2]677; CHECK-NEXT: ret678 %op1 = load <16 x half>, ptr %a679 %op2 = load <16 x half>, ptr %b680 %cmp = fcmp fast one <16 x half> %op1, %op2681 %sext = sext <16 x i1> %cmp to <16 x i16>682 store <16 x i16> %sext, ptr %c683 ret void684}685 686;687; FCMP GT688;689 690define void @fcmp_gt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {691; CHECK-LABEL: fcmp_gt_v16f16:692; CHECK: // %bb.0:693; CHECK-NEXT: ptrue p0.h, vl16694; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]695; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]696; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h697; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff698; CHECK-NEXT: st1h { z0.h }, p0, [x2]699; CHECK-NEXT: ret700 %op1 = load <16 x half>, ptr %a701 %op2 = load <16 x half>, ptr %b702 %cmp = fcmp fast ogt <16 x half> %op1, %op2703 %sext = sext <16 x i1> %cmp to <16 x i16>704 store <16 x i16> %sext, ptr %c705 ret void706}707 708;709; FCMP LT710;711 712define void @fcmp_lt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {713; CHECK-LABEL: fcmp_lt_v16f16:714; CHECK: // %bb.0:715; CHECK-NEXT: ptrue p0.h, vl16716; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]717; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]718; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z0.h719; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff720; CHECK-NEXT: st1h { z0.h }, p0, [x2]721; CHECK-NEXT: ret722 %op1 = load <16 x half>, ptr %a723 %op2 = load <16 x half>, ptr %b724 %cmp = fcmp fast olt <16 x half> %op1, %op2725 %sext = sext <16 x i1> %cmp to <16 x i16>726 store <16 x i16> %sext, ptr %c727 ret void728}729 730;731; FCMP GE732;733 734define void @fcmp_ge_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {735; CHECK-LABEL: fcmp_ge_v16f16:736; CHECK: // %bb.0:737; CHECK-NEXT: ptrue p0.h, vl16738; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]739; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]740; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h741; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff742; CHECK-NEXT: st1h { z0.h }, p0, [x2]743; CHECK-NEXT: ret744 %op1 = load <16 x half>, ptr %a745 %op2 = load <16 x half>, ptr %b746 %cmp = fcmp fast oge <16 x half> %op1, %op2747 %sext = sext <16 x i1> %cmp to <16 x i16>748 store <16 x i16> %sext, ptr %c749 ret void750}751 752;753; FCMP LE754;755 756define void @fcmp_le_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {757; CHECK-LABEL: fcmp_le_v16f16:758; CHECK: // %bb.0:759; CHECK-NEXT: ptrue p0.h, vl16760; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]761; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]762; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z0.h763; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff764; CHECK-NEXT: st1h { z0.h }, p0, [x2]765; CHECK-NEXT: ret766 %op1 = load <16 x half>, ptr %a767 %op2 = load <16 x half>, ptr %b768 %cmp = fcmp fast ole <16 x half> %op1, %op2769 %sext = sext <16 x i1> %cmp to <16 x i16>770 store <16 x i16> %sext, ptr %c771 ret void772}773 774attributes #0 = { "target-features"="+sve" }775