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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_EQ_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; FMAXNM10;11 12; Don't use SVE for 64-bit vectors.13define <4 x half> @fmaxnm_v4f16(<4 x half> %op1, <4 x half> %op2) vscale_range(2,0) #0 {14; CHECK-LABEL: fmaxnm_v4f16:15; CHECK: // %bb.0:16; CHECK-NEXT: fmaxnm v0.4h, v0.4h, v1.4h17; CHECK-NEXT: ret18 %res = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %op1, <4 x half> %op2)19 ret <4 x half> %res20}21 22; Don't use SVE for 128-bit vectors.23define <8 x half> @fmaxnm_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0) #0 {24; CHECK-LABEL: fmaxnm_v8f16:25; CHECK: // %bb.0:26; CHECK-NEXT: fmaxnm v0.8h, v0.8h, v1.8h27; CHECK-NEXT: ret28 %res = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %op1, <8 x half> %op2)29 ret <8 x half> %res30}31 32define void @fmaxnm_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {33; CHECK-LABEL: fmaxnm_v16f16:34; CHECK: // %bb.0:35; CHECK-NEXT: ptrue p0.h, vl1636; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]37; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]38; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h39; CHECK-NEXT: st1h { z0.h }, p0, [x0]40; CHECK-NEXT: ret41 %op1 = load <16 x half>, ptr %a42 %op2 = load <16 x half>, ptr %b43 %res = call <16 x half> @llvm.maxnum.v16f16(<16 x half> %op1, <16 x half> %op2)44 store <16 x half> %res, ptr %a45 ret void46}47 48define void @fmaxnm_v32f16(ptr %a, ptr %b) #0 {49; VBITS_EQ_256-LABEL: fmaxnm_v32f16:50; VBITS_EQ_256: // %bb.0:51; VBITS_EQ_256-NEXT: ptrue p0.h, vl1652; VBITS_EQ_256-NEXT: mov x8, #16 // =0x1053; VBITS_EQ_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]54; VBITS_EQ_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]55; VBITS_EQ_256-NEXT: ld1h { z2.h }, p0/z, [x0]56; VBITS_EQ_256-NEXT: ld1h { z3.h }, p0/z, [x1]57; VBITS_EQ_256-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h58; VBITS_EQ_256-NEXT: fmaxnm z2.h, p0/m, z2.h, z3.h59; VBITS_EQ_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]60; VBITS_EQ_256-NEXT: st1h { z2.h }, p0, [x0]61; VBITS_EQ_256-NEXT: ret62;63; VBITS_GE_512-LABEL: fmaxnm_v32f16:64; VBITS_GE_512: // %bb.0:65; VBITS_GE_512-NEXT: ptrue p0.h, vl3266; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]67; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]68; VBITS_GE_512-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h69; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]70; VBITS_GE_512-NEXT: ret71 %op1 = load <32 x half>, ptr %a72 %op2 = load <32 x half>, ptr %b73 %res = call <32 x half> @llvm.maxnum.v32f16(<32 x half> %op1, <32 x half> %op2)74 store <32 x half> %res, ptr %a75 ret void76}77 78define void @fmaxnm_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 {79; CHECK-LABEL: fmaxnm_v64f16:80; CHECK: // %bb.0:81; CHECK-NEXT: ptrue p0.h, vl6482; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]83; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]84; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h85; CHECK-NEXT: st1h { z0.h }, p0, [x0]86; CHECK-NEXT: ret87 %op1 = load <64 x half>, ptr %a88 %op2 = load <64 x half>, ptr %b89 %res = call <64 x half> @llvm.maxnum.v64f16(<64 x half> %op1, <64 x half> %op2)90 store <64 x half> %res, ptr %a91 ret void92}93 94define void @fmaxnm_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 {95; CHECK-LABEL: fmaxnm_v128f16:96; CHECK: // %bb.0:97; CHECK-NEXT: ptrue p0.h, vl12898; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]99; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]100; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h101; CHECK-NEXT: st1h { z0.h }, p0, [x0]102; CHECK-NEXT: ret103 %op1 = load <128 x half>, ptr %a104 %op2 = load <128 x half>, ptr %b105 %res = call <128 x half> @llvm.maxnum.v128f16(<128 x half> %op1, <128 x half> %op2)106 store <128 x half> %res, ptr %a107 ret void108}109 110; Don't use SVE for 64-bit vectors.111define <2 x float> @fmaxnm_v2f32(<2 x float> %op1, <2 x float> %op2) vscale_range(2,0) #0 {112; CHECK-LABEL: fmaxnm_v2f32:113; CHECK: // %bb.0:114; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s115; CHECK-NEXT: ret116 %res = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %op1, <2 x float> %op2)117 ret <2 x float> %res118}119 120; Don't use SVE for 128-bit vectors.121define <4 x float> @fmaxnm_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range(2,0) #0 {122; CHECK-LABEL: fmaxnm_v4f32:123; CHECK: // %bb.0:124; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s125; CHECK-NEXT: ret126 %res = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %op1, <4 x float> %op2)127 ret <4 x float> %res128}129 130define void @fmaxnm_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {131; CHECK-LABEL: fmaxnm_v8f32:132; CHECK: // %bb.0:133; CHECK-NEXT: ptrue p0.s, vl8134; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]135; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]136; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s137; CHECK-NEXT: st1w { z0.s }, p0, [x0]138; CHECK-NEXT: ret139 %op1 = load <8 x float>, ptr %a140 %op2 = load <8 x float>, ptr %b141 %res = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %op1, <8 x float> %op2)142 store <8 x float> %res, ptr %a143 ret void144}145 146define void @fmaxnm_v16f32(ptr %a, ptr %b) #0 {147; VBITS_EQ_256-LABEL: fmaxnm_v16f32:148; VBITS_EQ_256: // %bb.0:149; VBITS_EQ_256-NEXT: ptrue p0.s, vl8150; VBITS_EQ_256-NEXT: mov x8, #8 // =0x8151; VBITS_EQ_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]152; VBITS_EQ_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]153; VBITS_EQ_256-NEXT: ld1w { z2.s }, p0/z, [x0]154; VBITS_EQ_256-NEXT: ld1w { z3.s }, p0/z, [x1]155; VBITS_EQ_256-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s156; VBITS_EQ_256-NEXT: fmaxnm z2.s, p0/m, z2.s, z3.s157; VBITS_EQ_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]158; VBITS_EQ_256-NEXT: st1w { z2.s }, p0, [x0]159; VBITS_EQ_256-NEXT: ret160;161; VBITS_GE_512-LABEL: fmaxnm_v16f32:162; VBITS_GE_512: // %bb.0:163; VBITS_GE_512-NEXT: ptrue p0.s, vl16164; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]165; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]166; VBITS_GE_512-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s167; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]168; VBITS_GE_512-NEXT: ret169 %op1 = load <16 x float>, ptr %a170 %op2 = load <16 x float>, ptr %b171 %res = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %op1, <16 x float> %op2)172 store <16 x float> %res, ptr %a173 ret void174}175 176define void @fmaxnm_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 {177; CHECK-LABEL: fmaxnm_v32f32:178; CHECK: // %bb.0:179; CHECK-NEXT: ptrue p0.s, vl32180; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]181; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]182; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s183; CHECK-NEXT: st1w { z0.s }, p0, [x0]184; CHECK-NEXT: ret185 %op1 = load <32 x float>, ptr %a186 %op2 = load <32 x float>, ptr %b187 %res = call <32 x float> @llvm.maxnum.v32f32(<32 x float> %op1, <32 x float> %op2)188 store <32 x float> %res, ptr %a189 ret void190}191 192define void @fmaxnm_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 {193; CHECK-LABEL: fmaxnm_v64f32:194; CHECK: // %bb.0:195; CHECK-NEXT: ptrue p0.s, vl64196; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]197; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]198; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s199; CHECK-NEXT: st1w { z0.s }, p0, [x0]200; CHECK-NEXT: ret201 %op1 = load <64 x float>, ptr %a202 %op2 = load <64 x float>, ptr %b203 %res = call <64 x float> @llvm.maxnum.v64f32(<64 x float> %op1, <64 x float> %op2)204 store <64 x float> %res, ptr %a205 ret void206}207 208; Don't use SVE for 64-bit vectors.209define <1 x double> @fmaxnm_v1f64(<1 x double> %op1, <1 x double> %op2) vscale_range(2,0) #0 {210; CHECK-LABEL: fmaxnm_v1f64:211; CHECK: // %bb.0:212; CHECK-NEXT: fmaxnm d0, d0, d1213; CHECK-NEXT: ret214 %res = call <1 x double> @llvm.maxnum.v1f64(<1 x double> %op1, <1 x double> %op2)215 ret <1 x double> %res216}217 218; Don't use SVE for 128-bit vectors.219define <2 x double> @fmaxnm_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_range(2,0) #0 {220; CHECK-LABEL: fmaxnm_v2f64:221; CHECK: // %bb.0:222; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d223; CHECK-NEXT: ret224 %res = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %op1, <2 x double> %op2)225 ret <2 x double> %res226}227 228define void @fmaxnm_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {229; CHECK-LABEL: fmaxnm_v4f64:230; CHECK: // %bb.0:231; CHECK-NEXT: ptrue p0.d, vl4232; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]233; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]234; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d235; CHECK-NEXT: st1d { z0.d }, p0, [x0]236; CHECK-NEXT: ret237 %op1 = load <4 x double>, ptr %a238 %op2 = load <4 x double>, ptr %b239 %res = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %op1, <4 x double> %op2)240 store <4 x double> %res, ptr %a241 ret void242}243 244define void @fmaxnm_v8f64(ptr %a, ptr %b) #0 {245; VBITS_EQ_256-LABEL: fmaxnm_v8f64:246; VBITS_EQ_256: // %bb.0:247; VBITS_EQ_256-NEXT: ptrue p0.d, vl4248; VBITS_EQ_256-NEXT: mov x8, #4 // =0x4249; VBITS_EQ_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]250; VBITS_EQ_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]251; VBITS_EQ_256-NEXT: ld1d { z2.d }, p0/z, [x0]252; VBITS_EQ_256-NEXT: ld1d { z3.d }, p0/z, [x1]253; VBITS_EQ_256-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d254; VBITS_EQ_256-NEXT: fmaxnm z2.d, p0/m, z2.d, z3.d255; VBITS_EQ_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]256; VBITS_EQ_256-NEXT: st1d { z2.d }, p0, [x0]257; VBITS_EQ_256-NEXT: ret258;259; VBITS_GE_512-LABEL: fmaxnm_v8f64:260; VBITS_GE_512: // %bb.0:261; VBITS_GE_512-NEXT: ptrue p0.d, vl8262; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]263; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]264; VBITS_GE_512-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d265; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]266; VBITS_GE_512-NEXT: ret267 %op1 = load <8 x double>, ptr %a268 %op2 = load <8 x double>, ptr %b269 %res = call <8 x double> @llvm.maxnum.v8f64(<8 x double> %op1, <8 x double> %op2)270 store <8 x double> %res, ptr %a271 ret void272}273 274define void @fmaxnm_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {275; CHECK-LABEL: fmaxnm_v16f64:276; CHECK: // %bb.0:277; CHECK-NEXT: ptrue p0.d, vl16278; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]279; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]280; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d281; CHECK-NEXT: st1d { z0.d }, p0, [x0]282; CHECK-NEXT: ret283 %op1 = load <16 x double>, ptr %a284 %op2 = load <16 x double>, ptr %b285 %res = call <16 x double> @llvm.maxnum.v16f64(<16 x double> %op1, <16 x double> %op2)286 store <16 x double> %res, ptr %a287 ret void288}289 290define void @fmaxnm_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {291; CHECK-LABEL: fmaxnm_v32f64:292; CHECK: // %bb.0:293; CHECK-NEXT: ptrue p0.d, vl32294; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]295; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]296; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d297; CHECK-NEXT: st1d { z0.d }, p0, [x0]298; CHECK-NEXT: ret299 %op1 = load <32 x double>, ptr %a300 %op2 = load <32 x double>, ptr %b301 %res = call <32 x double> @llvm.maxnum.v32f64(<32 x double> %op1, <32 x double> %op2)302 store <32 x double> %res, ptr %a303 ret void304}305 306;307; FMINNM308;309 310; Don't use SVE for 64-bit vectors.311define <4 x half> @fminnm_v4f16(<4 x half> %op1, <4 x half> %op2) vscale_range(2,0) #0 {312; CHECK-LABEL: fminnm_v4f16:313; CHECK: // %bb.0:314; CHECK-NEXT: fminnm v0.4h, v0.4h, v1.4h315; CHECK-NEXT: ret316 %res = call <4 x half> @llvm.minnum.v4f16(<4 x half> %op1, <4 x half> %op2)317 ret <4 x half> %res318}319 320; Don't use SVE for 128-bit vectors.321define <8 x half> @fminnm_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0) #0 {322; CHECK-LABEL: fminnm_v8f16:323; CHECK: // %bb.0:324; CHECK-NEXT: fminnm v0.8h, v0.8h, v1.8h325; CHECK-NEXT: ret326 %res = call <8 x half> @llvm.minnum.v8f16(<8 x half> %op1, <8 x half> %op2)327 ret <8 x half> %res328}329 330define void @fminnm_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {331; CHECK-LABEL: fminnm_v16f16:332; CHECK: // %bb.0:333; CHECK-NEXT: ptrue p0.h, vl16334; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]335; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]336; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h337; CHECK-NEXT: st1h { z0.h }, p0, [x0]338; CHECK-NEXT: ret339 %op1 = load <16 x half>, ptr %a340 %op2 = load <16 x half>, ptr %b341 %res = call <16 x half> @llvm.minnum.v16f16(<16 x half> %op1, <16 x half> %op2)342 store <16 x half> %res, ptr %a343 ret void344}345 346define void @fminnm_v32f16(ptr %a, ptr %b) #0 {347; VBITS_EQ_256-LABEL: fminnm_v32f16:348; VBITS_EQ_256: // %bb.0:349; VBITS_EQ_256-NEXT: ptrue p0.h, vl16350; VBITS_EQ_256-NEXT: mov x8, #16 // =0x10351; VBITS_EQ_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]352; VBITS_EQ_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]353; VBITS_EQ_256-NEXT: ld1h { z2.h }, p0/z, [x0]354; VBITS_EQ_256-NEXT: ld1h { z3.h }, p0/z, [x1]355; VBITS_EQ_256-NEXT: fminnm z0.h, p0/m, z0.h, z1.h356; VBITS_EQ_256-NEXT: fminnm z2.h, p0/m, z2.h, z3.h357; VBITS_EQ_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]358; VBITS_EQ_256-NEXT: st1h { z2.h }, p0, [x0]359; VBITS_EQ_256-NEXT: ret360;361; VBITS_GE_512-LABEL: fminnm_v32f16:362; VBITS_GE_512: // %bb.0:363; VBITS_GE_512-NEXT: ptrue p0.h, vl32364; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]365; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]366; VBITS_GE_512-NEXT: fminnm z0.h, p0/m, z0.h, z1.h367; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]368; VBITS_GE_512-NEXT: ret369 %op1 = load <32 x half>, ptr %a370 %op2 = load <32 x half>, ptr %b371 %res = call <32 x half> @llvm.minnum.v32f16(<32 x half> %op1, <32 x half> %op2)372 store <32 x half> %res, ptr %a373 ret void374}375 376define void @fminnm_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 {377; CHECK-LABEL: fminnm_v64f16:378; CHECK: // %bb.0:379; CHECK-NEXT: ptrue p0.h, vl64380; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]381; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]382; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h383; CHECK-NEXT: st1h { z0.h }, p0, [x0]384; CHECK-NEXT: ret385 %op1 = load <64 x half>, ptr %a386 %op2 = load <64 x half>, ptr %b387 %res = call <64 x half> @llvm.minnum.v64f16(<64 x half> %op1, <64 x half> %op2)388 store <64 x half> %res, ptr %a389 ret void390}391 392define void @fminnm_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 {393; CHECK-LABEL: fminnm_v128f16:394; CHECK: // %bb.0:395; CHECK-NEXT: ptrue p0.h, vl128396; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]397; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]398; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h399; CHECK-NEXT: st1h { z0.h }, p0, [x0]400; CHECK-NEXT: ret401 %op1 = load <128 x half>, ptr %a402 %op2 = load <128 x half>, ptr %b403 %res = call <128 x half> @llvm.minnum.v128f16(<128 x half> %op1, <128 x half> %op2)404 store <128 x half> %res, ptr %a405 ret void406}407 408; Don't use SVE for 64-bit vectors.409define <2 x float> @fminnm_v2f32(<2 x float> %op1, <2 x float> %op2) vscale_range(2,0) #0 {410; CHECK-LABEL: fminnm_v2f32:411; CHECK: // %bb.0:412; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s413; CHECK-NEXT: ret414 %res = call <2 x float> @llvm.minnum.v2f32(<2 x float> %op1, <2 x float> %op2)415 ret <2 x float> %res416}417 418; Don't use SVE for 128-bit vectors.419define <4 x float> @fminnm_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range(2,0) #0 {420; CHECK-LABEL: fminnm_v4f32:421; CHECK: // %bb.0:422; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s423; CHECK-NEXT: ret424 %res = call <4 x float> @llvm.minnum.v4f32(<4 x float> %op1, <4 x float> %op2)425 ret <4 x float> %res426}427 428define void @fminnm_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {429; CHECK-LABEL: fminnm_v8f32:430; CHECK: // %bb.0:431; CHECK-NEXT: ptrue p0.s, vl8432; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]433; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]434; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s435; CHECK-NEXT: st1w { z0.s }, p0, [x0]436; CHECK-NEXT: ret437 %op1 = load <8 x float>, ptr %a438 %op2 = load <8 x float>, ptr %b439 %res = call <8 x float> @llvm.minnum.v8f32(<8 x float> %op1, <8 x float> %op2)440 store <8 x float> %res, ptr %a441 ret void442}443 444define void @fminnm_v16f32(ptr %a, ptr %b) #0 {445; VBITS_EQ_256-LABEL: fminnm_v16f32:446; VBITS_EQ_256: // %bb.0:447; VBITS_EQ_256-NEXT: ptrue p0.s, vl8448; VBITS_EQ_256-NEXT: mov x8, #8 // =0x8449; VBITS_EQ_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]450; VBITS_EQ_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]451; VBITS_EQ_256-NEXT: ld1w { z2.s }, p0/z, [x0]452; VBITS_EQ_256-NEXT: ld1w { z3.s }, p0/z, [x1]453; VBITS_EQ_256-NEXT: fminnm z0.s, p0/m, z0.s, z1.s454; VBITS_EQ_256-NEXT: fminnm z2.s, p0/m, z2.s, z3.s455; VBITS_EQ_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]456; VBITS_EQ_256-NEXT: st1w { z2.s }, p0, [x0]457; VBITS_EQ_256-NEXT: ret458;459; VBITS_GE_512-LABEL: fminnm_v16f32:460; VBITS_GE_512: // %bb.0:461; VBITS_GE_512-NEXT: ptrue p0.s, vl16462; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]463; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]464; VBITS_GE_512-NEXT: fminnm z0.s, p0/m, z0.s, z1.s465; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]466; VBITS_GE_512-NEXT: ret467 %op1 = load <16 x float>, ptr %a468 %op2 = load <16 x float>, ptr %b469 %res = call <16 x float> @llvm.minnum.v16f32(<16 x float> %op1, <16 x float> %op2)470 store <16 x float> %res, ptr %a471 ret void472}473 474define void @fminnm_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 {475; CHECK-LABEL: fminnm_v32f32:476; CHECK: // %bb.0:477; CHECK-NEXT: ptrue p0.s, vl32478; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]479; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]480; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s481; CHECK-NEXT: st1w { z0.s }, p0, [x0]482; CHECK-NEXT: ret483 %op1 = load <32 x float>, ptr %a484 %op2 = load <32 x float>, ptr %b485 %res = call <32 x float> @llvm.minnum.v32f32(<32 x float> %op1, <32 x float> %op2)486 store <32 x float> %res, ptr %a487 ret void488}489 490define void @fminnm_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 {491; CHECK-LABEL: fminnm_v64f32:492; CHECK: // %bb.0:493; CHECK-NEXT: ptrue p0.s, vl64494; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]495; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]496; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s497; CHECK-NEXT: st1w { z0.s }, p0, [x0]498; CHECK-NEXT: ret499 %op1 = load <64 x float>, ptr %a500 %op2 = load <64 x float>, ptr %b501 %res = call <64 x float> @llvm.minnum.v64f32(<64 x float> %op1, <64 x float> %op2)502 store <64 x float> %res, ptr %a503 ret void504}505 506; Don't use SVE for 64-bit vectors.507define <1 x double> @fminnm_v1f64(<1 x double> %op1, <1 x double> %op2) vscale_range(2,0) #0 {508; CHECK-LABEL: fminnm_v1f64:509; CHECK: // %bb.0:510; CHECK-NEXT: fminnm d0, d0, d1511; CHECK-NEXT: ret512 %res = call <1 x double> @llvm.minnum.v1f64(<1 x double> %op1, <1 x double> %op2)513 ret <1 x double> %res514}515 516; Don't use SVE for 128-bit vectors.517define <2 x double> @fminnm_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_range(2,0) #0 {518; CHECK-LABEL: fminnm_v2f64:519; CHECK: // %bb.0:520; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d521; CHECK-NEXT: ret522 %res = call <2 x double> @llvm.minnum.v2f64(<2 x double> %op1, <2 x double> %op2)523 ret <2 x double> %res524}525 526define void @fminnm_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {527; CHECK-LABEL: fminnm_v4f64:528; CHECK: // %bb.0:529; CHECK-NEXT: ptrue p0.d, vl4530; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]531; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]532; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d533; CHECK-NEXT: st1d { z0.d }, p0, [x0]534; CHECK-NEXT: ret535 %op1 = load <4 x double>, ptr %a536 %op2 = load <4 x double>, ptr %b537 %res = call <4 x double> @llvm.minnum.v4f64(<4 x double> %op1, <4 x double> %op2)538 store <4 x double> %res, ptr %a539 ret void540}541 542define void @fminnm_v8f64(ptr %a, ptr %b) #0 {543; VBITS_EQ_256-LABEL: fminnm_v8f64:544; VBITS_EQ_256: // %bb.0:545; VBITS_EQ_256-NEXT: ptrue p0.d, vl4546; VBITS_EQ_256-NEXT: mov x8, #4 // =0x4547; VBITS_EQ_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]548; VBITS_EQ_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]549; VBITS_EQ_256-NEXT: ld1d { z2.d }, p0/z, [x0]550; VBITS_EQ_256-NEXT: ld1d { z3.d }, p0/z, [x1]551; VBITS_EQ_256-NEXT: fminnm z0.d, p0/m, z0.d, z1.d552; VBITS_EQ_256-NEXT: fminnm z2.d, p0/m, z2.d, z3.d553; VBITS_EQ_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]554; VBITS_EQ_256-NEXT: st1d { z2.d }, p0, [x0]555; VBITS_EQ_256-NEXT: ret556;557; VBITS_GE_512-LABEL: fminnm_v8f64:558; VBITS_GE_512: // %bb.0:559; VBITS_GE_512-NEXT: ptrue p0.d, vl8560; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]561; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]562; VBITS_GE_512-NEXT: fminnm z0.d, p0/m, z0.d, z1.d563; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]564; VBITS_GE_512-NEXT: ret565 %op1 = load <8 x double>, ptr %a566 %op2 = load <8 x double>, ptr %b567 %res = call <8 x double> @llvm.minnum.v8f64(<8 x double> %op1, <8 x double> %op2)568 store <8 x double> %res, ptr %a569 ret void570}571 572define void @fminnm_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {573; CHECK-LABEL: fminnm_v16f64:574; CHECK: // %bb.0:575; CHECK-NEXT: ptrue p0.d, vl16576; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]577; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]578; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d579; CHECK-NEXT: st1d { z0.d }, p0, [x0]580; CHECK-NEXT: ret581 %op1 = load <16 x double>, ptr %a582 %op2 = load <16 x double>, ptr %b583 %res = call <16 x double> @llvm.minnum.v16f64(<16 x double> %op1, <16 x double> %op2)584 store <16 x double> %res, ptr %a585 ret void586}587 588define void @fminnm_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {589; CHECK-LABEL: fminnm_v32f64:590; CHECK: // %bb.0:591; CHECK-NEXT: ptrue p0.d, vl32592; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]593; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]594; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d595; CHECK-NEXT: st1d { z0.d }, p0, [x0]596; CHECK-NEXT: ret597 %op1 = load <32 x double>, ptr %a598 %op2 = load <32 x double>, ptr %b599 %res = call <32 x double> @llvm.minnum.v32f64(<32 x double> %op1, <32 x double> %op2)600 store <32 x double> %res, ptr %a601 ret void602}603 604;605; FMAX606;607 608; Don't use SVE for 64-bit vectors.609define <4 x half> @fmax_v4f16(<4 x half> %op1, <4 x half> %op2) vscale_range(2,0) #0 {610; CHECK-LABEL: fmax_v4f16:611; CHECK: // %bb.0:612; CHECK-NEXT: fmax v0.4h, v0.4h, v1.4h613; CHECK-NEXT: ret614 %res = call <4 x half> @llvm.maximum.v4f16(<4 x half> %op1, <4 x half> %op2)615 ret <4 x half> %res616}617 618; Don't use SVE for 128-bit vectors.619define <8 x half> @fmax_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0) #0 {620; CHECK-LABEL: fmax_v8f16:621; CHECK: // %bb.0:622; CHECK-NEXT: fmax v0.8h, v0.8h, v1.8h623; CHECK-NEXT: ret624 %res = call <8 x half> @llvm.maximum.v8f16(<8 x half> %op1, <8 x half> %op2)625 ret <8 x half> %res626}627 628define void @fmax_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {629; CHECK-LABEL: fmax_v16f16:630; CHECK: // %bb.0:631; CHECK-NEXT: ptrue p0.h, vl16632; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]633; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]634; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h635; CHECK-NEXT: st1h { z0.h }, p0, [x0]636; CHECK-NEXT: ret637 %op1 = load <16 x half>, ptr %a638 %op2 = load <16 x half>, ptr %b639 %res = call <16 x half> @llvm.maximum.v16f16(<16 x half> %op1, <16 x half> %op2)640 store <16 x half> %res, ptr %a641 ret void642}643 644define void @fmax_v32f16(ptr %a, ptr %b) #0 {645; VBITS_EQ_256-LABEL: fmax_v32f16:646; VBITS_EQ_256: // %bb.0:647; VBITS_EQ_256-NEXT: ptrue p0.h, vl16648; VBITS_EQ_256-NEXT: mov x8, #16 // =0x10649; VBITS_EQ_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]650; VBITS_EQ_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]651; VBITS_EQ_256-NEXT: ld1h { z2.h }, p0/z, [x0]652; VBITS_EQ_256-NEXT: ld1h { z3.h }, p0/z, [x1]653; VBITS_EQ_256-NEXT: fmax z0.h, p0/m, z0.h, z1.h654; VBITS_EQ_256-NEXT: fmax z2.h, p0/m, z2.h, z3.h655; VBITS_EQ_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]656; VBITS_EQ_256-NEXT: st1h { z2.h }, p0, [x0]657; VBITS_EQ_256-NEXT: ret658;659; VBITS_GE_512-LABEL: fmax_v32f16:660; VBITS_GE_512: // %bb.0:661; VBITS_GE_512-NEXT: ptrue p0.h, vl32662; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]663; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]664; VBITS_GE_512-NEXT: fmax z0.h, p0/m, z0.h, z1.h665; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]666; VBITS_GE_512-NEXT: ret667 %op1 = load <32 x half>, ptr %a668 %op2 = load <32 x half>, ptr %b669 %res = call <32 x half> @llvm.maximum.v32f16(<32 x half> %op1, <32 x half> %op2)670 store <32 x half> %res, ptr %a671 ret void672}673 674define void @fmax_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 {675; CHECK-LABEL: fmax_v64f16:676; CHECK: // %bb.0:677; CHECK-NEXT: ptrue p0.h, vl64678; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]679; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]680; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h681; CHECK-NEXT: st1h { z0.h }, p0, [x0]682; CHECK-NEXT: ret683 %op1 = load <64 x half>, ptr %a684 %op2 = load <64 x half>, ptr %b685 %res = call <64 x half> @llvm.maximum.v64f16(<64 x half> %op1, <64 x half> %op2)686 store <64 x half> %res, ptr %a687 ret void688}689 690define void @fmax_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 {691; CHECK-LABEL: fmax_v128f16:692; CHECK: // %bb.0:693; CHECK-NEXT: ptrue p0.h, vl128694; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]695; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]696; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h697; CHECK-NEXT: st1h { z0.h }, p0, [x0]698; CHECK-NEXT: ret699 %op1 = load <128 x half>, ptr %a700 %op2 = load <128 x half>, ptr %b701 %res = call <128 x half> @llvm.maximum.v128f16(<128 x half> %op1, <128 x half> %op2)702 store <128 x half> %res, ptr %a703 ret void704}705 706; Don't use SVE for 64-bit vectors.707define <2 x float> @fmax_v2f32(<2 x float> %op1, <2 x float> %op2) vscale_range(2,0) #0 {708; CHECK-LABEL: fmax_v2f32:709; CHECK: // %bb.0:710; CHECK-NEXT: fmax v0.2s, v0.2s, v1.2s711; CHECK-NEXT: ret712 %res = call <2 x float> @llvm.maximum.v2f32(<2 x float> %op1, <2 x float> %op2)713 ret <2 x float> %res714}715 716; Don't use SVE for 128-bit vectors.717define <4 x float> @fmax_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range(2,0) #0 {718; CHECK-LABEL: fmax_v4f32:719; CHECK: // %bb.0:720; CHECK-NEXT: fmax v0.4s, v0.4s, v1.4s721; CHECK-NEXT: ret722 %res = call <4 x float> @llvm.maximum.v4f32(<4 x float> %op1, <4 x float> %op2)723 ret <4 x float> %res724}725 726define void @fmax_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {727; CHECK-LABEL: fmax_v8f32:728; CHECK: // %bb.0:729; CHECK-NEXT: ptrue p0.s, vl8730; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]731; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]732; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s733; CHECK-NEXT: st1w { z0.s }, p0, [x0]734; CHECK-NEXT: ret735 %op1 = load <8 x float>, ptr %a736 %op2 = load <8 x float>, ptr %b737 %res = call <8 x float> @llvm.maximum.v8f32(<8 x float> %op1, <8 x float> %op2)738 store <8 x float> %res, ptr %a739 ret void740}741 742define void @fmax_v16f32(ptr %a, ptr %b) #0 {743; VBITS_EQ_256-LABEL: fmax_v16f32:744; VBITS_EQ_256: // %bb.0:745; VBITS_EQ_256-NEXT: ptrue p0.s, vl8746; VBITS_EQ_256-NEXT: mov x8, #8 // =0x8747; VBITS_EQ_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]748; VBITS_EQ_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]749; VBITS_EQ_256-NEXT: ld1w { z2.s }, p0/z, [x0]750; VBITS_EQ_256-NEXT: ld1w { z3.s }, p0/z, [x1]751; VBITS_EQ_256-NEXT: fmax z0.s, p0/m, z0.s, z1.s752; VBITS_EQ_256-NEXT: fmax z2.s, p0/m, z2.s, z3.s753; VBITS_EQ_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]754; VBITS_EQ_256-NEXT: st1w { z2.s }, p0, [x0]755; VBITS_EQ_256-NEXT: ret756;757; VBITS_GE_512-LABEL: fmax_v16f32:758; VBITS_GE_512: // %bb.0:759; VBITS_GE_512-NEXT: ptrue p0.s, vl16760; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]761; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]762; VBITS_GE_512-NEXT: fmax z0.s, p0/m, z0.s, z1.s763; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]764; VBITS_GE_512-NEXT: ret765 %op1 = load <16 x float>, ptr %a766 %op2 = load <16 x float>, ptr %b767 %res = call <16 x float> @llvm.maximum.v16f32(<16 x float> %op1, <16 x float> %op2)768 store <16 x float> %res, ptr %a769 ret void770}771 772define void @fmax_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 {773; CHECK-LABEL: fmax_v32f32:774; CHECK: // %bb.0:775; CHECK-NEXT: ptrue p0.s, vl32776; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]777; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]778; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s779; CHECK-NEXT: st1w { z0.s }, p0, [x0]780; CHECK-NEXT: ret781 %op1 = load <32 x float>, ptr %a782 %op2 = load <32 x float>, ptr %b783 %res = call <32 x float> @llvm.maximum.v32f32(<32 x float> %op1, <32 x float> %op2)784 store <32 x float> %res, ptr %a785 ret void786}787 788define void @fmax_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 {789; CHECK-LABEL: fmax_v64f32:790; CHECK: // %bb.0:791; CHECK-NEXT: ptrue p0.s, vl64792; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]793; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]794; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s795; CHECK-NEXT: st1w { z0.s }, p0, [x0]796; CHECK-NEXT: ret797 %op1 = load <64 x float>, ptr %a798 %op2 = load <64 x float>, ptr %b799 %res = call <64 x float> @llvm.maximum.v64f32(<64 x float> %op1, <64 x float> %op2)800 store <64 x float> %res, ptr %a801 ret void802}803 804; Don't use SVE for 64-bit vectors.805define <1 x double> @fmax_v1f64(<1 x double> %op1, <1 x double> %op2) vscale_range(2,0) #0 {806; CHECK-LABEL: fmax_v1f64:807; CHECK: // %bb.0:808; CHECK-NEXT: fmax d0, d0, d1809; CHECK-NEXT: ret810 %res = call <1 x double> @llvm.maximum.v1f64(<1 x double> %op1, <1 x double> %op2)811 ret <1 x double> %res812}813 814; Don't use SVE for 128-bit vectors.815define <2 x double> @fmax_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_range(2,0) #0 {816; CHECK-LABEL: fmax_v2f64:817; CHECK: // %bb.0:818; CHECK-NEXT: fmax v0.2d, v0.2d, v1.2d819; CHECK-NEXT: ret820 %res = call <2 x double> @llvm.maximum.v2f64(<2 x double> %op1, <2 x double> %op2)821 ret <2 x double> %res822}823 824define void @fmax_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {825; CHECK-LABEL: fmax_v4f64:826; CHECK: // %bb.0:827; CHECK-NEXT: ptrue p0.d, vl4828; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]829; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]830; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d831; CHECK-NEXT: st1d { z0.d }, p0, [x0]832; CHECK-NEXT: ret833 %op1 = load <4 x double>, ptr %a834 %op2 = load <4 x double>, ptr %b835 %res = call <4 x double> @llvm.maximum.v4f64(<4 x double> %op1, <4 x double> %op2)836 store <4 x double> %res, ptr %a837 ret void838}839 840define void @fmax_v8f64(ptr %a, ptr %b) #0 {841; VBITS_EQ_256-LABEL: fmax_v8f64:842; VBITS_EQ_256: // %bb.0:843; VBITS_EQ_256-NEXT: ptrue p0.d, vl4844; VBITS_EQ_256-NEXT: mov x8, #4 // =0x4845; VBITS_EQ_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]846; VBITS_EQ_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]847; VBITS_EQ_256-NEXT: ld1d { z2.d }, p0/z, [x0]848; VBITS_EQ_256-NEXT: ld1d { z3.d }, p0/z, [x1]849; VBITS_EQ_256-NEXT: fmax z0.d, p0/m, z0.d, z1.d850; VBITS_EQ_256-NEXT: fmax z2.d, p0/m, z2.d, z3.d851; VBITS_EQ_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]852; VBITS_EQ_256-NEXT: st1d { z2.d }, p0, [x0]853; VBITS_EQ_256-NEXT: ret854;855; VBITS_GE_512-LABEL: fmax_v8f64:856; VBITS_GE_512: // %bb.0:857; VBITS_GE_512-NEXT: ptrue p0.d, vl8858; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]859; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]860; VBITS_GE_512-NEXT: fmax z0.d, p0/m, z0.d, z1.d861; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]862; VBITS_GE_512-NEXT: ret863 %op1 = load <8 x double>, ptr %a864 %op2 = load <8 x double>, ptr %b865 %res = call <8 x double> @llvm.maximum.v8f64(<8 x double> %op1, <8 x double> %op2)866 store <8 x double> %res, ptr %a867 ret void868}869 870define void @fmax_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {871; CHECK-LABEL: fmax_v16f64:872; CHECK: // %bb.0:873; CHECK-NEXT: ptrue p0.d, vl16874; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]875; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]876; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d877; CHECK-NEXT: st1d { z0.d }, p0, [x0]878; CHECK-NEXT: ret879 %op1 = load <16 x double>, ptr %a880 %op2 = load <16 x double>, ptr %b881 %res = call <16 x double> @llvm.maximum.v16f64(<16 x double> %op1, <16 x double> %op2)882 store <16 x double> %res, ptr %a883 ret void884}885 886define void @fmax_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {887; CHECK-LABEL: fmax_v32f64:888; CHECK: // %bb.0:889; CHECK-NEXT: ptrue p0.d, vl32890; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]891; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]892; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d893; CHECK-NEXT: st1d { z0.d }, p0, [x0]894; CHECK-NEXT: ret895 %op1 = load <32 x double>, ptr %a896 %op2 = load <32 x double>, ptr %b897 %res = call <32 x double> @llvm.maximum.v32f64(<32 x double> %op1, <32 x double> %op2)898 store <32 x double> %res, ptr %a899 ret void900}901 902;903; FMIN904;905 906; Don't use SVE for 64-bit vectors.907define <4 x half> @fmin_v4f16(<4 x half> %op1, <4 x half> %op2) vscale_range(2,0) #0 {908; CHECK-LABEL: fmin_v4f16:909; CHECK: // %bb.0:910; CHECK-NEXT: fmin v0.4h, v0.4h, v1.4h911; CHECK-NEXT: ret912 %res = call <4 x half> @llvm.minimum.v4f16(<4 x half> %op1, <4 x half> %op2)913 ret <4 x half> %res914}915 916; Don't use SVE for 128-bit vectors.917define <8 x half> @fmin_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0) #0 {918; CHECK-LABEL: fmin_v8f16:919; CHECK: // %bb.0:920; CHECK-NEXT: fmin v0.8h, v0.8h, v1.8h921; CHECK-NEXT: ret922 %res = call <8 x half> @llvm.minimum.v8f16(<8 x half> %op1, <8 x half> %op2)923 ret <8 x half> %res924}925 926define void @fmin_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {927; CHECK-LABEL: fmin_v16f16:928; CHECK: // %bb.0:929; CHECK-NEXT: ptrue p0.h, vl16930; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]931; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]932; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h933; CHECK-NEXT: st1h { z0.h }, p0, [x0]934; CHECK-NEXT: ret935 %op1 = load <16 x half>, ptr %a936 %op2 = load <16 x half>, ptr %b937 %res = call <16 x half> @llvm.minimum.v16f16(<16 x half> %op1, <16 x half> %op2)938 store <16 x half> %res, ptr %a939 ret void940}941 942define void @fmin_v32f16(ptr %a, ptr %b) #0 {943; VBITS_EQ_256-LABEL: fmin_v32f16:944; VBITS_EQ_256: // %bb.0:945; VBITS_EQ_256-NEXT: ptrue p0.h, vl16946; VBITS_EQ_256-NEXT: mov x8, #16 // =0x10947; VBITS_EQ_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]948; VBITS_EQ_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]949; VBITS_EQ_256-NEXT: ld1h { z2.h }, p0/z, [x0]950; VBITS_EQ_256-NEXT: ld1h { z3.h }, p0/z, [x1]951; VBITS_EQ_256-NEXT: fmin z0.h, p0/m, z0.h, z1.h952; VBITS_EQ_256-NEXT: fmin z2.h, p0/m, z2.h, z3.h953; VBITS_EQ_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]954; VBITS_EQ_256-NEXT: st1h { z2.h }, p0, [x0]955; VBITS_EQ_256-NEXT: ret956;957; VBITS_GE_512-LABEL: fmin_v32f16:958; VBITS_GE_512: // %bb.0:959; VBITS_GE_512-NEXT: ptrue p0.h, vl32960; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]961; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]962; VBITS_GE_512-NEXT: fmin z0.h, p0/m, z0.h, z1.h963; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]964; VBITS_GE_512-NEXT: ret965 %op1 = load <32 x half>, ptr %a966 %op2 = load <32 x half>, ptr %b967 %res = call <32 x half> @llvm.minimum.v32f16(<32 x half> %op1, <32 x half> %op2)968 store <32 x half> %res, ptr %a969 ret void970}971 972define void @fmin_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 {973; CHECK-LABEL: fmin_v64f16:974; CHECK: // %bb.0:975; CHECK-NEXT: ptrue p0.h, vl64976; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]977; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]978; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h979; CHECK-NEXT: st1h { z0.h }, p0, [x0]980; CHECK-NEXT: ret981 %op1 = load <64 x half>, ptr %a982 %op2 = load <64 x half>, ptr %b983 %res = call <64 x half> @llvm.minimum.v64f16(<64 x half> %op1, <64 x half> %op2)984 store <64 x half> %res, ptr %a985 ret void986}987 988define void @fmin_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 {989; CHECK-LABEL: fmin_v128f16:990; CHECK: // %bb.0:991; CHECK-NEXT: ptrue p0.h, vl128992; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]993; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]994; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h995; CHECK-NEXT: st1h { z0.h }, p0, [x0]996; CHECK-NEXT: ret997 %op1 = load <128 x half>, ptr %a998 %op2 = load <128 x half>, ptr %b999 %res = call <128 x half> @llvm.minimum.v128f16(<128 x half> %op1, <128 x half> %op2)1000 store <128 x half> %res, ptr %a1001 ret void1002}1003 1004; Don't use SVE for 64-bit vectors.1005define <2 x float> @fmin_v2f32(<2 x float> %op1, <2 x float> %op2) vscale_range(2,0) #0 {1006; CHECK-LABEL: fmin_v2f32:1007; CHECK: // %bb.0:1008; CHECK-NEXT: fmin v0.2s, v0.2s, v1.2s1009; CHECK-NEXT: ret1010 %res = call <2 x float> @llvm.minimum.v2f32(<2 x float> %op1, <2 x float> %op2)1011 ret <2 x float> %res1012}1013 1014; Don't use SVE for 128-bit vectors.1015define <4 x float> @fmin_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range(2,0) #0 {1016; CHECK-LABEL: fmin_v4f32:1017; CHECK: // %bb.0:1018; CHECK-NEXT: fmin v0.4s, v0.4s, v1.4s1019; CHECK-NEXT: ret1020 %res = call <4 x float> @llvm.minimum.v4f32(<4 x float> %op1, <4 x float> %op2)1021 ret <4 x float> %res1022}1023 1024define void @fmin_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {1025; CHECK-LABEL: fmin_v8f32:1026; CHECK: // %bb.0:1027; CHECK-NEXT: ptrue p0.s, vl81028; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1029; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1030; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s1031; CHECK-NEXT: st1w { z0.s }, p0, [x0]1032; CHECK-NEXT: ret1033 %op1 = load <8 x float>, ptr %a1034 %op2 = load <8 x float>, ptr %b1035 %res = call <8 x float> @llvm.minimum.v8f32(<8 x float> %op1, <8 x float> %op2)1036 store <8 x float> %res, ptr %a1037 ret void1038}1039 1040define void @fmin_v16f32(ptr %a, ptr %b) #0 {1041; VBITS_EQ_256-LABEL: fmin_v16f32:1042; VBITS_EQ_256: // %bb.0:1043; VBITS_EQ_256-NEXT: ptrue p0.s, vl81044; VBITS_EQ_256-NEXT: mov x8, #8 // =0x81045; VBITS_EQ_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]1046; VBITS_EQ_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]1047; VBITS_EQ_256-NEXT: ld1w { z2.s }, p0/z, [x0]1048; VBITS_EQ_256-NEXT: ld1w { z3.s }, p0/z, [x1]1049; VBITS_EQ_256-NEXT: fmin z0.s, p0/m, z0.s, z1.s1050; VBITS_EQ_256-NEXT: fmin z2.s, p0/m, z2.s, z3.s1051; VBITS_EQ_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]1052; VBITS_EQ_256-NEXT: st1w { z2.s }, p0, [x0]1053; VBITS_EQ_256-NEXT: ret1054;1055; VBITS_GE_512-LABEL: fmin_v16f32:1056; VBITS_GE_512: // %bb.0:1057; VBITS_GE_512-NEXT: ptrue p0.s, vl161058; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]1059; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]1060; VBITS_GE_512-NEXT: fmin z0.s, p0/m, z0.s, z1.s1061; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]1062; VBITS_GE_512-NEXT: ret1063 %op1 = load <16 x float>, ptr %a1064 %op2 = load <16 x float>, ptr %b1065 %res = call <16 x float> @llvm.minimum.v16f32(<16 x float> %op1, <16 x float> %op2)1066 store <16 x float> %res, ptr %a1067 ret void1068}1069 1070define void @fmin_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 {1071; CHECK-LABEL: fmin_v32f32:1072; CHECK: // %bb.0:1073; CHECK-NEXT: ptrue p0.s, vl321074; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1075; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1076; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s1077; CHECK-NEXT: st1w { z0.s }, p0, [x0]1078; CHECK-NEXT: ret1079 %op1 = load <32 x float>, ptr %a1080 %op2 = load <32 x float>, ptr %b1081 %res = call <32 x float> @llvm.minimum.v32f32(<32 x float> %op1, <32 x float> %op2)1082 store <32 x float> %res, ptr %a1083 ret void1084}1085 1086define void @fmin_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 {1087; CHECK-LABEL: fmin_v64f32:1088; CHECK: // %bb.0:1089; CHECK-NEXT: ptrue p0.s, vl641090; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1091; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1092; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s1093; CHECK-NEXT: st1w { z0.s }, p0, [x0]1094; CHECK-NEXT: ret1095 %op1 = load <64 x float>, ptr %a1096 %op2 = load <64 x float>, ptr %b1097 %res = call <64 x float> @llvm.minimum.v64f32(<64 x float> %op1, <64 x float> %op2)1098 store <64 x float> %res, ptr %a1099 ret void1100}1101 1102; Don't use SVE for 64-bit vectors.1103define <1 x double> @fmin_v1f64(<1 x double> %op1, <1 x double> %op2) vscale_range(2,0) #0 {1104; CHECK-LABEL: fmin_v1f64:1105; CHECK: // %bb.0:1106; CHECK-NEXT: fmin d0, d0, d11107; CHECK-NEXT: ret1108 %res = call <1 x double> @llvm.minimum.v1f64(<1 x double> %op1, <1 x double> %op2)1109 ret <1 x double> %res1110}1111 1112; Don't use SVE for 128-bit vectors.1113define <2 x double> @fmin_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_range(2,0) #0 {1114; CHECK-LABEL: fmin_v2f64:1115; CHECK: // %bb.0:1116; CHECK-NEXT: fmin v0.2d, v0.2d, v1.2d1117; CHECK-NEXT: ret1118 %res = call <2 x double> @llvm.minimum.v2f64(<2 x double> %op1, <2 x double> %op2)1119 ret <2 x double> %res1120}1121 1122define void @fmin_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {1123; CHECK-LABEL: fmin_v4f64:1124; CHECK: // %bb.0:1125; CHECK-NEXT: ptrue p0.d, vl41126; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1127; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1128; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d1129; CHECK-NEXT: st1d { z0.d }, p0, [x0]1130; CHECK-NEXT: ret1131 %op1 = load <4 x double>, ptr %a1132 %op2 = load <4 x double>, ptr %b1133 %res = call <4 x double> @llvm.minimum.v4f64(<4 x double> %op1, <4 x double> %op2)1134 store <4 x double> %res, ptr %a1135 ret void1136}1137 1138define void @fmin_v8f64(ptr %a, ptr %b) #0 {1139; VBITS_EQ_256-LABEL: fmin_v8f64:1140; VBITS_EQ_256: // %bb.0:1141; VBITS_EQ_256-NEXT: ptrue p0.d, vl41142; VBITS_EQ_256-NEXT: mov x8, #4 // =0x41143; VBITS_EQ_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]1144; VBITS_EQ_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]1145; VBITS_EQ_256-NEXT: ld1d { z2.d }, p0/z, [x0]1146; VBITS_EQ_256-NEXT: ld1d { z3.d }, p0/z, [x1]1147; VBITS_EQ_256-NEXT: fmin z0.d, p0/m, z0.d, z1.d1148; VBITS_EQ_256-NEXT: fmin z2.d, p0/m, z2.d, z3.d1149; VBITS_EQ_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]1150; VBITS_EQ_256-NEXT: st1d { z2.d }, p0, [x0]1151; VBITS_EQ_256-NEXT: ret1152;1153; VBITS_GE_512-LABEL: fmin_v8f64:1154; VBITS_GE_512: // %bb.0:1155; VBITS_GE_512-NEXT: ptrue p0.d, vl81156; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]1157; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]1158; VBITS_GE_512-NEXT: fmin z0.d, p0/m, z0.d, z1.d1159; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]1160; VBITS_GE_512-NEXT: ret1161 %op1 = load <8 x double>, ptr %a1162 %op2 = load <8 x double>, ptr %b1163 %res = call <8 x double> @llvm.minimum.v8f64(<8 x double> %op1, <8 x double> %op2)1164 store <8 x double> %res, ptr %a1165 ret void1166}1167 1168define void @fmin_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {1169; CHECK-LABEL: fmin_v16f64:1170; CHECK: // %bb.0:1171; CHECK-NEXT: ptrue p0.d, vl161172; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1173; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1174; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d1175; CHECK-NEXT: st1d { z0.d }, p0, [x0]1176; CHECK-NEXT: ret1177 %op1 = load <16 x double>, ptr %a1178 %op2 = load <16 x double>, ptr %b1179 %res = call <16 x double> @llvm.minimum.v16f64(<16 x double> %op1, <16 x double> %op2)1180 store <16 x double> %res, ptr %a1181 ret void1182}1183 1184define void @fmin_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {1185; CHECK-LABEL: fmin_v32f64:1186; CHECK: // %bb.0:1187; CHECK-NEXT: ptrue p0.d, vl321188; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1189; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1190; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d1191; CHECK-NEXT: st1d { z0.d }, p0, [x0]1192; CHECK-NEXT: ret1193 %op1 = load <32 x double>, ptr %a1194 %op2 = load <32 x double>, ptr %b1195 %res = call <32 x double> @llvm.minimum.v32f64(<32 x double> %op1, <32 x double> %op2)1196 store <32 x double> %res, ptr %a1197 ret void1198}1199 1200attributes #0 = { "target-features"="+sve" }1201 1202declare <4 x half> @llvm.minnum.v4f16(<4 x half>, <4 x half>)1203declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>)1204declare <16 x half> @llvm.minnum.v16f16(<16 x half>, <16 x half>)1205declare <32 x half> @llvm.minnum.v32f16(<32 x half>, <32 x half>)1206declare <64 x half> @llvm.minnum.v64f16(<64 x half>, <64 x half>)1207declare <128 x half> @llvm.minnum.v128f16(<128 x half>, <128 x half>)1208declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)1209declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)1210declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>)1211declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>)1212declare <32 x float> @llvm.minnum.v32f32(<32 x float>, <32 x float>)1213declare <64 x float> @llvm.minnum.v64f32(<64 x float>, <64 x float>)1214declare <1 x double> @llvm.minnum.v1f64(<1 x double>, <1 x double>)1215declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>)1216declare <4 x double> @llvm.minnum.v4f64(<4 x double>, <4 x double>)1217declare <8 x double> @llvm.minnum.v8f64(<8 x double>, <8 x double>)1218declare <16 x double> @llvm.minnum.v16f64(<16 x double>, <16 x double>)1219declare <32 x double> @llvm.minnum.v32f64(<32 x double>, <32 x double>)1220 1221declare <4 x half> @llvm.maxnum.v4f16(<4 x half>, <4 x half>)1222declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>)1223declare <16 x half> @llvm.maxnum.v16f16(<16 x half>, <16 x half>)1224declare <32 x half> @llvm.maxnum.v32f16(<32 x half>, <32 x half>)1225declare <64 x half> @llvm.maxnum.v64f16(<64 x half>, <64 x half>)1226declare <128 x half> @llvm.maxnum.v128f16(<128 x half>, <128 x half>)1227declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)1228declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>)1229declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>)1230declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>)1231declare <32 x float> @llvm.maxnum.v32f32(<32 x float>, <32 x float>)1232declare <64 x float> @llvm.maxnum.v64f32(<64 x float>, <64 x float>)1233declare <1 x double> @llvm.maxnum.v1f64(<1 x double>, <1 x double>)1234declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>)1235declare <4 x double> @llvm.maxnum.v4f64(<4 x double>, <4 x double>)1236declare <8 x double> @llvm.maxnum.v8f64(<8 x double>, <8 x double>)1237declare <16 x double> @llvm.maxnum.v16f64(<16 x double>, <16 x double>)1238declare <32 x double> @llvm.maxnum.v32f64(<32 x double>, <32 x double>)1239 1240declare <4 x half> @llvm.minimum.v4f16(<4 x half>, <4 x half>)1241declare <8 x half> @llvm.minimum.v8f16(<8 x half>, <8 x half>)1242declare <16 x half> @llvm.minimum.v16f16(<16 x half>, <16 x half>)1243declare <32 x half> @llvm.minimum.v32f16(<32 x half>, <32 x half>)1244declare <64 x half> @llvm.minimum.v64f16(<64 x half>, <64 x half>)1245declare <128 x half> @llvm.minimum.v128f16(<128 x half>, <128 x half>)1246declare <2 x float> @llvm.minimum.v2f32(<2 x float>, <2 x float>)1247declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>)1248declare <8 x float> @llvm.minimum.v8f32(<8 x float>, <8 x float>)1249declare <16 x float> @llvm.minimum.v16f32(<16 x float>, <16 x float>)1250declare <32 x float> @llvm.minimum.v32f32(<32 x float>, <32 x float>)1251declare <64 x float> @llvm.minimum.v64f32(<64 x float>, <64 x float>)1252declare <1 x double> @llvm.minimum.v1f64(<1 x double>, <1 x double>)1253declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>)1254declare <4 x double> @llvm.minimum.v4f64(<4 x double>, <4 x double>)1255declare <8 x double> @llvm.minimum.v8f64(<8 x double>, <8 x double>)1256declare <16 x double> @llvm.minimum.v16f64(<16 x double>, <16 x double>)1257declare <32 x double> @llvm.minimum.v32f64(<32 x double>, <32 x double>)1258 1259declare <4 x half> @llvm.maximum.v4f16(<4 x half>, <4 x half>)1260declare <8 x half> @llvm.maximum.v8f16(<8 x half>, <8 x half>)1261declare <16 x half> @llvm.maximum.v16f16(<16 x half>, <16 x half>)1262declare <32 x half> @llvm.maximum.v32f16(<32 x half>, <32 x half>)1263declare <64 x half> @llvm.maximum.v64f16(<64 x half>, <64 x half>)1264declare <128 x half> @llvm.maximum.v128f16(<128 x half>, <128 x half>)1265declare <2 x float> @llvm.maximum.v2f32(<2 x float>, <2 x float>)1266declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>)1267declare <8 x float> @llvm.maximum.v8f32(<8 x float>, <8 x float>)1268declare <16 x float> @llvm.maximum.v16f32(<16 x float>, <16 x float>)1269declare <32 x float> @llvm.maximum.v32f32(<32 x float>, <32 x float>)1270declare <64 x float> @llvm.maximum.v64f32(<64 x float>, <64 x float>)1271declare <1 x double> @llvm.maximum.v1f64(<1 x double>, <1 x double>)1272declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>)1273declare <4 x double> @llvm.maximum.v4f64(<4 x double>, <4 x double>)1274declare <8 x double> @llvm.maximum.v8f64(<8 x double>, <8 x double>)1275declare <16 x double> @llvm.maximum.v16f64(<16 x double>, <16 x double>)1276declare <32 x double> @llvm.maximum.v32f64(<32 x double>, <32 x double>)1277