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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8; Don't use SVE for 64-bit vectors.9define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, i1 %mask) vscale_range(2,0) #0 {10; CHECK-LABEL: select_v4f16:11; CHECK: // %bb.0:12; CHECK-NEXT: tst w0, #0x113; CHECK-NEXT: csetm w8, ne14; CHECK-NEXT: dup v2.4h, w815; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b16; CHECK-NEXT: ret17 %sel = select i1 %mask, <4 x half> %op1, <4 x half> %op218 ret <4 x half> %sel19}20 21; Don't use SVE for 128-bit vectors.22define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, i1 %mask) vscale_range(2,0) #0 {23; CHECK-LABEL: select_v8f16:24; CHECK: // %bb.0:25; CHECK-NEXT: tst w0, #0x126; CHECK-NEXT: csetm w8, ne27; CHECK-NEXT: dup v2.8h, w828; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b29; CHECK-NEXT: ret30 %sel = select i1 %mask, <8 x half> %op1, <8 x half> %op231 ret <8 x half> %sel32}33 34define void @select_v16f16(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 {35; CHECK-LABEL: select_v16f16:36; CHECK: // %bb.0:37; CHECK-NEXT: mov z0.h, w238; CHECK-NEXT: ptrue p0.h39; CHECK-NEXT: ptrue p1.h, vl1640; CHECK-NEXT: and z0.h, z0.h, #0x141; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #042; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0]43; CHECK-NEXT: ld1h { z1.h }, p1/z, [x1]44; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h45; CHECK-NEXT: st1h { z0.h }, p1, [x0]46; CHECK-NEXT: ret47 %op1 = load volatile <16 x half>, ptr %a48 %op2 = load volatile <16 x half>, ptr %b49 %sel = select i1 %mask, <16 x half> %op1, <16 x half> %op250 store <16 x half> %sel, ptr %a51 ret void52}53 54define void @select_v32f16(ptr %a, ptr %b, i1 %mask) #0 {55; VBITS_GE_256-LABEL: select_v32f16:56; VBITS_GE_256: // %bb.0:57; VBITS_GE_256-NEXT: mov z0.h, w258; VBITS_GE_256-NEXT: ptrue p0.h59; VBITS_GE_256-NEXT: mov x8, #16 // =0x1060; VBITS_GE_256-NEXT: ptrue p1.h, vl1661; VBITS_GE_256-NEXT: and z0.h, z0.h, #0x162; VBITS_GE_256-NEXT: cmpne p0.h, p0/z, z0.h, #063; VBITS_GE_256-NEXT: ld1h { z0.h }, p1/z, [x0, x8, lsl #1]64; VBITS_GE_256-NEXT: ld1h { z1.h }, p1/z, [x0]65; VBITS_GE_256-NEXT: ld1h { z2.h }, p1/z, [x1, x8, lsl #1]66; VBITS_GE_256-NEXT: ld1h { z3.h }, p1/z, [x1]67; VBITS_GE_256-NEXT: sel z0.h, p0, z0.h, z2.h68; VBITS_GE_256-NEXT: sel z1.h, p0, z1.h, z3.h69; VBITS_GE_256-NEXT: st1h { z0.h }, p1, [x0, x8, lsl #1]70; VBITS_GE_256-NEXT: st1h { z1.h }, p1, [x0]71; VBITS_GE_256-NEXT: ret72;73; VBITS_GE_512-LABEL: select_v32f16:74; VBITS_GE_512: // %bb.0:75; VBITS_GE_512-NEXT: mov z0.h, w276; VBITS_GE_512-NEXT: ptrue p0.h77; VBITS_GE_512-NEXT: ptrue p1.h, vl3278; VBITS_GE_512-NEXT: and z0.h, z0.h, #0x179; VBITS_GE_512-NEXT: cmpne p0.h, p0/z, z0.h, #080; VBITS_GE_512-NEXT: ld1h { z0.h }, p1/z, [x0]81; VBITS_GE_512-NEXT: ld1h { z1.h }, p1/z, [x1]82; VBITS_GE_512-NEXT: sel z0.h, p0, z0.h, z1.h83; VBITS_GE_512-NEXT: st1h { z0.h }, p1, [x0]84; VBITS_GE_512-NEXT: ret85 %op1 = load volatile <32 x half>, ptr %a86 %op2 = load volatile <32 x half>, ptr %b87 %sel = select i1 %mask, <32 x half> %op1, <32 x half> %op288 store <32 x half> %sel, ptr %a89 ret void90}91 92define void @select_v64f16(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 {93; CHECK-LABEL: select_v64f16:94; CHECK: // %bb.0:95; CHECK-NEXT: mov z0.h, w296; CHECK-NEXT: ptrue p0.h97; CHECK-NEXT: ptrue p1.h, vl6498; CHECK-NEXT: and z0.h, z0.h, #0x199; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0100; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0]101; CHECK-NEXT: ld1h { z1.h }, p1/z, [x1]102; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h103; CHECK-NEXT: st1h { z0.h }, p1, [x0]104; CHECK-NEXT: ret105 %op1 = load volatile <64 x half>, ptr %a106 %op2 = load volatile <64 x half>, ptr %b107 %sel = select i1 %mask, <64 x half> %op1, <64 x half> %op2108 store <64 x half> %sel, ptr %a109 ret void110}111 112define void @select_v128f16(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 {113; CHECK-LABEL: select_v128f16:114; CHECK: // %bb.0:115; CHECK-NEXT: mov z0.h, w2116; CHECK-NEXT: ptrue p0.h117; CHECK-NEXT: ptrue p1.h, vl128118; CHECK-NEXT: and z0.h, z0.h, #0x1119; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0120; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0]121; CHECK-NEXT: ld1h { z1.h }, p1/z, [x1]122; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h123; CHECK-NEXT: st1h { z0.h }, p1, [x0]124; CHECK-NEXT: ret125 %op1 = load volatile <128 x half>, ptr %a126 %op2 = load volatile <128 x half>, ptr %b127 %sel = select i1 %mask, <128 x half> %op1, <128 x half> %op2128 store <128 x half> %sel, ptr %a129 ret void130}131 132; Don't use SVE for 64-bit vectors.133define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, i1 %mask) vscale_range(2,0) #0 {134; CHECK-LABEL: select_v2f32:135; CHECK: // %bb.0:136; CHECK-NEXT: tst w0, #0x1137; CHECK-NEXT: csetm w8, ne138; CHECK-NEXT: dup v2.2s, w8139; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b140; CHECK-NEXT: ret141 %sel = select i1 %mask, <2 x float> %op1, <2 x float> %op2142 ret <2 x float> %sel143}144 145; Don't use SVE for 128-bit vectors.146define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, i1 %mask) vscale_range(2,0) #0 {147; CHECK-LABEL: select_v4f32:148; CHECK: // %bb.0:149; CHECK-NEXT: tst w0, #0x1150; CHECK-NEXT: csetm w8, ne151; CHECK-NEXT: dup v2.4s, w8152; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b153; CHECK-NEXT: ret154 %sel = select i1 %mask, <4 x float> %op1, <4 x float> %op2155 ret <4 x float> %sel156}157 158define void @select_v8f32(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 {159; CHECK-LABEL: select_v8f32:160; CHECK: // %bb.0:161; CHECK-NEXT: and w8, w2, #0x1162; CHECK-NEXT: ptrue p0.s163; CHECK-NEXT: mov z0.s, w8164; CHECK-NEXT: ptrue p1.s, vl8165; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0166; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]167; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]168; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s169; CHECK-NEXT: st1w { z0.s }, p1, [x0]170; CHECK-NEXT: ret171 %op1 = load volatile <8 x float>, ptr %a172 %op2 = load volatile <8 x float>, ptr %b173 %sel = select i1 %mask, <8 x float> %op1, <8 x float> %op2174 store <8 x float> %sel, ptr %a175 ret void176}177 178define void @select_v16f32(ptr %a, ptr %b, i1 %mask) #0 {179; VBITS_GE_256-LABEL: select_v16f32:180; VBITS_GE_256: // %bb.0:181; VBITS_GE_256-NEXT: and w8, w2, #0x1182; VBITS_GE_256-NEXT: ptrue p0.s183; VBITS_GE_256-NEXT: mov z0.s, w8184; VBITS_GE_256-NEXT: ptrue p1.s, vl8185; VBITS_GE_256-NEXT: mov x8, #8 // =0x8186; VBITS_GE_256-NEXT: cmpne p0.s, p0/z, z0.s, #0187; VBITS_GE_256-NEXT: ld1w { z0.s }, p1/z, [x0, x8, lsl #2]188; VBITS_GE_256-NEXT: ld1w { z1.s }, p1/z, [x0]189; VBITS_GE_256-NEXT: ld1w { z2.s }, p1/z, [x1, x8, lsl #2]190; VBITS_GE_256-NEXT: ld1w { z3.s }, p1/z, [x1]191; VBITS_GE_256-NEXT: sel z0.s, p0, z0.s, z2.s192; VBITS_GE_256-NEXT: sel z1.s, p0, z1.s, z3.s193; VBITS_GE_256-NEXT: st1w { z0.s }, p1, [x0, x8, lsl #2]194; VBITS_GE_256-NEXT: st1w { z1.s }, p1, [x0]195; VBITS_GE_256-NEXT: ret196;197; VBITS_GE_512-LABEL: select_v16f32:198; VBITS_GE_512: // %bb.0:199; VBITS_GE_512-NEXT: and w8, w2, #0x1200; VBITS_GE_512-NEXT: ptrue p0.s201; VBITS_GE_512-NEXT: mov z0.s, w8202; VBITS_GE_512-NEXT: ptrue p1.s, vl16203; VBITS_GE_512-NEXT: cmpne p0.s, p0/z, z0.s, #0204; VBITS_GE_512-NEXT: ld1w { z0.s }, p1/z, [x0]205; VBITS_GE_512-NEXT: ld1w { z1.s }, p1/z, [x1]206; VBITS_GE_512-NEXT: sel z0.s, p0, z0.s, z1.s207; VBITS_GE_512-NEXT: st1w { z0.s }, p1, [x0]208; VBITS_GE_512-NEXT: ret209 %op1 = load volatile <16 x float>, ptr %a210 %op2 = load volatile <16 x float>, ptr %b211 %sel = select i1 %mask, <16 x float> %op1, <16 x float> %op2212 store <16 x float> %sel, ptr %a213 ret void214}215 216define void @select_v32f32(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 {217; CHECK-LABEL: select_v32f32:218; CHECK: // %bb.0:219; CHECK-NEXT: and w8, w2, #0x1220; CHECK-NEXT: ptrue p0.s221; CHECK-NEXT: mov z0.s, w8222; CHECK-NEXT: ptrue p1.s, vl32223; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0224; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]225; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]226; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s227; CHECK-NEXT: st1w { z0.s }, p1, [x0]228; CHECK-NEXT: ret229 %op1 = load volatile <32 x float>, ptr %a230 %op2 = load volatile <32 x float>, ptr %b231 %sel = select i1 %mask, <32 x float> %op1, <32 x float> %op2232 store <32 x float> %sel, ptr %a233 ret void234}235 236define void @select_v64f32(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 {237; CHECK-LABEL: select_v64f32:238; CHECK: // %bb.0:239; CHECK-NEXT: and w8, w2, #0x1240; CHECK-NEXT: ptrue p0.s241; CHECK-NEXT: mov z0.s, w8242; CHECK-NEXT: ptrue p1.s, vl64243; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0244; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]245; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]246; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s247; CHECK-NEXT: st1w { z0.s }, p1, [x0]248; CHECK-NEXT: ret249 %op1 = load volatile <64 x float>, ptr %a250 %op2 = load volatile <64 x float>, ptr %b251 %sel = select i1 %mask, <64 x float> %op1, <64 x float> %op2252 store <64 x float> %sel, ptr %a253 ret void254}255 256; Don't use SVE for 64-bit vectors.257define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask) vscale_range(2,0) #0 {258; CHECK-LABEL: select_v1f64:259; CHECK: // %bb.0:260; CHECK-NEXT: tst w0, #0x1261; CHECK-NEXT: csetm x8, ne262; CHECK-NEXT: fmov d2, x8263; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b264; CHECK-NEXT: ret265 %sel = select i1 %mask, <1 x double> %op1, <1 x double> %op2266 ret <1 x double> %sel267}268 269; Don't use SVE for 128-bit vectors.270define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, i1 %mask) vscale_range(2,0) #0 {271; CHECK-LABEL: select_v2f64:272; CHECK: // %bb.0:273; CHECK-NEXT: tst w0, #0x1274; CHECK-NEXT: csetm x8, ne275; CHECK-NEXT: dup v2.2d, x8276; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b277; CHECK-NEXT: ret278 %sel = select i1 %mask, <2 x double> %op1, <2 x double> %op2279 ret <2 x double> %sel280}281 282define void @select_v4f64(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 {283; CHECK-LABEL: select_v4f64:284; CHECK: // %bb.0:285; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2286; CHECK-NEXT: and x8, x2, #0x1287; CHECK-NEXT: ptrue p0.d288; CHECK-NEXT: mov z0.d, x8289; CHECK-NEXT: ptrue p1.d, vl4290; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0291; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]292; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]293; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d294; CHECK-NEXT: st1d { z0.d }, p1, [x0]295; CHECK-NEXT: ret296 %op1 = load volatile <4 x double>, ptr %a297 %op2 = load volatile <4 x double>, ptr %b298 %sel = select i1 %mask, <4 x double> %op1, <4 x double> %op2299 store <4 x double> %sel, ptr %a300 ret void301}302 303define void @select_v8f64(ptr %a, ptr %b, i1 %mask) #0 {304; VBITS_GE_256-LABEL: select_v8f64:305; VBITS_GE_256: // %bb.0:306; VBITS_GE_256-NEXT: // kill: def $w2 killed $w2 def $x2307; VBITS_GE_256-NEXT: and x8, x2, #0x1308; VBITS_GE_256-NEXT: ptrue p0.d309; VBITS_GE_256-NEXT: mov z0.d, x8310; VBITS_GE_256-NEXT: ptrue p1.d, vl4311; VBITS_GE_256-NEXT: mov x8, #4 // =0x4312; VBITS_GE_256-NEXT: cmpne p0.d, p0/z, z0.d, #0313; VBITS_GE_256-NEXT: ld1d { z0.d }, p1/z, [x0, x8, lsl #3]314; VBITS_GE_256-NEXT: ld1d { z1.d }, p1/z, [x0]315; VBITS_GE_256-NEXT: ld1d { z2.d }, p1/z, [x1, x8, lsl #3]316; VBITS_GE_256-NEXT: ld1d { z3.d }, p1/z, [x1]317; VBITS_GE_256-NEXT: sel z0.d, p0, z0.d, z2.d318; VBITS_GE_256-NEXT: sel z1.d, p0, z1.d, z3.d319; VBITS_GE_256-NEXT: st1d { z0.d }, p1, [x0, x8, lsl #3]320; VBITS_GE_256-NEXT: st1d { z1.d }, p1, [x0]321; VBITS_GE_256-NEXT: ret322;323; VBITS_GE_512-LABEL: select_v8f64:324; VBITS_GE_512: // %bb.0:325; VBITS_GE_512-NEXT: // kill: def $w2 killed $w2 def $x2326; VBITS_GE_512-NEXT: and x8, x2, #0x1327; VBITS_GE_512-NEXT: ptrue p0.d328; VBITS_GE_512-NEXT: mov z0.d, x8329; VBITS_GE_512-NEXT: ptrue p1.d, vl8330; VBITS_GE_512-NEXT: cmpne p0.d, p0/z, z0.d, #0331; VBITS_GE_512-NEXT: ld1d { z0.d }, p1/z, [x0]332; VBITS_GE_512-NEXT: ld1d { z1.d }, p1/z, [x1]333; VBITS_GE_512-NEXT: sel z0.d, p0, z0.d, z1.d334; VBITS_GE_512-NEXT: st1d { z0.d }, p1, [x0]335; VBITS_GE_512-NEXT: ret336 %op1 = load volatile <8 x double>, ptr %a337 %op2 = load volatile <8 x double>, ptr %b338 %sel = select i1 %mask, <8 x double> %op1, <8 x double> %op2339 store <8 x double> %sel, ptr %a340 ret void341}342 343define void @select_v16f64(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 {344; CHECK-LABEL: select_v16f64:345; CHECK: // %bb.0:346; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2347; CHECK-NEXT: and x8, x2, #0x1348; CHECK-NEXT: ptrue p0.d349; CHECK-NEXT: mov z0.d, x8350; CHECK-NEXT: ptrue p1.d, vl16351; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0352; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]353; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]354; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d355; CHECK-NEXT: st1d { z0.d }, p1, [x0]356; CHECK-NEXT: ret357 %op1 = load volatile <16 x double>, ptr %a358 %op2 = load volatile <16 x double>, ptr %b359 %sel = select i1 %mask, <16 x double> %op1, <16 x double> %op2360 store <16 x double> %sel, ptr %a361 ret void362}363 364define void @select_v32f64(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 {365; CHECK-LABEL: select_v32f64:366; CHECK: // %bb.0:367; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2368; CHECK-NEXT: and x8, x2, #0x1369; CHECK-NEXT: ptrue p0.d370; CHECK-NEXT: mov z0.d, x8371; CHECK-NEXT: ptrue p1.d, vl32372; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0373; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]374; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]375; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d376; CHECK-NEXT: st1d { z0.d }, p1, [x0]377; CHECK-NEXT: ret378 %op1 = load volatile <32 x double>, ptr %a379 %op2 = load volatile <32 x double>, ptr %b380 %sel = select i1 %mask, <32 x double> %op1, <32 x double> %op2381 store <32 x double> %sel, ptr %a382 ret void383}384 385attributes #0 = { "target-features"="+sve" }386