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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8; Don't use SVE for 64-bit vectors.9define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x i1> %mask) vscale_range(2,0) #0 {10; CHECK-LABEL: select_v4f16:11; CHECK: // %bb.0:12; CHECK-NEXT: shl v2.4h, v2.4h, #1513; CHECK-NEXT: cmlt v2.4h, v2.4h, #014; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b15; CHECK-NEXT: ret16 %sel = select <4 x i1> %mask, <4 x half> %op1, <4 x half> %op217 ret <4 x half> %sel18}19 20; Don't use SVE for 128-bit vectors.21define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x i1> %mask) vscale_range(2,0) #0 {22; CHECK-LABEL: select_v8f16:23; CHECK: // %bb.0:24; CHECK-NEXT: ushll v2.8h, v2.8b, #025; CHECK-NEXT: shl v2.8h, v2.8h, #1526; CHECK-NEXT: cmlt v2.8h, v2.8h, #027; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b28; CHECK-NEXT: ret29 %sel = select <8 x i1> %mask, <8 x half> %op1, <8 x half> %op230 ret <8 x half> %sel31}32 33define void @select_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {34; CHECK-LABEL: select_v16f16:35; CHECK: // %bb.0:36; CHECK-NEXT: ptrue p0.h, vl1637; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]38; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]39; CHECK-NEXT: fcmne p0.h, p0/z, z0.h, z1.h40; CHECK-NEXT: st1h { z1.h }, p0, [x0]41; CHECK-NEXT: ret42 %op1 = load <16 x half>, ptr %a43 %op2 = load <16 x half>, ptr %b44 %mask = fcmp oeq <16 x half> %op1, %op245 %sel = select <16 x i1> %mask, <16 x half> %op1, <16 x half> %op246 store <16 x half> %sel, ptr %a47 ret void48}49 50define void @select_v32f16(ptr %a, ptr %b) #0 {51; VBITS_GE_256-LABEL: select_v32f16:52; VBITS_GE_256: // %bb.0:53; VBITS_GE_256-NEXT: ptrue p0.h, vl1654; VBITS_GE_256-NEXT: mov x8, #16 // =0x1055; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]56; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]57; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]58; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]59; VBITS_GE_256-NEXT: fcmne p1.h, p0/z, z0.h, z1.h60; VBITS_GE_256-NEXT: fcmne p0.h, p0/z, z2.h, z3.h61; VBITS_GE_256-NEXT: st1h { z1.h }, p1, [x0, x8, lsl #1]62; VBITS_GE_256-NEXT: st1h { z3.h }, p0, [x0]63; VBITS_GE_256-NEXT: ret64;65; VBITS_GE_512-LABEL: select_v32f16:66; VBITS_GE_512: // %bb.0:67; VBITS_GE_512-NEXT: ptrue p0.h, vl3268; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]69; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]70; VBITS_GE_512-NEXT: fcmne p0.h, p0/z, z0.h, z1.h71; VBITS_GE_512-NEXT: st1h { z1.h }, p0, [x0]72; VBITS_GE_512-NEXT: ret73 %op1 = load <32 x half>, ptr %a74 %op2 = load <32 x half>, ptr %b75 %mask = fcmp oeq <32 x half> %op1, %op276 %sel = select <32 x i1> %mask, <32 x half> %op1, <32 x half> %op277 store <32 x half> %sel, ptr %a78 ret void79}80 81define void @select_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 {82; CHECK-LABEL: select_v64f16:83; CHECK: // %bb.0:84; CHECK-NEXT: ptrue p0.h, vl6485; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]86; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]87; CHECK-NEXT: fcmne p0.h, p0/z, z0.h, z1.h88; CHECK-NEXT: st1h { z1.h }, p0, [x0]89; CHECK-NEXT: ret90 %op1 = load <64 x half>, ptr %a91 %op2 = load <64 x half>, ptr %b92 %mask = fcmp oeq <64 x half> %op1, %op293 %sel = select <64 x i1> %mask, <64 x half> %op1, <64 x half> %op294 store <64 x half> %sel, ptr %a95 ret void96}97 98define void @select_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 {99; CHECK-LABEL: select_v128f16:100; CHECK: // %bb.0:101; CHECK-NEXT: ptrue p0.h, vl128102; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]103; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]104; CHECK-NEXT: fcmne p0.h, p0/z, z0.h, z1.h105; CHECK-NEXT: st1h { z1.h }, p0, [x0]106; CHECK-NEXT: ret107 %op1 = load <128 x half>, ptr %a108 %op2 = load <128 x half>, ptr %b109 %mask = fcmp oeq <128 x half> %op1, %op2110 %sel = select <128 x i1> %mask, <128 x half> %op1, <128 x half> %op2111 store <128 x half> %sel, ptr %a112 ret void113}114 115; Don't use SVE for 64-bit vectors.116define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x i1> %mask) vscale_range(2,0) #0 {117; CHECK-LABEL: select_v2f32:118; CHECK: // %bb.0:119; CHECK-NEXT: shl v2.2s, v2.2s, #31120; CHECK-NEXT: cmlt v2.2s, v2.2s, #0121; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b122; CHECK-NEXT: ret123 %sel = select <2 x i1> %mask, <2 x float> %op1, <2 x float> %op2124 ret <2 x float> %sel125}126 127; Don't use SVE for 128-bit vectors.128define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x i1> %mask) vscale_range(2,0) #0 {129; CHECK-LABEL: select_v4f32:130; CHECK: // %bb.0:131; CHECK-NEXT: ushll v2.4s, v2.4h, #0132; CHECK-NEXT: shl v2.4s, v2.4s, #31133; CHECK-NEXT: cmlt v2.4s, v2.4s, #0134; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b135; CHECK-NEXT: ret136 %sel = select <4 x i1> %mask, <4 x float> %op1, <4 x float> %op2137 ret <4 x float> %sel138}139 140define void @select_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {141; CHECK-LABEL: select_v8f32:142; CHECK: // %bb.0:143; CHECK-NEXT: ptrue p0.s, vl8144; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]145; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]146; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, z1.s147; CHECK-NEXT: st1w { z1.s }, p0, [x0]148; CHECK-NEXT: ret149 %op1 = load <8 x float>, ptr %a150 %op2 = load <8 x float>, ptr %b151 %mask = fcmp oeq <8 x float> %op1, %op2152 %sel = select <8 x i1> %mask, <8 x float> %op1, <8 x float> %op2153 store <8 x float> %sel, ptr %a154 ret void155}156 157define void @select_v16f32(ptr %a, ptr %b) #0 {158; VBITS_GE_256-LABEL: select_v16f32:159; VBITS_GE_256: // %bb.0:160; VBITS_GE_256-NEXT: ptrue p0.s, vl8161; VBITS_GE_256-NEXT: mov x8, #8 // =0x8162; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]163; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]164; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]165; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]166; VBITS_GE_256-NEXT: fcmne p1.s, p0/z, z0.s, z1.s167; VBITS_GE_256-NEXT: fcmne p0.s, p0/z, z2.s, z3.s168; VBITS_GE_256-NEXT: st1w { z1.s }, p1, [x0, x8, lsl #2]169; VBITS_GE_256-NEXT: st1w { z3.s }, p0, [x0]170; VBITS_GE_256-NEXT: ret171;172; VBITS_GE_512-LABEL: select_v16f32:173; VBITS_GE_512: // %bb.0:174; VBITS_GE_512-NEXT: ptrue p0.s, vl16175; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]176; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]177; VBITS_GE_512-NEXT: fcmne p0.s, p0/z, z0.s, z1.s178; VBITS_GE_512-NEXT: st1w { z1.s }, p0, [x0]179; VBITS_GE_512-NEXT: ret180 %op1 = load <16 x float>, ptr %a181 %op2 = load <16 x float>, ptr %b182 %mask = fcmp oeq <16 x float> %op1, %op2183 %sel = select <16 x i1> %mask, <16 x float> %op1, <16 x float> %op2184 store <16 x float> %sel, ptr %a185 ret void186}187 188define void @select_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 {189; CHECK-LABEL: select_v32f32:190; CHECK: // %bb.0:191; CHECK-NEXT: ptrue p0.s, vl32192; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]193; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]194; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, z1.s195; CHECK-NEXT: st1w { z1.s }, p0, [x0]196; CHECK-NEXT: ret197 %op1 = load <32 x float>, ptr %a198 %op2 = load <32 x float>, ptr %b199 %mask = fcmp oeq <32 x float> %op1, %op2200 %sel = select <32 x i1> %mask, <32 x float> %op1, <32 x float> %op2201 store <32 x float> %sel, ptr %a202 ret void203}204 205define void @select_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 {206; CHECK-LABEL: select_v64f32:207; CHECK: // %bb.0:208; CHECK-NEXT: ptrue p0.s, vl64209; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]210; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]211; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, z1.s212; CHECK-NEXT: st1w { z1.s }, p0, [x0]213; CHECK-NEXT: ret214 %op1 = load <64 x float>, ptr %a215 %op2 = load <64 x float>, ptr %b216 %mask = fcmp oeq <64 x float> %op1, %op2217 %sel = select <64 x i1> %mask, <64 x float> %op1, <64 x float> %op2218 store <64 x float> %sel, ptr %a219 ret void220}221 222; Don't use SVE for 64-bit vectors.223define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1> %mask) vscale_range(2,0) #0 {224; CHECK-LABEL: select_v1f64:225; CHECK: // %bb.0:226; CHECK-NEXT: tst w0, #0x1227; CHECK-NEXT: csetm x8, ne228; CHECK-NEXT: fmov d2, x8229; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b230; CHECK-NEXT: ret231 %sel = select <1 x i1> %mask, <1 x double> %op1, <1 x double> %op2232 ret <1 x double> %sel233}234 235; Don't use SVE for 128-bit vectors.236define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x i1> %mask) vscale_range(2,0) #0 {237; CHECK-LABEL: select_v2f64:238; CHECK: // %bb.0:239; CHECK-NEXT: ushll v2.2d, v2.2s, #0240; CHECK-NEXT: shl v2.2d, v2.2d, #63241; CHECK-NEXT: cmlt v2.2d, v2.2d, #0242; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b243; CHECK-NEXT: ret244 %sel = select <2 x i1> %mask, <2 x double> %op1, <2 x double> %op2245 ret <2 x double> %sel246}247 248define void @select_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {249; CHECK-LABEL: select_v4f64:250; CHECK: // %bb.0:251; CHECK-NEXT: ptrue p0.d, vl4252; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]253; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]254; CHECK-NEXT: fcmne p0.d, p0/z, z0.d, z1.d255; CHECK-NEXT: st1d { z1.d }, p0, [x0]256; CHECK-NEXT: ret257 %op1 = load <4 x double>, ptr %a258 %op2 = load <4 x double>, ptr %b259 %mask = fcmp oeq <4 x double> %op1, %op2260 %sel = select <4 x i1> %mask, <4 x double> %op1, <4 x double> %op2261 store <4 x double> %sel, ptr %a262 ret void263}264 265define void @select_v8f64(ptr %a, ptr %b) #0 {266; VBITS_GE_256-LABEL: select_v8f64:267; VBITS_GE_256: // %bb.0:268; VBITS_GE_256-NEXT: ptrue p0.d, vl4269; VBITS_GE_256-NEXT: mov x8, #4 // =0x4270; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]271; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]272; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]273; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]274; VBITS_GE_256-NEXT: fcmne p1.d, p0/z, z0.d, z1.d275; VBITS_GE_256-NEXT: fcmne p0.d, p0/z, z2.d, z3.d276; VBITS_GE_256-NEXT: st1d { z1.d }, p1, [x0, x8, lsl #3]277; VBITS_GE_256-NEXT: st1d { z3.d }, p0, [x0]278; VBITS_GE_256-NEXT: ret279;280; VBITS_GE_512-LABEL: select_v8f64:281; VBITS_GE_512: // %bb.0:282; VBITS_GE_512-NEXT: ptrue p0.d, vl8283; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]284; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]285; VBITS_GE_512-NEXT: fcmne p0.d, p0/z, z0.d, z1.d286; VBITS_GE_512-NEXT: st1d { z1.d }, p0, [x0]287; VBITS_GE_512-NEXT: ret288 %op1 = load <8 x double>, ptr %a289 %op2 = load <8 x double>, ptr %b290 %mask = fcmp oeq <8 x double> %op1, %op2291 %sel = select <8 x i1> %mask, <8 x double> %op1, <8 x double> %op2292 store <8 x double> %sel, ptr %a293 ret void294}295 296define void @select_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {297; CHECK-LABEL: select_v16f64:298; CHECK: // %bb.0:299; CHECK-NEXT: ptrue p0.d, vl16300; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]301; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]302; CHECK-NEXT: fcmne p0.d, p0/z, z0.d, z1.d303; CHECK-NEXT: st1d { z1.d }, p0, [x0]304; CHECK-NEXT: ret305 %op1 = load <16 x double>, ptr %a306 %op2 = load <16 x double>, ptr %b307 %mask = fcmp oeq <16 x double> %op1, %op2308 %sel = select <16 x i1> %mask, <16 x double> %op1, <16 x double> %op2309 store <16 x double> %sel, ptr %a310 ret void311}312 313define void @select_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {314; CHECK-LABEL: select_v32f64:315; CHECK: // %bb.0:316; CHECK-NEXT: ptrue p0.d, vl32317; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]318; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]319; CHECK-NEXT: fcmne p0.d, p0/z, z0.d, z1.d320; CHECK-NEXT: st1d { z1.d }, p0, [x0]321; CHECK-NEXT: ret322 %op1 = load <32 x double>, ptr %a323 %op2 = load <32 x double>, ptr %b324 %mask = fcmp oeq <32 x double> %op1, %op2325 %sel = select <32 x i1> %mask, <32 x double> %op1, <32 x double> %op2326 store <32 x double> %sel, ptr %a327 ret void328}329 330attributes #0 = { "target-features"="+sve" }331