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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -debug-only=isel < %s 2>&1 | FileCheck %s3 4; REQUIRES: asserts5 6target triple = "aarch64-unknown-linux-gnu"7 8; Ensure that only no offset frame indexes are folded into SVE load/stores when9; accessing fixed width objects.10define void @foo(ptr %a) #0 {11; CHECK-LABEL: foo:12; CHECK: SelectionDAG has 13 nodes:13; CHECK-NEXT: t0: ch,glue = EntryToken14; CHECK-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %015; CHECK-NEXT: t21: nxv2i64,ch = LDR_ZXI<Mem:(volatile load (<vscale x 1 x s128>) from %ir.a, align 64)> t2, TargetConstant:i64<0>, t016; CHECK-NEXT: t8: i64 = ADDXri TargetFrameIndex:i64<1>, TargetConstant:i32<0>, TargetConstant:i32<0>17; CHECK-NEXT: t6: i64 = ADDXri TargetFrameIndex:i64<0>, TargetConstant:i32<0>, TargetConstant:i32<0>18; CHECK-NEXT: t22: ch = STR_ZXI<Mem:(volatile store (<vscale x 1 x s128>) into %ir.r0, align 64)> t21, t6, TargetConstant:i64<0>, t21:119; CHECK-NEXT: t23: ch = STR_ZXI<Mem:(volatile store (<vscale x 1 x s128>) into %ir.r1, align 64)> t21, t8, TargetConstant:i64<0>, t2220; CHECK-NEXT: t10: ch = RET_ReallyLR t2321; CHECK-EMPTY:22entry:23 %r0 = alloca <8 x i64>24 %r1 = alloca <8 x i64>25 %r = load volatile <8 x i64>, ptr %a26 store volatile <8 x i64> %r, ptr %r027 store volatile <8 x i64> %r, ptr %r128 ret void29}30 31attributes #0 = { nounwind "target-features"="+sve" vscale_range(4,4) }32