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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s | FileCheck %s3; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s4; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s5 6target triple = "aarch64-unknown-linux-gnu"7 8declare void @foo_v32i8(<32 x i8>)9define void @test_v32i8(<32 x i8> %unused, <32 x i8> %a) #0 {10; CHECK-LABEL: test_v32i8:11; CHECK: // %bb.0:12; CHECK-NEXT: mov v1.16b, v3.16b13; CHECK-NEXT: mov v0.16b, v2.16b14; CHECK-NEXT: b foo_v32i815 tail call void @foo_v32i8(<32 x i8> %a)16 ret void17}18 19declare void @foo_v16i16(<16 x i16>)20define void @test_v16i16(<16 x i16> %unused, <16 x i16> %a) #0 {21; CHECK-LABEL: test_v16i16:22; CHECK: // %bb.0:23; CHECK-NEXT: mov v1.16b, v3.16b24; CHECK-NEXT: mov v0.16b, v2.16b25; CHECK-NEXT: b foo_v16i1626 tail call void @foo_v16i16(<16 x i16> %a)27 ret void28}29 30declare void @foo_v8i32(<8 x i32>)31define void @test_v8i32(<8 x i32> %unused, <8 x i32> %a) #0 {32; CHECK-LABEL: test_v8i32:33; CHECK: // %bb.0:34; CHECK-NEXT: mov v1.16b, v3.16b35; CHECK-NEXT: mov v0.16b, v2.16b36; CHECK-NEXT: b foo_v8i3237 tail call void @foo_v8i32(<8 x i32> %a)38 ret void39}40 41declare void @foo_v4i64(<4 x i64>)42define void @test_v4i64(<4 x i64> %unused, <4 x i64> %a) #0 {43; CHECK-LABEL: test_v4i64:44; CHECK: // %bb.0:45; CHECK-NEXT: mov v1.16b, v3.16b46; CHECK-NEXT: mov v0.16b, v2.16b47; CHECK-NEXT: b foo_v4i6448 tail call void @foo_v4i64(<4 x i64> %a)49 ret void50}51 52declare void @foo_v16f16(<16 x half>)53define void @test_v16f16(<16 x half> %unused, <16 x half> %a) #0 {54; CHECK-LABEL: test_v16f16:55; CHECK: // %bb.0:56; CHECK-NEXT: mov v1.16b, v3.16b57; CHECK-NEXT: mov v0.16b, v2.16b58; CHECK-NEXT: b foo_v16f1659 tail call void @foo_v16f16(<16 x half> %a)60 ret void61}62 63declare void @foo_v8f32(<8 x float>)64define void @test_v8f32(<8 x float> %unused, <8 x float> %a) #0 {65; CHECK-LABEL: test_v8f32:66; CHECK: // %bb.0:67; CHECK-NEXT: mov v1.16b, v3.16b68; CHECK-NEXT: mov v0.16b, v2.16b69; CHECK-NEXT: b foo_v8f3270 tail call void @foo_v8f32(<8 x float> %a)71 ret void72}73 74declare void @foo_v4f64(<4 x double>)75define void @test_v4f64(<4 x double> %unused, <4 x double> %a) #0 {76; CHECK-LABEL: test_v4f64:77; CHECK: // %bb.0:78; CHECK-NEXT: mov v1.16b, v3.16b79; CHECK-NEXT: mov v0.16b, v2.16b80; CHECK-NEXT: b foo_v4f6481 tail call void @foo_v4f64(<4 x double> %a)82 ret void83}84 85declare void @foo_v16bf16(<16 x bfloat>)86define void @test_v16bf16(<16 x bfloat> %unused, <16 x bfloat> %a) #0 {87; CHECK-LABEL: test_v16bf16:88; CHECK: // %bb.0:89; CHECK-NEXT: mov v1.16b, v3.16b90; CHECK-NEXT: mov v0.16b, v2.16b91; CHECK-NEXT: b foo_v16bf1692 tail call void @foo_v16bf16(<16 x bfloat> %a)93 ret void94}95 96declare void @foo_v3i64(<3 x i64>)97define void @test_v3i64(<3 x i64> %unused, <3 x i64> %a) #0 {98; CHECK-LABEL: test_v3i64:99; CHECK: // %bb.0:100; CHECK-NEXT: fmov d2, d5101; CHECK-NEXT: fmov d1, d4102; CHECK-NEXT: fmov d0, d3103; CHECK-NEXT: b foo_v3i64104 tail call void @foo_v3i64(<3 x i64> %a)105 ret void106}107 108declare void @foo_v5i64(<5 x i64>)109define void @test_v5i64(<5 x i64> %unused, <5 x i64> %a) #0 {110; CHECK-LABEL: test_v5i64:111; CHECK: // %bb.0:112; CHECK-NEXT: fmov d1, d6113; CHECK-NEXT: fmov d0, d5114; CHECK-NEXT: fmov d2, d7115; CHECK-NEXT: ldp d3, d4, [sp]116; CHECK-NEXT: b foo_v5i64117 tail call void @foo_v5i64(<5 x i64> %a)118 ret void119}120 121declare void @foo_v1i16(<1 x i16>)122define void @test_v1i16(<1 x i16> %unused, <1 x i16> %a) #0 {123; CHECK-LABEL: test_v1i16:124; CHECK: // %bb.0:125; CHECK-NEXT: fmov d0, d1126; CHECK-NEXT: b foo_v1i16127 tail call void @foo_v1i16(<1 x i16> %a)128 ret void129}130 131declare void @foo_v9i16(<9 x i16>)132define void @test_v9i16(<9 x i16> %unused, <9 x i16> %a) #0 {133; CHECK-LABEL: test_v9i16:134; CHECK: // %bb.0:135; CHECK-NEXT: ldr w0, [sp, #8]136; CHECK-NEXT: ldr w1, [sp, #16]137; CHECK-NEXT: ldr w2, [sp, #24]138; CHECK-NEXT: ldr w3, [sp, #32]139; CHECK-NEXT: ldr w4, [sp, #40]140; CHECK-NEXT: ldr w5, [sp, #48]141; CHECK-NEXT: ldr w6, [sp, #56]142; CHECK-NEXT: ldr w7, [sp, #64]143; CHECK-NEXT: ldr w8, [sp, #72]144; CHECK-NEXT: str w8, [sp]145; CHECK-NEXT: b foo_v9i16146 tail call void @foo_v9i16(<9 x i16> %a)147 ret void148}149 150declare void @foo_v16i1(<16 x i1>)151define void @test_v16i1(<16 x i1> %unused, <16 x i1> %a) #0 {152; CHECK-LABEL: test_v16i1:153; CHECK: // %bb.0:154; CHECK-NEXT: mov v0.16b, v1.16b155; CHECK-NEXT: b foo_v16i1156 tail call void @foo_v16i1(<16 x i1> %a)157 ret void158}159 160; UTC_ARGS: --disable161; The output from this test is large and generally not useful, what matters is162; no vector registers are used.163declare void @foo_v32i1(<32 x i1>)164define void @test_v32i1(<32 x i1> %unused, <32 x i1> %a) #0 {165; CHECK-LABEL: test_v32i1:166; CHECK: // %bb.0:167; CHECK-NOT: [q,v,z][0-9]+168; CHECK: b foo_v32i1169 tail call void @foo_v32i1(<32 x i1> %a)170 ret void171}172; UTC_ARGS: --enable173 174declare void @foo_v1i128(<1 x i128>)175define void @test_v1i128(<1 x i128> %unused, <1 x i128> %a) #0 {176; CHECK-LABEL: test_v1i128:177; CHECK: // %bb.0:178; CHECK-NEXT: mov x1, x3179; CHECK-NEXT: mov x0, x2180; CHECK-NEXT: b foo_v1i128181 tail call void @foo_v1i128(<1 x i128> %a)182 ret void183}184 185declare void @foo_v2i128(<2 x i128>)186define void @test_v2i128(<2 x i128> %unused, <2 x i128> %a) #0 {187; CHECK-LABEL: test_v2i128:188; CHECK: // %bb.0:189; CHECK-NEXT: mov x3, x7190; CHECK-NEXT: mov x2, x6191; CHECK-NEXT: mov x0, x4192; CHECK-NEXT: mov x1, x5193; CHECK-NEXT: b foo_v2i128194 tail call void @foo_v2i128(<2 x i128> %a)195 ret void196}197 198declare void @foo_v1i256(<1 x i256>)199define void @test_v1i256(<1 x i256> %unused, <1 x i256> %a) #0 {200; CHECK-LABEL: test_v1i256:201; CHECK: // %bb.0:202; CHECK-NEXT: mov x3, x7203; CHECK-NEXT: mov x2, x6204; CHECK-NEXT: mov x0, x4205; CHECK-NEXT: mov x1, x5206; CHECK-NEXT: b foo_v1i256207 tail call void @foo_v1i256(<1 x i256> %a)208 ret void209}210 211declare void @foo_v2i256(<2 x i256>)212define void @test_v2i256(<2 x i256> %unused, <2 x i256> %a) #0 {213; CHECK-LABEL: test_v2i256:214; CHECK: // %bb.0:215; CHECK-NEXT: ldp x0, x1, [sp]216; CHECK-NEXT: ldp x2, x3, [sp, #16]217; CHECK-NEXT: ldp x4, x5, [sp, #32]218; CHECK-NEXT: ldp x6, x7, [sp, #48]219; CHECK-NEXT: b foo_v2i256220 tail call void @foo_v2i256(<2 x i256> %a)221 ret void222}223 224declare void @foo_v1f128(<1 x fp128>)225define void @test_v1f128(<1 x fp128> %unused, <1 x fp128> %a) #0 {226; CHECK-LABEL: test_v1f128:227; CHECK: // %bb.0:228; CHECK-NEXT: mov v0.16b, v1.16b229; CHECK-NEXT: b foo_v1f128230 tail call void @foo_v1f128(<1 x fp128> %a)231 ret void232}233 234declare void @foo_v2f128(<2 x fp128>)235define void @test_v2f128(<2 x fp128> %unused, <2 x fp128> %a) #0 {236; CHECK-LABEL: test_v2f128:237; CHECK: // %bb.0:238; CHECK-NEXT: mov v1.16b, v3.16b239; CHECK-NEXT: mov v0.16b, v2.16b240; CHECK-NEXT: b foo_v2f128241 tail call void @foo_v2f128(<2 x fp128> %a)242 ret void243}244 245attributes #0 = { "target-features"="+sve,+bf16" nounwind }246