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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; insertelement10;11 12; Don't use SVE for 64-bit vectors.13define <4 x half> @insertelement_v4f16(<4 x half> %op1) vscale_range(2,0) #0 {14; CHECK-LABEL: insertelement_v4f16:15; CHECK: // %bb.0:16; CHECK-NEXT: fmov h1, #5.0000000017; CHECK-NEXT: // kill: def $d0 killed $d0 def $q018; CHECK-NEXT: mov v0.h[3], v1.h[0]19; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q020; CHECK-NEXT: ret21 %r = insertelement <4 x half> %op1, half 5.0, i64 322 ret <4 x half> %r23}24 25; Don't use SVE for 128-bit vectors.26define <8 x half> @insertelement_v8f16(<8 x half> %op1) vscale_range(2,0) #0 {27; CHECK-LABEL: insertelement_v8f16:28; CHECK: // %bb.0:29; CHECK-NEXT: fmov h1, #5.0000000030; CHECK-NEXT: mov v0.h[7], v1.h[0]31; CHECK-NEXT: ret32 %r = insertelement <8 x half> %op1, half 5.0, i64 733 ret <8 x half> %r34}35 36define void @insertelement_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {37; CHECK-LABEL: insertelement_v16f16:38; CHECK: // %bb.0:39; CHECK-NEXT: mov w8, #15 // =0xf40; CHECK-NEXT: index z0.h, #0, #141; CHECK-NEXT: ptrue p0.h42; CHECK-NEXT: mov z1.h, w843; CHECK-NEXT: ptrue p1.h, vl1644; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h45; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0]46; CHECK-NEXT: fmov h1, #5.0000000047; CHECK-NEXT: mov z0.h, p0/m, h148; CHECK-NEXT: st1h { z0.h }, p1, [x1]49; CHECK-NEXT: ret50 %op1 = load <16 x half>, ptr %a51 %r = insertelement <16 x half> %op1, half 5.0, i64 1552 store <16 x half> %r, ptr %b53 ret void54}55 56define void @insertelement_v32f16(ptr %a, ptr %b) #0 {57; VBITS_GE_256-LABEL: insertelement_v32f16:58; VBITS_GE_256: // %bb.0:59; VBITS_GE_256-NEXT: mov w8, #15 // =0xf60; VBITS_GE_256-NEXT: index z0.h, #0, #161; VBITS_GE_256-NEXT: ptrue p0.h62; VBITS_GE_256-NEXT: mov z1.h, w863; VBITS_GE_256-NEXT: ptrue p1.h, vl1664; VBITS_GE_256-NEXT: mov x8, #16 // =0x1065; VBITS_GE_256-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h66; VBITS_GE_256-NEXT: fmov h0, #5.0000000067; VBITS_GE_256-NEXT: ld1h { z1.h }, p1/z, [x0, x8, lsl #1]68; VBITS_GE_256-NEXT: mov z1.h, p0/m, h069; VBITS_GE_256-NEXT: ld1h { z0.h }, p1/z, [x0]70; VBITS_GE_256-NEXT: st1h { z1.h }, p1, [x1, x8, lsl #1]71; VBITS_GE_256-NEXT: st1h { z0.h }, p1, [x1]72; VBITS_GE_256-NEXT: ret73;74; VBITS_GE_512-LABEL: insertelement_v32f16:75; VBITS_GE_512: // %bb.0:76; VBITS_GE_512-NEXT: mov w8, #31 // =0x1f77; VBITS_GE_512-NEXT: index z0.h, #0, #178; VBITS_GE_512-NEXT: ptrue p0.h79; VBITS_GE_512-NEXT: mov z1.h, w880; VBITS_GE_512-NEXT: ptrue p1.h, vl3281; VBITS_GE_512-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h82; VBITS_GE_512-NEXT: ld1h { z0.h }, p1/z, [x0]83; VBITS_GE_512-NEXT: fmov h1, #5.0000000084; VBITS_GE_512-NEXT: mov z0.h, p0/m, h185; VBITS_GE_512-NEXT: st1h { z0.h }, p1, [x1]86; VBITS_GE_512-NEXT: ret87 %op1 = load <32 x half>, ptr %a88 %r = insertelement <32 x half> %op1, half 5.0, i64 3189 store <32 x half> %r, ptr %b90 ret void91}92 93define void @insertelement_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 {94; CHECK-LABEL: insertelement_v64f16:95; CHECK: // %bb.0:96; CHECK-NEXT: mov w8, #63 // =0x3f97; CHECK-NEXT: index z0.h, #0, #198; CHECK-NEXT: ptrue p0.h99; CHECK-NEXT: mov z1.h, w8100; CHECK-NEXT: ptrue p1.h, vl64101; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h102; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0]103; CHECK-NEXT: fmov h1, #5.00000000104; CHECK-NEXT: mov z0.h, p0/m, h1105; CHECK-NEXT: st1h { z0.h }, p1, [x1]106; CHECK-NEXT: ret107 %op1 = load <64 x half>, ptr %a108 %r = insertelement <64 x half> %op1, half 5.0, i64 63109 store <64 x half> %r, ptr %b110 ret void111}112 113define void @insertelement_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 {114; CHECK-LABEL: insertelement_v128f16:115; CHECK: // %bb.0:116; CHECK-NEXT: mov w8, #127 // =0x7f117; CHECK-NEXT: index z0.h, #0, #1118; CHECK-NEXT: ptrue p0.h119; CHECK-NEXT: mov z1.h, w8120; CHECK-NEXT: ptrue p1.h, vl128121; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h122; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0]123; CHECK-NEXT: fmov h1, #5.00000000124; CHECK-NEXT: mov z0.h, p0/m, h1125; CHECK-NEXT: st1h { z0.h }, p1, [x1]126; CHECK-NEXT: ret127 %op1 = load <128 x half>, ptr %a128 %r = insertelement <128 x half> %op1, half 5.0, i64 127129 store <128 x half> %r, ptr %b130 ret void131}132 133; Don't use SVE for 64-bit vectors.134define <2 x float> @insertelement_v2f32(<2 x float> %op1) vscale_range(2,0) #0 {135; CHECK-LABEL: insertelement_v2f32:136; CHECK: // %bb.0:137; CHECK-NEXT: fmov s1, #5.00000000138; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0139; CHECK-NEXT: mov v0.s[1], v1.s[0]140; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0141; CHECK-NEXT: ret142 %r = insertelement <2 x float> %op1, float 5.0, i64 1143 ret <2 x float> %r144}145 146; Don't use SVE for 128-bit vectors.147define <4 x float> @insertelement_v4f32(<4 x float> %op1) vscale_range(2,0) #0 {148; CHECK-LABEL: insertelement_v4f32:149; CHECK: // %bb.0:150; CHECK-NEXT: fmov s1, #5.00000000151; CHECK-NEXT: mov v0.s[3], v1.s[0]152; CHECK-NEXT: ret153 %r = insertelement <4 x float> %op1, float 5.0, i64 3154 ret <4 x float> %r155}156 157define void @insertelement_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {158; CHECK-LABEL: insertelement_v8f32:159; CHECK: // %bb.0:160; CHECK-NEXT: mov w8, #7 // =0x7161; CHECK-NEXT: index z0.s, #0, #1162; CHECK-NEXT: ptrue p0.s163; CHECK-NEXT: mov z1.s, w8164; CHECK-NEXT: ptrue p1.s, vl8165; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s166; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]167; CHECK-NEXT: fmov s1, #5.00000000168; CHECK-NEXT: mov z0.s, p0/m, s1169; CHECK-NEXT: st1w { z0.s }, p1, [x1]170; CHECK-NEXT: ret171 %op1 = load <8 x float>, ptr %a172 %r = insertelement <8 x float> %op1, float 5.0, i64 7173 store <8 x float> %r, ptr %b174 ret void175}176 177define void @insertelement_v16f32(ptr %a, ptr %b) #0 {178; VBITS_GE_256-LABEL: insertelement_v16f32:179; VBITS_GE_256: // %bb.0:180; VBITS_GE_256-NEXT: mov w8, #7 // =0x7181; VBITS_GE_256-NEXT: index z0.s, #0, #1182; VBITS_GE_256-NEXT: ptrue p0.s183; VBITS_GE_256-NEXT: mov z1.s, w8184; VBITS_GE_256-NEXT: ptrue p1.s, vl8185; VBITS_GE_256-NEXT: mov x8, #8 // =0x8186; VBITS_GE_256-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s187; VBITS_GE_256-NEXT: fmov s0, #5.00000000188; VBITS_GE_256-NEXT: ld1w { z1.s }, p1/z, [x0, x8, lsl #2]189; VBITS_GE_256-NEXT: mov z1.s, p0/m, s0190; VBITS_GE_256-NEXT: ld1w { z0.s }, p1/z, [x0]191; VBITS_GE_256-NEXT: st1w { z1.s }, p1, [x1, x8, lsl #2]192; VBITS_GE_256-NEXT: st1w { z0.s }, p1, [x1]193; VBITS_GE_256-NEXT: ret194;195; VBITS_GE_512-LABEL: insertelement_v16f32:196; VBITS_GE_512: // %bb.0:197; VBITS_GE_512-NEXT: mov w8, #15 // =0xf198; VBITS_GE_512-NEXT: index z0.s, #0, #1199; VBITS_GE_512-NEXT: ptrue p0.s200; VBITS_GE_512-NEXT: mov z1.s, w8201; VBITS_GE_512-NEXT: ptrue p1.s, vl16202; VBITS_GE_512-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s203; VBITS_GE_512-NEXT: ld1w { z0.s }, p1/z, [x0]204; VBITS_GE_512-NEXT: fmov s1, #5.00000000205; VBITS_GE_512-NEXT: mov z0.s, p0/m, s1206; VBITS_GE_512-NEXT: st1w { z0.s }, p1, [x1]207; VBITS_GE_512-NEXT: ret208 %op1 = load <16 x float>, ptr %a209 %r = insertelement <16 x float> %op1, float 5.0, i64 15210 store <16 x float> %r, ptr %b211 ret void212}213 214define void @insertelement_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 {215; CHECK-LABEL: insertelement_v32f32:216; CHECK: // %bb.0:217; CHECK-NEXT: mov w8, #31 // =0x1f218; CHECK-NEXT: index z0.s, #0, #1219; CHECK-NEXT: ptrue p0.s220; CHECK-NEXT: mov z1.s, w8221; CHECK-NEXT: ptrue p1.s, vl32222; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s223; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]224; CHECK-NEXT: fmov s1, #5.00000000225; CHECK-NEXT: mov z0.s, p0/m, s1226; CHECK-NEXT: st1w { z0.s }, p1, [x1]227; CHECK-NEXT: ret228 %op1 = load <32 x float>, ptr %a229 %r = insertelement <32 x float> %op1, float 5.0, i64 31230 store <32 x float> %r, ptr %b231 ret void232}233 234define void @insertelement_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 {235; CHECK-LABEL: insertelement_v64f32:236; CHECK: // %bb.0:237; CHECK-NEXT: mov w8, #63 // =0x3f238; CHECK-NEXT: index z0.s, #0, #1239; CHECK-NEXT: ptrue p0.s240; CHECK-NEXT: mov z1.s, w8241; CHECK-NEXT: ptrue p1.s, vl64242; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s243; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]244; CHECK-NEXT: fmov s1, #5.00000000245; CHECK-NEXT: mov z0.s, p0/m, s1246; CHECK-NEXT: st1w { z0.s }, p1, [x1]247; CHECK-NEXT: ret248 %op1 = load <64 x float>, ptr %a249 %r = insertelement <64 x float> %op1, float 5.0, i64 63250 store <64 x float> %r, ptr %b251 ret void252}253 254; Don't use SVE for 64-bit vectors.255define <1 x double> @insertelement_v1f64(<1 x double> %op1) vscale_range(2,0) #0 {256; CHECK-LABEL: insertelement_v1f64:257; CHECK: // %bb.0:258; CHECK-NEXT: mov x8, #4617315517961601024 // =0x4014000000000000259; CHECK-NEXT: fmov d0, x8260; CHECK-NEXT: ret261 %r = insertelement <1 x double> %op1, double 5.0, i64 0262 ret <1 x double> %r263}264 265; Don't use SVE for 128-bit vectors.266define <2 x double> @insertelement_v2f64(<2 x double> %op1) vscale_range(2,0) #0 {267; CHECK-LABEL: insertelement_v2f64:268; CHECK: // %bb.0:269; CHECK-NEXT: fmov d1, #5.00000000270; CHECK-NEXT: mov v0.d[1], v1.d[0]271; CHECK-NEXT: ret272 %r = insertelement <2 x double> %op1, double 5.0, i64 1273 ret <2 x double> %r274}275 276define void @insertelement_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {277; CHECK-LABEL: insertelement_v4f64:278; CHECK: // %bb.0:279; CHECK-NEXT: mov w8, #3 // =0x3280; CHECK-NEXT: index z0.d, #0, #1281; CHECK-NEXT: ptrue p0.d282; CHECK-NEXT: mov z1.d, x8283; CHECK-NEXT: ptrue p1.d, vl4284; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d285; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]286; CHECK-NEXT: fmov d1, #5.00000000287; CHECK-NEXT: mov z0.d, p0/m, d1288; CHECK-NEXT: st1d { z0.d }, p1, [x1]289; CHECK-NEXT: ret290 %op1 = load <4 x double>, ptr %a291 %r = insertelement <4 x double> %op1, double 5.0, i64 3292 store <4 x double> %r, ptr %b293 ret void294}295 296define void @insertelement_v8f64(ptr %a, ptr %b) #0 {297; VBITS_GE_256-LABEL: insertelement_v8f64:298; VBITS_GE_256: // %bb.0:299; VBITS_GE_256-NEXT: mov w8, #3 // =0x3300; VBITS_GE_256-NEXT: index z0.d, #0, #1301; VBITS_GE_256-NEXT: ptrue p0.d302; VBITS_GE_256-NEXT: mov z1.d, x8303; VBITS_GE_256-NEXT: ptrue p1.d, vl4304; VBITS_GE_256-NEXT: mov x8, #4 // =0x4305; VBITS_GE_256-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d306; VBITS_GE_256-NEXT: fmov d0, #5.00000000307; VBITS_GE_256-NEXT: ld1d { z1.d }, p1/z, [x0, x8, lsl #3]308; VBITS_GE_256-NEXT: mov z1.d, p0/m, d0309; VBITS_GE_256-NEXT: ld1d { z0.d }, p1/z, [x0]310; VBITS_GE_256-NEXT: st1d { z1.d }, p1, [x1, x8, lsl #3]311; VBITS_GE_256-NEXT: st1d { z0.d }, p1, [x1]312; VBITS_GE_256-NEXT: ret313;314; VBITS_GE_512-LABEL: insertelement_v8f64:315; VBITS_GE_512: // %bb.0:316; VBITS_GE_512-NEXT: mov w8, #7 // =0x7317; VBITS_GE_512-NEXT: index z0.d, #0, #1318; VBITS_GE_512-NEXT: ptrue p0.d319; VBITS_GE_512-NEXT: mov z1.d, x8320; VBITS_GE_512-NEXT: ptrue p1.d, vl8321; VBITS_GE_512-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d322; VBITS_GE_512-NEXT: ld1d { z0.d }, p1/z, [x0]323; VBITS_GE_512-NEXT: fmov d1, #5.00000000324; VBITS_GE_512-NEXT: mov z0.d, p0/m, d1325; VBITS_GE_512-NEXT: st1d { z0.d }, p1, [x1]326; VBITS_GE_512-NEXT: ret327 %op1 = load <8 x double>, ptr %a328 %r = insertelement <8 x double> %op1, double 5.0, i64 7329 store <8 x double> %r, ptr %b330 ret void331}332 333define void @insertelement_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {334; CHECK-LABEL: insertelement_v16f64:335; CHECK: // %bb.0:336; CHECK-NEXT: mov w8, #15 // =0xf337; CHECK-NEXT: index z0.d, #0, #1338; CHECK-NEXT: ptrue p0.d339; CHECK-NEXT: mov z1.d, x8340; CHECK-NEXT: ptrue p1.d, vl16341; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d342; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]343; CHECK-NEXT: fmov d1, #5.00000000344; CHECK-NEXT: mov z0.d, p0/m, d1345; CHECK-NEXT: st1d { z0.d }, p1, [x1]346; CHECK-NEXT: ret347 %op1 = load <16 x double>, ptr %a348 %r = insertelement <16 x double> %op1, double 5.0, i64 15349 store <16 x double> %r, ptr %b350 ret void351}352 353define void @insertelement_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {354; CHECK-LABEL: insertelement_v32f64:355; CHECK: // %bb.0:356; CHECK-NEXT: mov w8, #31 // =0x1f357; CHECK-NEXT: index z0.d, #0, #1358; CHECK-NEXT: ptrue p0.d359; CHECK-NEXT: mov z1.d, x8360; CHECK-NEXT: ptrue p1.d, vl32361; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d362; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]363; CHECK-NEXT: fmov d1, #5.00000000364; CHECK-NEXT: mov z0.d, p0/m, d1365; CHECK-NEXT: st1d { z0.d }, p1, [x1]366; CHECK-NEXT: ret367 %op1 = load <32 x double>, ptr %a368 %r = insertelement <32 x double> %op1, double 5.0, i64 31369 store <32 x double> %r, ptr %b370 ret void371}372 373attributes #0 = { "target-features"="+sve" }374