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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8; Don't use SVE for 128-bit vectors.9define void @sabd_v16i8_v16i16(ptr %a, ptr %b) #0 {10; CHECK-LABEL: sabd_v16i8_v16i16:11; CHECK: // %bb.0:12; CHECK-NEXT: ldr q0, [x0]13; CHECK-NEXT: ldr q1, [x1]14; CHECK-NEXT: sabd v0.16b, v0.16b, v1.16b15; CHECK-NEXT: str q0, [x0]16; CHECK-NEXT: ret17 %a.ld = load <16 x i8>, ptr %a18 %b.ld = load <16 x i8>, ptr %b19 %a.sext = sext <16 x i8> %a.ld to <16 x i16>20 %b.sext = sext <16 x i8> %b.ld to <16 x i16>21 %sub = sub <16 x i16> %a.sext, %b.sext22 %abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true)23 %trunc = trunc <16 x i16> %abs to <16 x i8>24 store <16 x i8> %trunc, ptr %a25 ret void26}27 28; Don't use SVE for 128-bit vectors.29define void @sabd_v16i8_v16i32(ptr %a, ptr %b) #0 {30; CHECK-LABEL: sabd_v16i8_v16i32:31; CHECK: // %bb.0:32; CHECK-NEXT: ldr q0, [x0]33; CHECK-NEXT: ldr q1, [x1]34; CHECK-NEXT: sabd v0.16b, v0.16b, v1.16b35; CHECK-NEXT: str q0, [x0]36; CHECK-NEXT: ret37 %a.ld = load <16 x i8>, ptr %a38 %b.ld = load <16 x i8>, ptr %b39 %a.sext = sext <16 x i8> %a.ld to <16 x i32>40 %b.sext = sext <16 x i8> %b.ld to <16 x i32>41 %sub = sub <16 x i32> %a.sext, %b.sext42 %abs = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %sub, i1 true)43 %trunc = trunc <16 x i32> %abs to <16 x i8>44 store <16 x i8> %trunc, ptr %a45 ret void46}47 48; Don't use SVE for 128-bit vectors.49define void @sabd_v16i8_v16i64(ptr %a, ptr %b) #0 {50; CHECK-LABEL: sabd_v16i8_v16i64:51; CHECK: // %bb.0:52; CHECK-NEXT: ldr q0, [x0]53; CHECK-NEXT: ldr q1, [x1]54; CHECK-NEXT: sabd v0.16b, v0.16b, v1.16b55; CHECK-NEXT: str q0, [x0]56; CHECK-NEXT: ret57 %a.ld = load <16 x i8>, ptr %a58 %b.ld = load <16 x i8>, ptr %b59 %a.sext = sext <16 x i8> %a.ld to <16 x i64>60 %b.sext = sext <16 x i8> %b.ld to <16 x i64>61 %sub = sub <16 x i64> %a.sext, %b.sext62 %abs = call <16 x i64> @llvm.abs.v16i64(<16 x i64> %sub, i1 true)63 %trunc = trunc <16 x i64> %abs to <16 x i8>64 store <16 x i8> %trunc, ptr %a65 ret void66}67 68define void @sabd_v32i8_v32i16(ptr %a, ptr %b) #0 {69; CHECK-LABEL: sabd_v32i8_v32i16:70; CHECK: // %bb.0:71; CHECK-NEXT: ptrue p0.b, vl3272; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]73; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]74; CHECK-NEXT: sabd z0.b, p0/m, z0.b, z1.b75; CHECK-NEXT: st1b { z0.b }, p0, [x0]76; CHECK-NEXT: ret77 %a.ld = load <32 x i8>, ptr %a78 %b.ld = load <32 x i8>, ptr %b79 %a.sext = sext <32 x i8> %a.ld to <32 x i16>80 %b.sext = sext <32 x i8> %b.ld to <32 x i16>81 %sub = sub <32 x i16> %a.sext, %b.sext82 %abs = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %sub, i1 true)83 %trunc = trunc <32 x i16> %abs to <32 x i8>84 store <32 x i8> %trunc, ptr %a85 ret void86}87 88define void @uabd_v32i8_v32i16(ptr %a, ptr %b) #0 {89; CHECK-LABEL: uabd_v32i8_v32i16:90; CHECK: // %bb.0:91; CHECK-NEXT: ptrue p0.b, vl3292; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]93; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]94; CHECK-NEXT: uabd z0.b, p0/m, z0.b, z1.b95; CHECK-NEXT: st1b { z0.b }, p0, [x0]96; CHECK-NEXT: ret97 %a.ld = load <32 x i8>, ptr %a98 %b.ld = load <32 x i8>, ptr %b99 %a.zext = zext <32 x i8> %a.ld to <32 x i16>100 %b.zext = zext <32 x i8> %b.ld to <32 x i16>101 %sub = sub <32 x i16> %a.zext, %b.zext102 %abs = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %sub, i1 true)103 %trunc = trunc <32 x i16> %abs to <32 x i8>104 store <32 x i8> %trunc, ptr %a105 ret void106}107 108define void @sabd_v32i8_v32i32(ptr %a, ptr %b) #0 {109; CHECK-LABEL: sabd_v32i8_v32i32:110; CHECK: // %bb.0:111; CHECK-NEXT: ptrue p0.b, vl32112; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]113; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]114; CHECK-NEXT: sabd z0.b, p0/m, z0.b, z1.b115; CHECK-NEXT: st1b { z0.b }, p0, [x0]116; CHECK-NEXT: ret117 %a.ld = load <32 x i8>, ptr %a118 %b.ld = load <32 x i8>, ptr %b119 %a.sext = sext <32 x i8> %a.ld to <32 x i32>120 %b.sext = sext <32 x i8> %b.ld to <32 x i32>121 %sub = sub <32 x i32> %a.sext, %b.sext122 %abs = call <32 x i32> @llvm.abs.v32i32(<32 x i32> %sub, i1 true)123 %trunc = trunc <32 x i32> %abs to <32 x i8>124 store <32 x i8> %trunc, ptr %a125 ret void126}127 128define void @sabd_v32i8_v32i64(ptr %a, ptr %b) #0 {129; CHECK-LABEL: sabd_v32i8_v32i64:130; CHECK: // %bb.0:131; CHECK-NEXT: ptrue p0.b, vl32132; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]133; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]134; CHECK-NEXT: sabd z0.b, p0/m, z0.b, z1.b135; CHECK-NEXT: st1b { z0.b }, p0, [x0]136; CHECK-NEXT: ret137 %a.ld = load <32 x i8>, ptr %a138 %b.ld = load <32 x i8>, ptr %b139 %a.sext = sext <32 x i8> %a.ld to <32 x i64>140 %b.sext = sext <32 x i8> %b.ld to <32 x i64>141 %sub = sub <32 x i64> %a.sext, %b.sext142 %abs = call <32 x i64> @llvm.abs.v32i64(<32 x i64> %sub, i1 true)143 %trunc = trunc <32 x i64> %abs to <32 x i8>144 store <32 x i8> %trunc, ptr %a145 ret void146}147 148define void @sabd_v64i8_v64i64(ptr %a, ptr %b) #0 {149; VBITS_GE_256-LABEL: sabd_v64i8_v64i64:150; VBITS_GE_256: // %bb.0:151; VBITS_GE_256-NEXT: ptrue p0.b, vl32152; VBITS_GE_256-NEXT: mov w8, #32 // =0x20153; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]154; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]155; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]156; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]157; VBITS_GE_256-NEXT: sabd z0.b, p0/m, z0.b, z1.b158; VBITS_GE_256-NEXT: sabd z2.b, p0/m, z2.b, z3.b159; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]160; VBITS_GE_256-NEXT: st1b { z2.b }, p0, [x0]161; VBITS_GE_256-NEXT: ret162;163; VBITS_GE_512-LABEL: sabd_v64i8_v64i64:164; VBITS_GE_512: // %bb.0:165; VBITS_GE_512-NEXT: ptrue p0.b, vl64166; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]167; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]168; VBITS_GE_512-NEXT: sabd z0.b, p0/m, z0.b, z1.b169; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]170; VBITS_GE_512-NEXT: ret171 %a.ld = load <64 x i8>, ptr %a172 %b.ld = load <64 x i8>, ptr %b173 %a.sext = sext <64 x i8> %a.ld to <64 x i64>174 %b.sext = sext <64 x i8> %b.ld to <64 x i64>175 %sub = sub <64 x i64> %a.sext, %b.sext176 %abs = call <64 x i64> @llvm.abs.v64i64(<64 x i64> %sub, i1 true)177 %trunc = trunc <64 x i64> %abs to <64 x i8>178 store <64 x i8> %trunc, ptr %a179 ret void180}181 182attributes #0 = { "target-features"="+neon,+sve" }183