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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; ADD10;11 12; Don't use SVE for 64-bit vectors.13define <8 x i8> @add_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {14; CHECK-LABEL: add_v8i8:15; CHECK: // %bb.0:16; CHECK-NEXT: add v0.8b, v0.8b, v1.8b17; CHECK-NEXT: ret18 %res = add <8 x i8> %op1, %op219 ret <8 x i8> %res20}21 22; Don't use SVE for 128-bit vectors.23define <16 x i8> @add_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 {24; CHECK-LABEL: add_v16i8:25; CHECK: // %bb.0:26; CHECK-NEXT: add v0.16b, v0.16b, v1.16b27; CHECK-NEXT: ret28 %res = add <16 x i8> %op1, %op229 ret <16 x i8> %res30}31 32define void @add_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {33; CHECK-LABEL: add_v32i8:34; CHECK: // %bb.0:35; CHECK-NEXT: ptrue p0.b, vl3236; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]37; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]38; CHECK-NEXT: add z0.b, z0.b, z1.b39; CHECK-NEXT: st1b { z0.b }, p0, [x0]40; CHECK-NEXT: ret41 %op1 = load <32 x i8>, ptr %a42 %op2 = load <32 x i8>, ptr %b43 %res = add <32 x i8> %op1, %op244 store <32 x i8> %res, ptr %a45 ret void46}47 48define void @add_v64i8(ptr %a, ptr %b) #0 {49; VBITS_GE_256-LABEL: add_v64i8:50; VBITS_GE_256: // %bb.0:51; VBITS_GE_256-NEXT: ptrue p0.b, vl3252; VBITS_GE_256-NEXT: mov w8, #32 // =0x2053; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]54; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]55; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]56; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]57; VBITS_GE_256-NEXT: add z0.b, z0.b, z1.b58; VBITS_GE_256-NEXT: add z1.b, z2.b, z3.b59; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]60; VBITS_GE_256-NEXT: st1b { z1.b }, p0, [x0]61; VBITS_GE_256-NEXT: ret62;63; VBITS_GE_512-LABEL: add_v64i8:64; VBITS_GE_512: // %bb.0:65; VBITS_GE_512-NEXT: ptrue p0.b, vl6466; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]67; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]68; VBITS_GE_512-NEXT: add z0.b, z0.b, z1.b69; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]70; VBITS_GE_512-NEXT: ret71 %op1 = load <64 x i8>, ptr %a72 %op2 = load <64 x i8>, ptr %b73 %res = add <64 x i8> %op1, %op274 store <64 x i8> %res, ptr %a75 ret void76}77 78define void @add_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {79; CHECK-LABEL: add_v128i8:80; CHECK: // %bb.0:81; CHECK-NEXT: ptrue p0.b, vl12882; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]83; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]84; CHECK-NEXT: add z0.b, z0.b, z1.b85; CHECK-NEXT: st1b { z0.b }, p0, [x0]86; CHECK-NEXT: ret87 %op1 = load <128 x i8>, ptr %a88 %op2 = load <128 x i8>, ptr %b89 %res = add <128 x i8> %op1, %op290 store <128 x i8> %res, ptr %a91 ret void92}93 94define void @add_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {95; CHECK-LABEL: add_v256i8:96; CHECK: // %bb.0:97; CHECK-NEXT: ptrue p0.b, vl25698; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]99; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]100; CHECK-NEXT: add z0.b, z0.b, z1.b101; CHECK-NEXT: st1b { z0.b }, p0, [x0]102; CHECK-NEXT: ret103 %op1 = load <256 x i8>, ptr %a104 %op2 = load <256 x i8>, ptr %b105 %res = add <256 x i8> %op1, %op2106 store <256 x i8> %res, ptr %a107 ret void108}109 110; Don't use SVE for 64-bit vectors.111define <4 x i16> @add_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 {112; CHECK-LABEL: add_v4i16:113; CHECK: // %bb.0:114; CHECK-NEXT: add v0.4h, v0.4h, v1.4h115; CHECK-NEXT: ret116 %res = add <4 x i16> %op1, %op2117 ret <4 x i16> %res118}119 120; Don't use SVE for 128-bit vectors.121define <8 x i16> @add_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 {122; CHECK-LABEL: add_v8i16:123; CHECK: // %bb.0:124; CHECK-NEXT: add v0.8h, v0.8h, v1.8h125; CHECK-NEXT: ret126 %res = add <8 x i16> %op1, %op2127 ret <8 x i16> %res128}129 130define void @add_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {131; CHECK-LABEL: add_v16i16:132; CHECK: // %bb.0:133; CHECK-NEXT: ptrue p0.h, vl16134; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]135; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]136; CHECK-NEXT: add z0.h, z0.h, z1.h137; CHECK-NEXT: st1h { z0.h }, p0, [x0]138; CHECK-NEXT: ret139 %op1 = load <16 x i16>, ptr %a140 %op2 = load <16 x i16>, ptr %b141 %res = add <16 x i16> %op1, %op2142 store <16 x i16> %res, ptr %a143 ret void144}145 146define void @add_v32i16(ptr %a, ptr %b) #0 {147; VBITS_GE_256-LABEL: add_v32i16:148; VBITS_GE_256: // %bb.0:149; VBITS_GE_256-NEXT: ptrue p0.h, vl16150; VBITS_GE_256-NEXT: mov x8, #16 // =0x10151; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]152; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]153; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]154; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]155; VBITS_GE_256-NEXT: add z0.h, z0.h, z1.h156; VBITS_GE_256-NEXT: add z1.h, z2.h, z3.h157; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]158; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x0]159; VBITS_GE_256-NEXT: ret160;161; VBITS_GE_512-LABEL: add_v32i16:162; VBITS_GE_512: // %bb.0:163; VBITS_GE_512-NEXT: ptrue p0.h, vl32164; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]165; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]166; VBITS_GE_512-NEXT: add z0.h, z0.h, z1.h167; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]168; VBITS_GE_512-NEXT: ret169 %op1 = load <32 x i16>, ptr %a170 %op2 = load <32 x i16>, ptr %b171 %res = add <32 x i16> %op1, %op2172 store <32 x i16> %res, ptr %a173 ret void174}175 176define void @add_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {177; CHECK-LABEL: add_v64i16:178; CHECK: // %bb.0:179; CHECK-NEXT: ptrue p0.h, vl64180; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]181; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]182; CHECK-NEXT: add z0.h, z0.h, z1.h183; CHECK-NEXT: st1h { z0.h }, p0, [x0]184; CHECK-NEXT: ret185 %op1 = load <64 x i16>, ptr %a186 %op2 = load <64 x i16>, ptr %b187 %res = add <64 x i16> %op1, %op2188 store <64 x i16> %res, ptr %a189 ret void190}191 192define void @add_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {193; CHECK-LABEL: add_v128i16:194; CHECK: // %bb.0:195; CHECK-NEXT: ptrue p0.h, vl128196; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]197; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]198; CHECK-NEXT: add z0.h, z0.h, z1.h199; CHECK-NEXT: st1h { z0.h }, p0, [x0]200; CHECK-NEXT: ret201 %op1 = load <128 x i16>, ptr %a202 %op2 = load <128 x i16>, ptr %b203 %res = add <128 x i16> %op1, %op2204 store <128 x i16> %res, ptr %a205 ret void206}207 208; Don't use SVE for 64-bit vectors.209define <2 x i32> @add_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) #0 {210; CHECK-LABEL: add_v2i32:211; CHECK: // %bb.0:212; CHECK-NEXT: add v0.2s, v0.2s, v1.2s213; CHECK-NEXT: ret214 %res = add <2 x i32> %op1, %op2215 ret <2 x i32> %res216}217 218; Don't use SVE for 128-bit vectors.219define <4 x i32> @add_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 {220; CHECK-LABEL: add_v4i32:221; CHECK: // %bb.0:222; CHECK-NEXT: add v0.4s, v0.4s, v1.4s223; CHECK-NEXT: ret224 %res = add <4 x i32> %op1, %op2225 ret <4 x i32> %res226}227 228define void @add_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {229; CHECK-LABEL: add_v8i32:230; CHECK: // %bb.0:231; CHECK-NEXT: ptrue p0.s, vl8232; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]233; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]234; CHECK-NEXT: add z0.s, z0.s, z1.s235; CHECK-NEXT: st1w { z0.s }, p0, [x0]236; CHECK-NEXT: ret237 %op1 = load <8 x i32>, ptr %a238 %op2 = load <8 x i32>, ptr %b239 %res = add <8 x i32> %op1, %op2240 store <8 x i32> %res, ptr %a241 ret void242}243 244define void @add_v16i32(ptr %a, ptr %b) #0 {245; VBITS_GE_256-LABEL: add_v16i32:246; VBITS_GE_256: // %bb.0:247; VBITS_GE_256-NEXT: ptrue p0.s, vl8248; VBITS_GE_256-NEXT: mov x8, #8 // =0x8249; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]250; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]251; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]252; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]253; VBITS_GE_256-NEXT: add z0.s, z0.s, z1.s254; VBITS_GE_256-NEXT: add z1.s, z2.s, z3.s255; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]256; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]257; VBITS_GE_256-NEXT: ret258;259; VBITS_GE_512-LABEL: add_v16i32:260; VBITS_GE_512: // %bb.0:261; VBITS_GE_512-NEXT: ptrue p0.s, vl16262; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]263; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]264; VBITS_GE_512-NEXT: add z0.s, z0.s, z1.s265; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]266; VBITS_GE_512-NEXT: ret267 %op1 = load <16 x i32>, ptr %a268 %op2 = load <16 x i32>, ptr %b269 %res = add <16 x i32> %op1, %op2270 store <16 x i32> %res, ptr %a271 ret void272}273 274define void @add_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {275; CHECK-LABEL: add_v32i32:276; CHECK: // %bb.0:277; CHECK-NEXT: ptrue p0.s, vl32278; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]279; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]280; CHECK-NEXT: add z0.s, z0.s, z1.s281; CHECK-NEXT: st1w { z0.s }, p0, [x0]282; CHECK-NEXT: ret283 %op1 = load <32 x i32>, ptr %a284 %op2 = load <32 x i32>, ptr %b285 %res = add <32 x i32> %op1, %op2286 store <32 x i32> %res, ptr %a287 ret void288}289 290define void @add_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {291; CHECK-LABEL: add_v64i32:292; CHECK: // %bb.0:293; CHECK-NEXT: ptrue p0.s, vl64294; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]295; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]296; CHECK-NEXT: add z0.s, z0.s, z1.s297; CHECK-NEXT: st1w { z0.s }, p0, [x0]298; CHECK-NEXT: ret299 %op1 = load <64 x i32>, ptr %a300 %op2 = load <64 x i32>, ptr %b301 %res = add <64 x i32> %op1, %op2302 store <64 x i32> %res, ptr %a303 ret void304}305 306; Don't use SVE for 64-bit vectors.307define <1 x i64> @add_v1i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0) #0 {308; CHECK-LABEL: add_v1i64:309; CHECK: // %bb.0:310; CHECK-NEXT: add d0, d0, d1311; CHECK-NEXT: ret312 %res = add <1 x i64> %op1, %op2313 ret <1 x i64> %res314}315 316; Don't use SVE for 128-bit vectors.317define <2 x i64> @add_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 {318; CHECK-LABEL: add_v2i64:319; CHECK: // %bb.0:320; CHECK-NEXT: add v0.2d, v0.2d, v1.2d321; CHECK-NEXT: ret322 %res = add <2 x i64> %op1, %op2323 ret <2 x i64> %res324}325 326define void @add_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {327; CHECK-LABEL: add_v4i64:328; CHECK: // %bb.0:329; CHECK-NEXT: ptrue p0.d, vl4330; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]331; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]332; CHECK-NEXT: add z0.d, z0.d, z1.d333; CHECK-NEXT: st1d { z0.d }, p0, [x0]334; CHECK-NEXT: ret335 %op1 = load <4 x i64>, ptr %a336 %op2 = load <4 x i64>, ptr %b337 %res = add <4 x i64> %op1, %op2338 store <4 x i64> %res, ptr %a339 ret void340}341 342define void @add_v8i64(ptr %a, ptr %b) #0 {343; VBITS_GE_256-LABEL: add_v8i64:344; VBITS_GE_256: // %bb.0:345; VBITS_GE_256-NEXT: ptrue p0.d, vl4346; VBITS_GE_256-NEXT: mov x8, #4 // =0x4347; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]348; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]349; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]350; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]351; VBITS_GE_256-NEXT: add z0.d, z0.d, z1.d352; VBITS_GE_256-NEXT: add z1.d, z2.d, z3.d353; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]354; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]355; VBITS_GE_256-NEXT: ret356;357; VBITS_GE_512-LABEL: add_v8i64:358; VBITS_GE_512: // %bb.0:359; VBITS_GE_512-NEXT: ptrue p0.d, vl8360; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]361; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]362; VBITS_GE_512-NEXT: add z0.d, z0.d, z1.d363; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]364; VBITS_GE_512-NEXT: ret365 %op1 = load <8 x i64>, ptr %a366 %op2 = load <8 x i64>, ptr %b367 %res = add <8 x i64> %op1, %op2368 store <8 x i64> %res, ptr %a369 ret void370}371 372define void @add_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {373; CHECK-LABEL: add_v16i64:374; CHECK: // %bb.0:375; CHECK-NEXT: ptrue p0.d, vl16376; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]377; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]378; CHECK-NEXT: add z0.d, z0.d, z1.d379; CHECK-NEXT: st1d { z0.d }, p0, [x0]380; CHECK-NEXT: ret381 %op1 = load <16 x i64>, ptr %a382 %op2 = load <16 x i64>, ptr %b383 %res = add <16 x i64> %op1, %op2384 store <16 x i64> %res, ptr %a385 ret void386}387 388define void @add_v32i64(ptr %a, ptr %b) vscale_range(8,0) #0 {389; CHECK-LABEL: add_v32i64:390; CHECK: // %bb.0:391; CHECK-NEXT: ptrue p0.d, vl16392; CHECK-NEXT: mov x8, #16 // =0x10393; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]394; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]395; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]396; CHECK-NEXT: ld1d { z3.d }, p0/z, [x1]397; CHECK-NEXT: add z0.d, z0.d, z1.d398; CHECK-NEXT: add z1.d, z2.d, z3.d399; CHECK-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]400; CHECK-NEXT: st1d { z1.d }, p0, [x0]401; CHECK-NEXT: ret402 %op1 = load <32 x i64>, ptr %a403 %op2 = load <32 x i64>, ptr %b404 %res = add <32 x i64> %op1, %op2405 store <32 x i64> %res, ptr %a406 ret void407}408 409;410; MUL411;412 413; Don't use SVE for 64-bit vectors.414define <8 x i8> @mul_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {415; CHECK-LABEL: mul_v8i8:416; CHECK: // %bb.0:417; CHECK-NEXT: mul v0.8b, v0.8b, v1.8b418; CHECK-NEXT: ret419 %res = mul <8 x i8> %op1, %op2420 ret <8 x i8> %res421}422 423; Don't use SVE for 128-bit vectors.424define <16 x i8> @mul_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 {425; CHECK-LABEL: mul_v16i8:426; CHECK: // %bb.0:427; CHECK-NEXT: mul v0.16b, v0.16b, v1.16b428; CHECK-NEXT: ret429 %res = mul <16 x i8> %op1, %op2430 ret <16 x i8> %res431}432 433define void @mul_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {434; CHECK-LABEL: mul_v32i8:435; CHECK: // %bb.0:436; CHECK-NEXT: ptrue p0.b, vl32437; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]438; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]439; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b440; CHECK-NEXT: st1b { z0.b }, p0, [x0]441; CHECK-NEXT: ret442 %op1 = load <32 x i8>, ptr %a443 %op2 = load <32 x i8>, ptr %b444 %res = mul <32 x i8> %op1, %op2445 store <32 x i8> %res, ptr %a446 ret void447}448 449define void @mul_v64i8(ptr %a, ptr %b) #0 {450; VBITS_GE_256-LABEL: mul_v64i8:451; VBITS_GE_256: // %bb.0:452; VBITS_GE_256-NEXT: ptrue p0.b, vl32453; VBITS_GE_256-NEXT: mov w8, #32 // =0x20454; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]455; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]456; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]457; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]458; VBITS_GE_256-NEXT: mul z0.b, p0/m, z0.b, z1.b459; VBITS_GE_256-NEXT: mul z2.b, p0/m, z2.b, z3.b460; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]461; VBITS_GE_256-NEXT: st1b { z2.b }, p0, [x0]462; VBITS_GE_256-NEXT: ret463;464; VBITS_GE_512-LABEL: mul_v64i8:465; VBITS_GE_512: // %bb.0:466; VBITS_GE_512-NEXT: ptrue p0.b, vl64467; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]468; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]469; VBITS_GE_512-NEXT: mul z0.b, p0/m, z0.b, z1.b470; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]471; VBITS_GE_512-NEXT: ret472 %op1 = load <64 x i8>, ptr %a473 %op2 = load <64 x i8>, ptr %b474 %res = mul <64 x i8> %op1, %op2475 store <64 x i8> %res, ptr %a476 ret void477}478 479define void @mul_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {480; CHECK-LABEL: mul_v128i8:481; CHECK: // %bb.0:482; CHECK-NEXT: ptrue p0.b, vl128483; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]484; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]485; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b486; CHECK-NEXT: st1b { z0.b }, p0, [x0]487; CHECK-NEXT: ret488 %op1 = load <128 x i8>, ptr %a489 %op2 = load <128 x i8>, ptr %b490 %res = mul <128 x i8> %op1, %op2491 store <128 x i8> %res, ptr %a492 ret void493}494 495define void @mul_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {496; CHECK-LABEL: mul_v256i8:497; CHECK: // %bb.0:498; CHECK-NEXT: ptrue p0.b, vl256499; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]500; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]501; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b502; CHECK-NEXT: st1b { z0.b }, p0, [x0]503; CHECK-NEXT: ret504 %op1 = load <256 x i8>, ptr %a505 %op2 = load <256 x i8>, ptr %b506 %res = mul <256 x i8> %op1, %op2507 store <256 x i8> %res, ptr %a508 ret void509}510 511; Don't use SVE for 64-bit vectors.512define <4 x i16> @mul_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 {513; CHECK-LABEL: mul_v4i16:514; CHECK: // %bb.0:515; CHECK-NEXT: mul v0.4h, v0.4h, v1.4h516; CHECK-NEXT: ret517 %res = mul <4 x i16> %op1, %op2518 ret <4 x i16> %res519}520 521; Don't use SVE for 128-bit vectors.522define <8 x i16> @mul_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 {523; CHECK-LABEL: mul_v8i16:524; CHECK: // %bb.0:525; CHECK-NEXT: mul v0.8h, v0.8h, v1.8h526; CHECK-NEXT: ret527 %res = mul <8 x i16> %op1, %op2528 ret <8 x i16> %res529}530 531define void @mul_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {532; CHECK-LABEL: mul_v16i16:533; CHECK: // %bb.0:534; CHECK-NEXT: ptrue p0.h, vl16535; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]536; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]537; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h538; CHECK-NEXT: st1h { z0.h }, p0, [x0]539; CHECK-NEXT: ret540 %op1 = load <16 x i16>, ptr %a541 %op2 = load <16 x i16>, ptr %b542 %res = mul <16 x i16> %op1, %op2543 store <16 x i16> %res, ptr %a544 ret void545}546 547define void @mul_v32i16(ptr %a, ptr %b) #0 {548; VBITS_GE_256-LABEL: mul_v32i16:549; VBITS_GE_256: // %bb.0:550; VBITS_GE_256-NEXT: ptrue p0.h, vl16551; VBITS_GE_256-NEXT: mov x8, #16 // =0x10552; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]553; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]554; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]555; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]556; VBITS_GE_256-NEXT: mul z0.h, p0/m, z0.h, z1.h557; VBITS_GE_256-NEXT: mul z2.h, p0/m, z2.h, z3.h558; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]559; VBITS_GE_256-NEXT: st1h { z2.h }, p0, [x0]560; VBITS_GE_256-NEXT: ret561;562; VBITS_GE_512-LABEL: mul_v32i16:563; VBITS_GE_512: // %bb.0:564; VBITS_GE_512-NEXT: ptrue p0.h, vl32565; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]566; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]567; VBITS_GE_512-NEXT: mul z0.h, p0/m, z0.h, z1.h568; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]569; VBITS_GE_512-NEXT: ret570 %op1 = load <32 x i16>, ptr %a571 %op2 = load <32 x i16>, ptr %b572 %res = mul <32 x i16> %op1, %op2573 store <32 x i16> %res, ptr %a574 ret void575}576 577define void @mul_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {578; CHECK-LABEL: mul_v64i16:579; CHECK: // %bb.0:580; CHECK-NEXT: ptrue p0.h, vl64581; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]582; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]583; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h584; CHECK-NEXT: st1h { z0.h }, p0, [x0]585; CHECK-NEXT: ret586 %op1 = load <64 x i16>, ptr %a587 %op2 = load <64 x i16>, ptr %b588 %res = mul <64 x i16> %op1, %op2589 store <64 x i16> %res, ptr %a590 ret void591}592 593define void @mul_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {594; CHECK-LABEL: mul_v128i16:595; CHECK: // %bb.0:596; CHECK-NEXT: ptrue p0.h, vl128597; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]598; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]599; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h600; CHECK-NEXT: st1h { z0.h }, p0, [x0]601; CHECK-NEXT: ret602 %op1 = load <128 x i16>, ptr %a603 %op2 = load <128 x i16>, ptr %b604 %res = mul <128 x i16> %op1, %op2605 store <128 x i16> %res, ptr %a606 ret void607}608 609; Don't use SVE for 64-bit vectors.610define <2 x i32> @mul_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) #0 {611; CHECK-LABEL: mul_v2i32:612; CHECK: // %bb.0:613; CHECK-NEXT: mul v0.2s, v0.2s, v1.2s614; CHECK-NEXT: ret615 %res = mul <2 x i32> %op1, %op2616 ret <2 x i32> %res617}618 619; Don't use SVE for 128-bit vectors.620define <4 x i32> @mul_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 {621; CHECK-LABEL: mul_v4i32:622; CHECK: // %bb.0:623; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s624; CHECK-NEXT: ret625 %res = mul <4 x i32> %op1, %op2626 ret <4 x i32> %res627}628 629define void @mul_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {630; CHECK-LABEL: mul_v8i32:631; CHECK: // %bb.0:632; CHECK-NEXT: ptrue p0.s, vl8633; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]634; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]635; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s636; CHECK-NEXT: st1w { z0.s }, p0, [x0]637; CHECK-NEXT: ret638 %op1 = load <8 x i32>, ptr %a639 %op2 = load <8 x i32>, ptr %b640 %res = mul <8 x i32> %op1, %op2641 store <8 x i32> %res, ptr %a642 ret void643}644 645define void @mul_v16i32(ptr %a, ptr %b) #0 {646; VBITS_GE_256-LABEL: mul_v16i32:647; VBITS_GE_256: // %bb.0:648; VBITS_GE_256-NEXT: ptrue p0.s, vl8649; VBITS_GE_256-NEXT: mov x8, #8 // =0x8650; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]651; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]652; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]653; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]654; VBITS_GE_256-NEXT: mul z0.s, p0/m, z0.s, z1.s655; VBITS_GE_256-NEXT: mul z2.s, p0/m, z2.s, z3.s656; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]657; VBITS_GE_256-NEXT: st1w { z2.s }, p0, [x0]658; VBITS_GE_256-NEXT: ret659;660; VBITS_GE_512-LABEL: mul_v16i32:661; VBITS_GE_512: // %bb.0:662; VBITS_GE_512-NEXT: ptrue p0.s, vl16663; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]664; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]665; VBITS_GE_512-NEXT: mul z0.s, p0/m, z0.s, z1.s666; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]667; VBITS_GE_512-NEXT: ret668 %op1 = load <16 x i32>, ptr %a669 %op2 = load <16 x i32>, ptr %b670 %res = mul <16 x i32> %op1, %op2671 store <16 x i32> %res, ptr %a672 ret void673}674 675define void @mul_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {676; CHECK-LABEL: mul_v32i32:677; CHECK: // %bb.0:678; CHECK-NEXT: ptrue p0.s, vl32679; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]680; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]681; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s682; CHECK-NEXT: st1w { z0.s }, p0, [x0]683; CHECK-NEXT: ret684 %op1 = load <32 x i32>, ptr %a685 %op2 = load <32 x i32>, ptr %b686 %res = mul <32 x i32> %op1, %op2687 store <32 x i32> %res, ptr %a688 ret void689}690 691define void @mul_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {692; CHECK-LABEL: mul_v64i32:693; CHECK: // %bb.0:694; CHECK-NEXT: ptrue p0.s, vl64695; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]696; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]697; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s698; CHECK-NEXT: st1w { z0.s }, p0, [x0]699; CHECK-NEXT: ret700 %op1 = load <64 x i32>, ptr %a701 %op2 = load <64 x i32>, ptr %b702 %res = mul <64 x i32> %op1, %op2703 store <64 x i32> %res, ptr %a704 ret void705}706 707define <1 x i64> @mul_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {708; CHECK-LABEL: mul_v1i64:709; CHECK: // %bb.0:710; CHECK-NEXT: ptrue p0.d, vl1711; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0712; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1713; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d714; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0715; CHECK-NEXT: ret716 %res = mul <1 x i64> %op1, %op2717 ret <1 x i64> %res718}719 720define <2 x i64> @mul_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {721; CHECK-LABEL: mul_v2i64:722; CHECK: // %bb.0:723; CHECK-NEXT: ptrue p0.d, vl2724; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0725; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1726; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d727; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0728; CHECK-NEXT: ret729 %res = mul <2 x i64> %op1, %op2730 ret <2 x i64> %res731}732 733define void @mul_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {734; CHECK-LABEL: mul_v4i64:735; CHECK: // %bb.0:736; CHECK-NEXT: ptrue p0.d, vl4737; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]738; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]739; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d740; CHECK-NEXT: st1d { z0.d }, p0, [x0]741; CHECK-NEXT: ret742 %op1 = load <4 x i64>, ptr %a743 %op2 = load <4 x i64>, ptr %b744 %res = mul <4 x i64> %op1, %op2745 store <4 x i64> %res, ptr %a746 ret void747}748 749define void @mul_v8i64(ptr %a, ptr %b) #0 {750; VBITS_GE_256-LABEL: mul_v8i64:751; VBITS_GE_256: // %bb.0:752; VBITS_GE_256-NEXT: ptrue p0.d, vl4753; VBITS_GE_256-NEXT: mov x8, #4 // =0x4754; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]755; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]756; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]757; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]758; VBITS_GE_256-NEXT: mul z0.d, p0/m, z0.d, z1.d759; VBITS_GE_256-NEXT: mul z2.d, p0/m, z2.d, z3.d760; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]761; VBITS_GE_256-NEXT: st1d { z2.d }, p0, [x0]762; VBITS_GE_256-NEXT: ret763;764; VBITS_GE_512-LABEL: mul_v8i64:765; VBITS_GE_512: // %bb.0:766; VBITS_GE_512-NEXT: ptrue p0.d, vl8767; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]768; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]769; VBITS_GE_512-NEXT: mul z0.d, p0/m, z0.d, z1.d770; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]771; VBITS_GE_512-NEXT: ret772 %op1 = load <8 x i64>, ptr %a773 %op2 = load <8 x i64>, ptr %b774 %res = mul <8 x i64> %op1, %op2775 store <8 x i64> %res, ptr %a776 ret void777}778 779define void @mul_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {780; CHECK-LABEL: mul_v16i64:781; CHECK: // %bb.0:782; CHECK-NEXT: ptrue p0.d, vl16783; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]784; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]785; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d786; CHECK-NEXT: st1d { z0.d }, p0, [x0]787; CHECK-NEXT: ret788 %op1 = load <16 x i64>, ptr %a789 %op2 = load <16 x i64>, ptr %b790 %res = mul <16 x i64> %op1, %op2791 store <16 x i64> %res, ptr %a792 ret void793}794 795define void @mul_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {796; CHECK-LABEL: mul_v32i64:797; CHECK: // %bb.0:798; CHECK-NEXT: ptrue p0.d, vl32799; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]800; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]801; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d802; CHECK-NEXT: st1d { z0.d }, p0, [x0]803; CHECK-NEXT: ret804 %op1 = load <32 x i64>, ptr %a805 %op2 = load <32 x i64>, ptr %b806 %res = mul <32 x i64> %op1, %op2807 store <32 x i64> %res, ptr %a808 ret void809}810 811;812; SUB813;814 815; Don't use SVE for 64-bit vectors.816define <8 x i8> @sub_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {817; CHECK-LABEL: sub_v8i8:818; CHECK: // %bb.0:819; CHECK-NEXT: sub v0.8b, v0.8b, v1.8b820; CHECK-NEXT: ret821 %res = sub <8 x i8> %op1, %op2822 ret <8 x i8> %res823}824 825; Don't use SVE for 128-bit vectors.826define <16 x i8> @sub_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 {827; CHECK-LABEL: sub_v16i8:828; CHECK: // %bb.0:829; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b830; CHECK-NEXT: ret831 %res = sub <16 x i8> %op1, %op2832 ret <16 x i8> %res833}834 835define void @sub_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {836; CHECK-LABEL: sub_v32i8:837; CHECK: // %bb.0:838; CHECK-NEXT: ptrue p0.b, vl32839; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]840; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]841; CHECK-NEXT: sub z0.b, z0.b, z1.b842; CHECK-NEXT: st1b { z0.b }, p0, [x0]843; CHECK-NEXT: ret844 %op1 = load <32 x i8>, ptr %a845 %op2 = load <32 x i8>, ptr %b846 %res = sub <32 x i8> %op1, %op2847 store <32 x i8> %res, ptr %a848 ret void849}850 851define void @sub_v64i8(ptr %a, ptr %b) #0 {852; VBITS_GE_256-LABEL: sub_v64i8:853; VBITS_GE_256: // %bb.0:854; VBITS_GE_256-NEXT: ptrue p0.b, vl32855; VBITS_GE_256-NEXT: mov w8, #32 // =0x20856; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]857; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]858; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]859; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]860; VBITS_GE_256-NEXT: sub z0.b, z0.b, z1.b861; VBITS_GE_256-NEXT: sub z1.b, z2.b, z3.b862; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]863; VBITS_GE_256-NEXT: st1b { z1.b }, p0, [x0]864; VBITS_GE_256-NEXT: ret865;866; VBITS_GE_512-LABEL: sub_v64i8:867; VBITS_GE_512: // %bb.0:868; VBITS_GE_512-NEXT: ptrue p0.b, vl64869; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]870; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]871; VBITS_GE_512-NEXT: sub z0.b, z0.b, z1.b872; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]873; VBITS_GE_512-NEXT: ret874 %op1 = load <64 x i8>, ptr %a875 %op2 = load <64 x i8>, ptr %b876 %res = sub <64 x i8> %op1, %op2877 store <64 x i8> %res, ptr %a878 ret void879}880 881define void @sub_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {882; CHECK-LABEL: sub_v128i8:883; CHECK: // %bb.0:884; CHECK-NEXT: ptrue p0.b, vl128885; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]886; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]887; CHECK-NEXT: sub z0.b, z0.b, z1.b888; CHECK-NEXT: st1b { z0.b }, p0, [x0]889; CHECK-NEXT: ret890 %op1 = load <128 x i8>, ptr %a891 %op2 = load <128 x i8>, ptr %b892 %res = sub <128 x i8> %op1, %op2893 store <128 x i8> %res, ptr %a894 ret void895}896 897define void @sub_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {898; CHECK-LABEL: sub_v256i8:899; CHECK: // %bb.0:900; CHECK-NEXT: ptrue p0.b, vl256901; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]902; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]903; CHECK-NEXT: sub z0.b, z0.b, z1.b904; CHECK-NEXT: st1b { z0.b }, p0, [x0]905; CHECK-NEXT: ret906 %op1 = load <256 x i8>, ptr %a907 %op2 = load <256 x i8>, ptr %b908 %res = sub <256 x i8> %op1, %op2909 store <256 x i8> %res, ptr %a910 ret void911}912 913; Don't use SVE for 64-bit vectors.914define <4 x i16> @sub_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 {915; CHECK-LABEL: sub_v4i16:916; CHECK: // %bb.0:917; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h918; CHECK-NEXT: ret919 %res = sub <4 x i16> %op1, %op2920 ret <4 x i16> %res921}922 923; Don't use SVE for 128-bit vectors.924define <8 x i16> @sub_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 {925; CHECK-LABEL: sub_v8i16:926; CHECK: // %bb.0:927; CHECK-NEXT: sub v0.8h, v0.8h, v1.8h928; CHECK-NEXT: ret929 %res = sub <8 x i16> %op1, %op2930 ret <8 x i16> %res931}932 933define void @sub_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {934; CHECK-LABEL: sub_v16i16:935; CHECK: // %bb.0:936; CHECK-NEXT: ptrue p0.h, vl16937; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]938; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]939; CHECK-NEXT: sub z0.h, z0.h, z1.h940; CHECK-NEXT: st1h { z0.h }, p0, [x0]941; CHECK-NEXT: ret942 %op1 = load <16 x i16>, ptr %a943 %op2 = load <16 x i16>, ptr %b944 %res = sub <16 x i16> %op1, %op2945 store <16 x i16> %res, ptr %a946 ret void947}948 949define void @sub_v32i16(ptr %a, ptr %b) #0 {950; VBITS_GE_256-LABEL: sub_v32i16:951; VBITS_GE_256: // %bb.0:952; VBITS_GE_256-NEXT: ptrue p0.h, vl16953; VBITS_GE_256-NEXT: mov x8, #16 // =0x10954; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]955; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]956; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]957; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]958; VBITS_GE_256-NEXT: sub z0.h, z0.h, z1.h959; VBITS_GE_256-NEXT: sub z1.h, z2.h, z3.h960; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]961; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x0]962; VBITS_GE_256-NEXT: ret963;964; VBITS_GE_512-LABEL: sub_v32i16:965; VBITS_GE_512: // %bb.0:966; VBITS_GE_512-NEXT: ptrue p0.h, vl32967; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]968; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]969; VBITS_GE_512-NEXT: sub z0.h, z0.h, z1.h970; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]971; VBITS_GE_512-NEXT: ret972 %op1 = load <32 x i16>, ptr %a973 %op2 = load <32 x i16>, ptr %b974 %res = sub <32 x i16> %op1, %op2975 store <32 x i16> %res, ptr %a976 ret void977}978 979define void @sub_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {980; CHECK-LABEL: sub_v64i16:981; CHECK: // %bb.0:982; CHECK-NEXT: ptrue p0.h, vl64983; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]984; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]985; CHECK-NEXT: sub z0.h, z0.h, z1.h986; CHECK-NEXT: st1h { z0.h }, p0, [x0]987; CHECK-NEXT: ret988 %op1 = load <64 x i16>, ptr %a989 %op2 = load <64 x i16>, ptr %b990 %res = sub <64 x i16> %op1, %op2991 store <64 x i16> %res, ptr %a992 ret void993}994 995define void @sub_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {996; CHECK-LABEL: sub_v128i16:997; CHECK: // %bb.0:998; CHECK-NEXT: ptrue p0.h, vl128999; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1000; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]1001; CHECK-NEXT: sub z0.h, z0.h, z1.h1002; CHECK-NEXT: st1h { z0.h }, p0, [x0]1003; CHECK-NEXT: ret1004 %op1 = load <128 x i16>, ptr %a1005 %op2 = load <128 x i16>, ptr %b1006 %res = sub <128 x i16> %op1, %op21007 store <128 x i16> %res, ptr %a1008 ret void1009}1010 1011; Don't use SVE for 64-bit vectors.1012define <2 x i32> @sub_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) #0 {1013; CHECK-LABEL: sub_v2i32:1014; CHECK: // %bb.0:1015; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s1016; CHECK-NEXT: ret1017 %res = sub <2 x i32> %op1, %op21018 ret <2 x i32> %res1019}1020 1021; Don't use SVE for 128-bit vectors.1022define <4 x i32> @sub_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 {1023; CHECK-LABEL: sub_v4i32:1024; CHECK: // %bb.0:1025; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s1026; CHECK-NEXT: ret1027 %res = sub <4 x i32> %op1, %op21028 ret <4 x i32> %res1029}1030 1031define void @sub_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {1032; CHECK-LABEL: sub_v8i32:1033; CHECK: // %bb.0:1034; CHECK-NEXT: ptrue p0.s, vl81035; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1036; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1037; CHECK-NEXT: sub z0.s, z0.s, z1.s1038; CHECK-NEXT: st1w { z0.s }, p0, [x0]1039; CHECK-NEXT: ret1040 %op1 = load <8 x i32>, ptr %a1041 %op2 = load <8 x i32>, ptr %b1042 %res = sub <8 x i32> %op1, %op21043 store <8 x i32> %res, ptr %a1044 ret void1045}1046 1047define void @sub_v16i32(ptr %a, ptr %b) #0 {1048; VBITS_GE_256-LABEL: sub_v16i32:1049; VBITS_GE_256: // %bb.0:1050; VBITS_GE_256-NEXT: ptrue p0.s, vl81051; VBITS_GE_256-NEXT: mov x8, #8 // =0x81052; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]1053; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]1054; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]1055; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]1056; VBITS_GE_256-NEXT: sub z0.s, z0.s, z1.s1057; VBITS_GE_256-NEXT: sub z1.s, z2.s, z3.s1058; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]1059; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]1060; VBITS_GE_256-NEXT: ret1061;1062; VBITS_GE_512-LABEL: sub_v16i32:1063; VBITS_GE_512: // %bb.0:1064; VBITS_GE_512-NEXT: ptrue p0.s, vl161065; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]1066; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]1067; VBITS_GE_512-NEXT: sub z0.s, z0.s, z1.s1068; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]1069; VBITS_GE_512-NEXT: ret1070 %op1 = load <16 x i32>, ptr %a1071 %op2 = load <16 x i32>, ptr %b1072 %res = sub <16 x i32> %op1, %op21073 store <16 x i32> %res, ptr %a1074 ret void1075}1076 1077define void @sub_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {1078; CHECK-LABEL: sub_v32i32:1079; CHECK: // %bb.0:1080; CHECK-NEXT: ptrue p0.s, vl321081; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1082; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1083; CHECK-NEXT: sub z0.s, z0.s, z1.s1084; CHECK-NEXT: st1w { z0.s }, p0, [x0]1085; CHECK-NEXT: ret1086 %op1 = load <32 x i32>, ptr %a1087 %op2 = load <32 x i32>, ptr %b1088 %res = sub <32 x i32> %op1, %op21089 store <32 x i32> %res, ptr %a1090 ret void1091}1092 1093define void @sub_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {1094; CHECK-LABEL: sub_v64i32:1095; CHECK: // %bb.0:1096; CHECK-NEXT: ptrue p0.s, vl641097; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1098; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1099; CHECK-NEXT: sub z0.s, z0.s, z1.s1100; CHECK-NEXT: st1w { z0.s }, p0, [x0]1101; CHECK-NEXT: ret1102 %op1 = load <64 x i32>, ptr %a1103 %op2 = load <64 x i32>, ptr %b1104 %res = sub <64 x i32> %op1, %op21105 store <64 x i32> %res, ptr %a1106 ret void1107}1108 1109; Don't use SVE for 64-bit vectors.1110define <1 x i64> @sub_v1i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0) #0 {1111; CHECK-LABEL: sub_v1i64:1112; CHECK: // %bb.0:1113; CHECK-NEXT: sub d0, d0, d11114; CHECK-NEXT: ret1115 %res = sub <1 x i64> %op1, %op21116 ret <1 x i64> %res1117}1118 1119; Don't use SVE for 128-bit vectors.1120define <2 x i64> @sub_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 {1121; CHECK-LABEL: sub_v2i64:1122; CHECK: // %bb.0:1123; CHECK-NEXT: sub v0.2d, v0.2d, v1.2d1124; CHECK-NEXT: ret1125 %res = sub <2 x i64> %op1, %op21126 ret <2 x i64> %res1127}1128 1129define void @sub_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {1130; CHECK-LABEL: sub_v4i64:1131; CHECK: // %bb.0:1132; CHECK-NEXT: ptrue p0.d, vl41133; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1134; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1135; CHECK-NEXT: sub z0.d, z0.d, z1.d1136; CHECK-NEXT: st1d { z0.d }, p0, [x0]1137; CHECK-NEXT: ret1138 %op1 = load <4 x i64>, ptr %a1139 %op2 = load <4 x i64>, ptr %b1140 %res = sub <4 x i64> %op1, %op21141 store <4 x i64> %res, ptr %a1142 ret void1143}1144 1145define void @sub_v8i64(ptr %a, ptr %b) #0 {1146; VBITS_GE_256-LABEL: sub_v8i64:1147; VBITS_GE_256: // %bb.0:1148; VBITS_GE_256-NEXT: ptrue p0.d, vl41149; VBITS_GE_256-NEXT: mov x8, #4 // =0x41150; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]1151; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]1152; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]1153; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]1154; VBITS_GE_256-NEXT: sub z0.d, z0.d, z1.d1155; VBITS_GE_256-NEXT: sub z1.d, z2.d, z3.d1156; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]1157; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]1158; VBITS_GE_256-NEXT: ret1159;1160; VBITS_GE_512-LABEL: sub_v8i64:1161; VBITS_GE_512: // %bb.0:1162; VBITS_GE_512-NEXT: ptrue p0.d, vl81163; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]1164; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]1165; VBITS_GE_512-NEXT: sub z0.d, z0.d, z1.d1166; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]1167; VBITS_GE_512-NEXT: ret1168 %op1 = load <8 x i64>, ptr %a1169 %op2 = load <8 x i64>, ptr %b1170 %res = sub <8 x i64> %op1, %op21171 store <8 x i64> %res, ptr %a1172 ret void1173}1174 1175define void @sub_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {1176; CHECK-LABEL: sub_v16i64:1177; CHECK: // %bb.0:1178; CHECK-NEXT: ptrue p0.d, vl161179; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1180; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1181; CHECK-NEXT: sub z0.d, z0.d, z1.d1182; CHECK-NEXT: st1d { z0.d }, p0, [x0]1183; CHECK-NEXT: ret1184 %op1 = load <16 x i64>, ptr %a1185 %op2 = load <16 x i64>, ptr %b1186 %res = sub <16 x i64> %op1, %op21187 store <16 x i64> %res, ptr %a1188 ret void1189}1190 1191define void @sub_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {1192; CHECK-LABEL: sub_v32i64:1193; CHECK: // %bb.0:1194; CHECK-NEXT: ptrue p0.d, vl321195; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1196; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1197; CHECK-NEXT: sub z0.d, z0.d, z1.d1198; CHECK-NEXT: st1d { z0.d }, p0, [x0]1199; CHECK-NEXT: ret1200 %op1 = load <32 x i64>, ptr %a1201 %op2 = load <32 x i64>, ptr %b1202 %res = sub <32 x i64> %op1, %op21203 store <32 x i64> %res, ptr %a1204 ret void1205}1206 1207 1208;1209; ABS1210;1211 1212; Don't use SVE for 64-bit vectors.1213define <8 x i8> @abs_v8i8(<8 x i8> %op1) vscale_range(2,0) #0 {1214; CHECK-LABEL: abs_v8i8:1215; CHECK: // %bb.0:1216; CHECK-NEXT: abs v0.8b, v0.8b1217; CHECK-NEXT: ret1218 %res = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %op1, i1 false)1219 ret <8 x i8> %res1220}1221 1222; Don't use SVE for 128-bit vectors.1223define <16 x i8> @abs_v16i8(<16 x i8> %op1) vscale_range(2,0) #0 {1224; CHECK-LABEL: abs_v16i8:1225; CHECK: // %bb.0:1226; CHECK-NEXT: abs v0.16b, v0.16b1227; CHECK-NEXT: ret1228 %res = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %op1, i1 false)1229 ret <16 x i8> %res1230}1231 1232define void @abs_v32i8(ptr %a) vscale_range(2,0) #0 {1233; CHECK-LABEL: abs_v32i8:1234; CHECK: // %bb.0:1235; CHECK-NEXT: ptrue p0.b, vl321236; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]1237; CHECK-NEXT: abs z0.b, p0/m, z0.b1238; CHECK-NEXT: st1b { z0.b }, p0, [x0]1239; CHECK-NEXT: ret1240 %op1 = load <32 x i8>, ptr %a1241 %res = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %op1, i1 false)1242 store <32 x i8> %res, ptr %a1243 ret void1244}1245 1246define void @abs_v64i8(ptr %a) #0 {1247; VBITS_GE_256-LABEL: abs_v64i8:1248; VBITS_GE_256: // %bb.0:1249; VBITS_GE_256-NEXT: ptrue p0.b, vl321250; VBITS_GE_256-NEXT: mov w8, #32 // =0x201251; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]1252; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0]1253; VBITS_GE_256-NEXT: abs z0.b, p0/m, z0.b1254; VBITS_GE_256-NEXT: abs z1.b, p0/m, z1.b1255; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]1256; VBITS_GE_256-NEXT: st1b { z1.b }, p0, [x0]1257; VBITS_GE_256-NEXT: ret1258;1259; VBITS_GE_512-LABEL: abs_v64i8:1260; VBITS_GE_512: // %bb.0:1261; VBITS_GE_512-NEXT: ptrue p0.b, vl641262; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]1263; VBITS_GE_512-NEXT: abs z0.b, p0/m, z0.b1264; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]1265; VBITS_GE_512-NEXT: ret1266 %op1 = load <64 x i8>, ptr %a1267 %res = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %op1, i1 false)1268 store <64 x i8> %res, ptr %a1269 ret void1270}1271 1272define void @abs_v128i8(ptr %a) vscale_range(8,0) #0 {1273; CHECK-LABEL: abs_v128i8:1274; CHECK: // %bb.0:1275; CHECK-NEXT: ptrue p0.b, vl1281276; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]1277; CHECK-NEXT: abs z0.b, p0/m, z0.b1278; CHECK-NEXT: st1b { z0.b }, p0, [x0]1279; CHECK-NEXT: ret1280 %op1 = load <128 x i8>, ptr %a1281 %res = call <128 x i8> @llvm.abs.v128i8(<128 x i8> %op1, i1 false)1282 store <128 x i8> %res, ptr %a1283 ret void1284}1285 1286define void @abs_v256i8(ptr %a) vscale_range(16,0) #0 {1287; CHECK-LABEL: abs_v256i8:1288; CHECK: // %bb.0:1289; CHECK-NEXT: ptrue p0.b, vl2561290; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]1291; CHECK-NEXT: abs z0.b, p0/m, z0.b1292; CHECK-NEXT: st1b { z0.b }, p0, [x0]1293; CHECK-NEXT: ret1294 %op1 = load <256 x i8>, ptr %a1295 %res = call <256 x i8> @llvm.abs.v256i8(<256 x i8> %op1, i1 false)1296 store <256 x i8> %res, ptr %a1297 ret void1298}1299 1300; Don't use SVE for 64-bit vectors.1301define <4 x i16> @abs_v4i16(<4 x i16> %op1) vscale_range(2,0) #0 {1302; CHECK-LABEL: abs_v4i16:1303; CHECK: // %bb.0:1304; CHECK-NEXT: abs v0.4h, v0.4h1305; CHECK-NEXT: ret1306 %res = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %op1, i1 false)1307 ret <4 x i16> %res1308}1309 1310; Don't use SVE for 128-bit vectors.1311define <8 x i16> @abs_v8i16(<8 x i16> %op1) vscale_range(2,0) #0 {1312; CHECK-LABEL: abs_v8i16:1313; CHECK: // %bb.0:1314; CHECK-NEXT: abs v0.8h, v0.8h1315; CHECK-NEXT: ret1316 %res = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %op1, i1 false)1317 ret <8 x i16> %res1318}1319 1320define void @abs_v16i16(ptr %a) vscale_range(2,0) #0 {1321; CHECK-LABEL: abs_v16i16:1322; CHECK: // %bb.0:1323; CHECK-NEXT: ptrue p0.h, vl161324; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1325; CHECK-NEXT: abs z0.h, p0/m, z0.h1326; CHECK-NEXT: st1h { z0.h }, p0, [x0]1327; CHECK-NEXT: ret1328 %op1 = load <16 x i16>, ptr %a1329 %res = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %op1, i1 false)1330 store <16 x i16> %res, ptr %a1331 ret void1332}1333 1334define void @abs_v32i16(ptr %a) vscale_range(2,0) #0 {1335; CHECK-LABEL: abs_v32i16:1336; CHECK: // %bb.0:1337; CHECK-NEXT: ptrue p0.h, vl161338; CHECK-NEXT: mov x8, #16 // =0x101339; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]1340; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0]1341; CHECK-NEXT: abs z0.h, p0/m, z0.h1342; CHECK-NEXT: abs z1.h, p0/m, z1.h1343; CHECK-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]1344; CHECK-NEXT: st1h { z1.h }, p0, [x0]1345; CHECK-NEXT: ret1346 %op1 = load <32 x i16>, ptr %a1347 %res = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %op1, i1 false)1348 store <32 x i16> %res, ptr %a1349 ret void1350}1351 1352define void @abs_v64i16(ptr %a) vscale_range(2,0) #0 {1353; CHECK-LABEL: abs_v64i16:1354; CHECK: // %bb.0:1355; CHECK-NEXT: ptrue p0.h, vl161356; CHECK-NEXT: mov x8, #32 // =0x201357; CHECK-NEXT: mov x9, #48 // =0x301358; CHECK-NEXT: mov x10, #16 // =0x101359; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]1360; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0, x9, lsl #1]1361; CHECK-NEXT: ld1h { z2.h }, p0/z, [x0, x10, lsl #1]1362; CHECK-NEXT: ld1h { z3.h }, p0/z, [x0]1363; CHECK-NEXT: abs z0.h, p0/m, z0.h1364; CHECK-NEXT: abs z1.h, p0/m, z1.h1365; CHECK-NEXT: abs z2.h, p0/m, z2.h1366; CHECK-NEXT: abs z3.h, p0/m, z3.h1367; CHECK-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]1368; CHECK-NEXT: st1h { z1.h }, p0, [x0, x9, lsl #1]1369; CHECK-NEXT: st1h { z2.h }, p0, [x0, x10, lsl #1]1370; CHECK-NEXT: st1h { z3.h }, p0, [x0]1371; CHECK-NEXT: ret1372 %op1 = load <64 x i16>, ptr %a1373 %res = call <64 x i16> @llvm.abs.v64i16(<64 x i16> %op1, i1 false)1374 store <64 x i16> %res, ptr %a1375 ret void1376}1377 1378define void @abs_v128i16(ptr %a) vscale_range(2,0) #0 {1379; CHECK-LABEL: abs_v128i16:1380; CHECK: // %bb.0:1381; CHECK-NEXT: ptrue p0.h, vl161382; CHECK-NEXT: mov x8, #96 // =0x601383; CHECK-NEXT: mov x9, #112 // =0x701384; CHECK-NEXT: mov x10, #64 // =0x401385; CHECK-NEXT: mov x11, #80 // =0x501386; CHECK-NEXT: mov x12, #32 // =0x201387; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]1388; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0, x9, lsl #1]1389; CHECK-NEXT: ld1h { z2.h }, p0/z, [x0, x10, lsl #1]1390; CHECK-NEXT: mov x13, #48 // =0x301391; CHECK-NEXT: mov x14, #16 // =0x101392; CHECK-NEXT: ld1h { z3.h }, p0/z, [x0, x11, lsl #1]1393; CHECK-NEXT: ld1h { z4.h }, p0/z, [x0, x12, lsl #1]1394; CHECK-NEXT: ld1h { z5.h }, p0/z, [x0, x13, lsl #1]1395; CHECK-NEXT: ld1h { z6.h }, p0/z, [x0, x14, lsl #1]1396; CHECK-NEXT: abs z0.h, p0/m, z0.h1397; CHECK-NEXT: abs z1.h, p0/m, z1.h1398; CHECK-NEXT: abs z2.h, p0/m, z2.h1399; CHECK-NEXT: abs z3.h, p0/m, z3.h1400; CHECK-NEXT: abs z4.h, p0/m, z4.h1401; CHECK-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]1402; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1403; CHECK-NEXT: st1h { z1.h }, p0, [x0, x9, lsl #1]1404; CHECK-NEXT: movprfx z1, z51405; CHECK-NEXT: abs z1.h, p0/m, z5.h1406; CHECK-NEXT: st1h { z2.h }, p0, [x0, x10, lsl #1]1407; CHECK-NEXT: movprfx z2, z61408; CHECK-NEXT: abs z2.h, p0/m, z6.h1409; CHECK-NEXT: abs z0.h, p0/m, z0.h1410; CHECK-NEXT: st1h { z3.h }, p0, [x0, x11, lsl #1]1411; CHECK-NEXT: st1h { z4.h }, p0, [x0, x12, lsl #1]1412; CHECK-NEXT: st1h { z1.h }, p0, [x0, x13, lsl #1]1413; CHECK-NEXT: st1h { z2.h }, p0, [x0, x14, lsl #1]1414; CHECK-NEXT: st1h { z0.h }, p0, [x0]1415; CHECK-NEXT: ret1416 %op1 = load <128 x i16>, ptr %a1417 %res = call <128 x i16> @llvm.abs.v128i16(<128 x i16> %op1, i1 false)1418 store <128 x i16> %res, ptr %a1419 ret void1420}1421 1422; Don't use SVE for 64-bit vectors.1423define <2 x i32> @abs_v2i32(<2 x i32> %op1) vscale_range(2,0) #0 {1424; CHECK-LABEL: abs_v2i32:1425; CHECK: // %bb.0:1426; CHECK-NEXT: abs v0.2s, v0.2s1427; CHECK-NEXT: ret1428 %res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %op1, i1 false)1429 ret <2 x i32> %res1430}1431 1432; Don't use SVE for 128-bit vectors.1433define <4 x i32> @abs_v4i32(<4 x i32> %op1) vscale_range(2,0) #0 {1434; CHECK-LABEL: abs_v4i32:1435; CHECK: // %bb.0:1436; CHECK-NEXT: abs v0.4s, v0.4s1437; CHECK-NEXT: ret1438 %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %op1, i1 false)1439 ret <4 x i32> %res1440}1441 1442define void @abs_v8i32(ptr %a) vscale_range(2,0) #0 {1443; CHECK-LABEL: abs_v8i32:1444; CHECK: // %bb.0:1445; CHECK-NEXT: ptrue p0.s, vl81446; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1447; CHECK-NEXT: abs z0.s, p0/m, z0.s1448; CHECK-NEXT: st1w { z0.s }, p0, [x0]1449; CHECK-NEXT: ret1450 %op1 = load <8 x i32>, ptr %a1451 %res = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %op1, i1 false)1452 store <8 x i32> %res, ptr %a1453 ret void1454}1455 1456define void @abs_v16i32(ptr %a) #0 {1457; VBITS_GE_256-LABEL: abs_v16i32:1458; VBITS_GE_256: // %bb.0:1459; VBITS_GE_256-NEXT: ptrue p0.s, vl81460; VBITS_GE_256-NEXT: mov x8, #8 // =0x81461; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]1462; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]1463; VBITS_GE_256-NEXT: abs z0.s, p0/m, z0.s1464; VBITS_GE_256-NEXT: abs z1.s, p0/m, z1.s1465; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]1466; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]1467; VBITS_GE_256-NEXT: ret1468;1469; VBITS_GE_512-LABEL: abs_v16i32:1470; VBITS_GE_512: // %bb.0:1471; VBITS_GE_512-NEXT: ptrue p0.s, vl161472; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]1473; VBITS_GE_512-NEXT: abs z0.s, p0/m, z0.s1474; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]1475; VBITS_GE_512-NEXT: ret1476 %op1 = load <16 x i32>, ptr %a1477 %res = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %op1, i1 false)1478 store <16 x i32> %res, ptr %a1479 ret void1480}1481 1482define void @abs_v32i32(ptr %a) vscale_range(8,0) #0 {1483; CHECK-LABEL: abs_v32i32:1484; CHECK: // %bb.0:1485; CHECK-NEXT: ptrue p0.s, vl321486; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1487; CHECK-NEXT: abs z0.s, p0/m, z0.s1488; CHECK-NEXT: st1w { z0.s }, p0, [x0]1489; CHECK-NEXT: ret1490 %op1 = load <32 x i32>, ptr %a1491 %res = call <32 x i32> @llvm.abs.v32i32(<32 x i32> %op1, i1 false)1492 store <32 x i32> %res, ptr %a1493 ret void1494}1495 1496define void @abs_v64i32(ptr %a) vscale_range(16,0) #0 {1497; CHECK-LABEL: abs_v64i32:1498; CHECK: // %bb.0:1499; CHECK-NEXT: ptrue p0.s, vl641500; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1501; CHECK-NEXT: abs z0.s, p0/m, z0.s1502; CHECK-NEXT: st1w { z0.s }, p0, [x0]1503; CHECK-NEXT: ret1504 %op1 = load <64 x i32>, ptr %a1505 %res = call <64 x i32> @llvm.abs.v64i32(<64 x i32> %op1, i1 false)1506 store <64 x i32> %res, ptr %a1507 ret void1508}1509 1510; Don't use SVE for 64-bit vectors.1511define <1 x i64> @abs_v1i64(<1 x i64> %op1) vscale_range(2,0) #0 {1512; CHECK-LABEL: abs_v1i64:1513; CHECK: // %bb.0:1514; CHECK-NEXT: abs d0, d01515; CHECK-NEXT: ret1516 %res = call <1 x i64> @llvm.abs.v1i64(<1 x i64> %op1, i1 false)1517 ret <1 x i64> %res1518}1519 1520; Don't use SVE for 128-bit vectors.1521define <2 x i64> @abs_v2i64(<2 x i64> %op1) vscale_range(2,0) #0 {1522; CHECK-LABEL: abs_v2i64:1523; CHECK: // %bb.0:1524; CHECK-NEXT: abs v0.2d, v0.2d1525; CHECK-NEXT: ret1526 %res = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %op1, i1 false)1527 ret <2 x i64> %res1528}1529 1530define void @abs_v4i64(ptr %a) vscale_range(2,0) #0 {1531; CHECK-LABEL: abs_v4i64:1532; CHECK: // %bb.0:1533; CHECK-NEXT: ptrue p0.d, vl41534; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1535; CHECK-NEXT: abs z0.d, p0/m, z0.d1536; CHECK-NEXT: st1d { z0.d }, p0, [x0]1537; CHECK-NEXT: ret1538 %op1 = load <4 x i64>, ptr %a1539 %res = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %op1, i1 false)1540 store <4 x i64> %res, ptr %a1541 ret void1542}1543 1544define void @abs_v8i64(ptr %a) #0 {1545; VBITS_GE_256-LABEL: abs_v8i64:1546; VBITS_GE_256: // %bb.0:1547; VBITS_GE_256-NEXT: ptrue p0.d, vl41548; VBITS_GE_256-NEXT: mov x8, #4 // =0x41549; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]1550; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]1551; VBITS_GE_256-NEXT: abs z0.d, p0/m, z0.d1552; VBITS_GE_256-NEXT: abs z1.d, p0/m, z1.d1553; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]1554; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]1555; VBITS_GE_256-NEXT: ret1556;1557; VBITS_GE_512-LABEL: abs_v8i64:1558; VBITS_GE_512: // %bb.0:1559; VBITS_GE_512-NEXT: ptrue p0.d, vl81560; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]1561; VBITS_GE_512-NEXT: abs z0.d, p0/m, z0.d1562; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]1563; VBITS_GE_512-NEXT: ret1564 %op1 = load <8 x i64>, ptr %a1565 %res = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %op1, i1 false)1566 store <8 x i64> %res, ptr %a1567 ret void1568}1569 1570define void @abs_v16i64(ptr %a) vscale_range(8,0) #0 {1571; CHECK-LABEL: abs_v16i64:1572; CHECK: // %bb.0:1573; CHECK-NEXT: ptrue p0.d, vl161574; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1575; CHECK-NEXT: abs z0.d, p0/m, z0.d1576; CHECK-NEXT: st1d { z0.d }, p0, [x0]1577; CHECK-NEXT: ret1578 %op1 = load <16 x i64>, ptr %a1579 %res = call <16 x i64> @llvm.abs.v16i64(<16 x i64> %op1, i1 false)1580 store <16 x i64> %res, ptr %a1581 ret void1582}1583 1584define void @abs_v32i64(ptr %a) vscale_range(16,0) #0 {1585; CHECK-LABEL: abs_v32i64:1586; CHECK: // %bb.0:1587; CHECK-NEXT: ptrue p0.d, vl321588; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1589; CHECK-NEXT: abs z0.d, p0/m, z0.d1590; CHECK-NEXT: st1d { z0.d }, p0, [x0]1591; CHECK-NEXT: ret1592 %op1 = load <32 x i64>, ptr %a1593 %res = call <32 x i64> @llvm.abs.v32i64(<32 x i64> %op1, i1 false)1594 store <32 x i64> %res, ptr %a1595 ret void1596}1597 1598declare <8 x i8> @llvm.abs.v8i8(<8 x i8>, i1)1599declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1)1600declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1)1601declare <64 x i8> @llvm.abs.v64i8(<64 x i8>, i1)1602declare <128 x i8> @llvm.abs.v128i8(<128 x i8>, i1)1603declare <256 x i8> @llvm.abs.v256i8(<256 x i8>, i1)1604declare <4 x i16> @llvm.abs.v4i16(<4 x i16>, i1)1605declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)1606declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1)1607declare <32 x i16> @llvm.abs.v32i16(<32 x i16>, i1)1608declare <64 x i16> @llvm.abs.v64i16(<64 x i16>, i1)1609declare <128 x i16> @llvm.abs.v128i16(<128 x i16>, i1)1610declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1)1611declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)1612declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)1613declare <16 x i32> @llvm.abs.v16i32(<16 x i32>, i1)1614declare <32 x i32> @llvm.abs.v32i32(<32 x i32>, i1)1615declare <64 x i32> @llvm.abs.v64i32(<64 x i32>, i1)1616declare <1 x i64> @llvm.abs.v1i64(<1 x i64>, i1)1617declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)1618declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)1619declare <8 x i64> @llvm.abs.v8i64(<8 x i64>, i1)1620declare <16 x i64> @llvm.abs.v16i64(<16 x i64>, i1)1621declare <32 x i64> @llvm.abs.v32i64(<32 x i64>, i1)1622 1623attributes #0 = { "target-features"="+sve" }1624