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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; Although SVE immediate packing should be fully tested using scalable vectors,7; these tests protects against the possibility that scalable nodes, resulting8; from lowering fixed length vector operations, trigger different isel patterns.9 10;11; ADD12;13 14define void @add_v64i8(ptr %a) #0 {15; CHECK-LABEL: add_v64i8:16; CHECK: // %bb.0:17; CHECK-NEXT: ptrue p0.b, vl6418; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]19; CHECK-NEXT: add z0.b, z0.b, #7 // =0x720; CHECK-NEXT: st1b { z0.b }, p0, [x0]21; CHECK-NEXT: ret22 %op1 = load <64 x i8>, ptr %a23 %res = add <64 x i8> %op1, splat (i8 7)24 store <64 x i8> %res, ptr %a25 ret void26}27 28define void @add_v32i16(ptr %a) #0 {29; CHECK-LABEL: add_v32i16:30; CHECK: // %bb.0:31; CHECK-NEXT: ptrue p0.h, vl3232; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]33; CHECK-NEXT: add z0.h, z0.h, #15 // =0xf34; CHECK-NEXT: st1h { z0.h }, p0, [x0]35; CHECK-NEXT: ret36 %op1 = load <32 x i16>, ptr %a37 %res = add <32 x i16> %op1, splat (i16 15)38 store <32 x i16> %res, ptr %a39 ret void40}41 42define void @add_v16i32(ptr %a) #0 {43; CHECK-LABEL: add_v16i32:44; CHECK: // %bb.0:45; CHECK-NEXT: ptrue p0.s, vl1646; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]47; CHECK-NEXT: add z0.s, z0.s, #31 // =0x1f48; CHECK-NEXT: st1w { z0.s }, p0, [x0]49; CHECK-NEXT: ret50 %op1 = load <16 x i32>, ptr %a51 %res = add <16 x i32> %op1, splat (i32 31)52 store <16 x i32> %res, ptr %a53 ret void54}55 56define void @add_v8i64(ptr %a) #0 {57; CHECK-LABEL: add_v8i64:58; CHECK: // %bb.0:59; CHECK-NEXT: ptrue p0.d, vl860; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]61; CHECK-NEXT: add z0.d, z0.d, #63 // =0x3f62; CHECK-NEXT: st1d { z0.d }, p0, [x0]63; CHECK-NEXT: ret64 %op1 = load <8 x i64>, ptr %a65 %res = add <8 x i64> %op1, splat (i64 63)66 store <8 x i64> %res, ptr %a67 ret void68}69 70;71; AND72;73 74define void @and_v64i8(ptr %a) #0 {75; CHECK-LABEL: and_v64i8:76; CHECK: // %bb.0:77; CHECK-NEXT: ptrue p0.b, vl6478; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]79; CHECK-NEXT: and z0.b, z0.b, #0x780; CHECK-NEXT: st1b { z0.b }, p0, [x0]81; CHECK-NEXT: ret82 %op1 = load <64 x i8>, ptr %a83 %res = and <64 x i8> %op1, splat (i8 7)84 store <64 x i8> %res, ptr %a85 ret void86}87 88define void @and_v32i16(ptr %a) #0 {89; CHECK-LABEL: and_v32i16:90; CHECK: // %bb.0:91; CHECK-NEXT: ptrue p0.h, vl3292; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]93; CHECK-NEXT: and z0.h, z0.h, #0xf94; CHECK-NEXT: st1h { z0.h }, p0, [x0]95; CHECK-NEXT: ret96 %op1 = load <32 x i16>, ptr %a97 %res = and <32 x i16> %op1, splat (i16 15)98 store <32 x i16> %res, ptr %a99 ret void100}101 102define void @and_v16i32(ptr %a) #0 {103; CHECK-LABEL: and_v16i32:104; CHECK: // %bb.0:105; CHECK-NEXT: ptrue p0.s, vl16106; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]107; CHECK-NEXT: and z0.s, z0.s, #0x1f108; CHECK-NEXT: st1w { z0.s }, p0, [x0]109; CHECK-NEXT: ret110 %op1 = load <16 x i32>, ptr %a111 %res = and <16 x i32> %op1, splat (i32 31)112 store <16 x i32> %res, ptr %a113 ret void114}115 116define void @and_v8i64(ptr %a) #0 {117; CHECK-LABEL: and_v8i64:118; CHECK: // %bb.0:119; CHECK-NEXT: ptrue p0.d, vl8120; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]121; CHECK-NEXT: and z0.d, z0.d, #0x3f122; CHECK-NEXT: st1d { z0.d }, p0, [x0]123; CHECK-NEXT: ret124 %op1 = load <8 x i64>, ptr %a125 %res = and <8 x i64> %op1, splat (i64 63)126 store <8 x i64> %res, ptr %a127 ret void128}129 130;131; ASHR132;133 134define void @ashr_v64i8(ptr %a) #0 {135; CHECK-LABEL: ashr_v64i8:136; CHECK: // %bb.0:137; CHECK-NEXT: ptrue p0.b, vl64138; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]139; CHECK-NEXT: asr z0.b, z0.b, #7140; CHECK-NEXT: st1b { z0.b }, p0, [x0]141; CHECK-NEXT: ret142 %op1 = load <64 x i8>, ptr %a143 %res = ashr <64 x i8> %op1, splat (i8 7)144 store <64 x i8> %res, ptr %a145 ret void146}147 148define void @ashr_v32i16(ptr %a) #0 {149; CHECK-LABEL: ashr_v32i16:150; CHECK: // %bb.0:151; CHECK-NEXT: ptrue p0.h, vl32152; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]153; CHECK-NEXT: asr z0.h, z0.h, #15154; CHECK-NEXT: st1h { z0.h }, p0, [x0]155; CHECK-NEXT: ret156 %op1 = load <32 x i16>, ptr %a157 %res = ashr <32 x i16> %op1, splat (i16 15)158 store <32 x i16> %res, ptr %a159 ret void160}161 162define void @ashr_v16i32(ptr %a) #0 {163; CHECK-LABEL: ashr_v16i32:164; CHECK: // %bb.0:165; CHECK-NEXT: ptrue p0.s, vl16166; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]167; CHECK-NEXT: asr z0.s, z0.s, #31168; CHECK-NEXT: st1w { z0.s }, p0, [x0]169; CHECK-NEXT: ret170 %op1 = load <16 x i32>, ptr %a171 %res = ashr <16 x i32> %op1, splat (i32 31)172 store <16 x i32> %res, ptr %a173 ret void174}175 176define void @ashr_v8i64(ptr %a) #0 {177; CHECK-LABEL: ashr_v8i64:178; CHECK: // %bb.0:179; CHECK-NEXT: ptrue p0.d, vl8180; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]181; CHECK-NEXT: asr z0.d, z0.d, #63182; CHECK-NEXT: st1d { z0.d }, p0, [x0]183; CHECK-NEXT: ret184 %op1 = load <8 x i64>, ptr %a185 %res = ashr <8 x i64> %op1, splat (i64 63)186 store <8 x i64> %res, ptr %a187 ret void188}189 190;191; ICMP192;193 194define void @icmp_eq_v64i8(ptr %a) #0 {195; CHECK-LABEL: icmp_eq_v64i8:196; CHECK: // %bb.0:197; CHECK-NEXT: ptrue p0.b, vl64198; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]199; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #7200; CHECK-NEXT: mov z0.b, p1/z, #-1 // =0xffffffffffffffff201; CHECK-NEXT: st1b { z0.b }, p0, [x0]202; CHECK-NEXT: ret203 %op1 = load <64 x i8>, ptr %a204 %cmp = icmp eq <64 x i8> %op1, splat (i8 7)205 %res = sext <64 x i1> %cmp to <64 x i8>206 store <64 x i8> %res, ptr %a207 ret void208}209 210define void @icmp_sge_v32i16(ptr %a) #0 {211; CHECK-LABEL: icmp_sge_v32i16:212; CHECK: // %bb.0:213; CHECK-NEXT: ptrue p0.h, vl32214; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]215; CHECK-NEXT: cmpge p1.h, p0/z, z0.h, #15216; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff217; CHECK-NEXT: st1h { z0.h }, p0, [x0]218; CHECK-NEXT: ret219 %op1 = load <32 x i16>, ptr %a220 %cmp = icmp sge <32 x i16> %op1, splat (i16 15)221 %res = sext <32 x i1> %cmp to <32 x i16>222 store <32 x i16> %res, ptr %a223 ret void224}225 226define void @icmp_sgt_v16i32(ptr %a) #0 {227; CHECK-LABEL: icmp_sgt_v16i32:228; CHECK: // %bb.0:229; CHECK-NEXT: ptrue p0.s, vl16230; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]231; CHECK-NEXT: cmpgt p1.s, p0/z, z0.s, #-16232; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff233; CHECK-NEXT: st1w { z0.s }, p0, [x0]234; CHECK-NEXT: ret235 %op1 = load <16 x i32>, ptr %a236 %cmp = icmp sgt <16 x i32> %op1, splat (i32 -16)237 %res = sext <16 x i1> %cmp to <16 x i32>238 store <16 x i32> %res, ptr %a239 ret void240}241 242define void @icmp_ult_v8i64(ptr %a) #0 {243; CHECK-LABEL: icmp_ult_v8i64:244; CHECK: // %bb.0:245; CHECK-NEXT: ptrue p0.d, vl8246; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]247; CHECK-NEXT: cmplo p1.d, p0/z, z0.d, #63248; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff249; CHECK-NEXT: st1d { z0.d }, p0, [x0]250; CHECK-NEXT: ret251 %op1 = load <8 x i64>, ptr %a252 %cmp = icmp ult <8 x i64> %op1, splat (i64 63)253 %res = sext <8 x i1> %cmp to <8 x i64>254 store <8 x i64> %res, ptr %a255 ret void256}257 258;259; LSHR260;261 262define void @lshr_v64i8(ptr %a) #0 {263; CHECK-LABEL: lshr_v64i8:264; CHECK: // %bb.0:265; CHECK-NEXT: ptrue p0.b, vl64266; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]267; CHECK-NEXT: lsr z0.b, z0.b, #7268; CHECK-NEXT: st1b { z0.b }, p0, [x0]269; CHECK-NEXT: ret270 %op1 = load <64 x i8>, ptr %a271 %res = lshr <64 x i8> %op1, splat (i8 7)272 store <64 x i8> %res, ptr %a273 ret void274}275 276define void @lshr_v32i16(ptr %a) #0 {277; CHECK-LABEL: lshr_v32i16:278; CHECK: // %bb.0:279; CHECK-NEXT: ptrue p0.h, vl32280; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]281; CHECK-NEXT: lsr z0.h, z0.h, #15282; CHECK-NEXT: st1h { z0.h }, p0, [x0]283; CHECK-NEXT: ret284 %op1 = load <32 x i16>, ptr %a285 %res = lshr <32 x i16> %op1, splat (i16 15)286 store <32 x i16> %res, ptr %a287 ret void288}289 290define void @lshr_v16i32(ptr %a) #0 {291; CHECK-LABEL: lshr_v16i32:292; CHECK: // %bb.0:293; CHECK-NEXT: ptrue p0.s, vl16294; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]295; CHECK-NEXT: lsr z0.s, z0.s, #31296; CHECK-NEXT: st1w { z0.s }, p0, [x0]297; CHECK-NEXT: ret298 %op1 = load <16 x i32>, ptr %a299 %res = lshr <16 x i32> %op1, splat (i32 31)300 store <16 x i32> %res, ptr %a301 ret void302}303 304define void @lshr_v8i64(ptr %a) #0 {305; CHECK-LABEL: lshr_v8i64:306; CHECK: // %bb.0:307; CHECK-NEXT: ptrue p0.d, vl8308; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]309; CHECK-NEXT: lsr z0.d, z0.d, #63310; CHECK-NEXT: st1d { z0.d }, p0, [x0]311; CHECK-NEXT: ret312 %op1 = load <8 x i64>, ptr %a313 %res = lshr <8 x i64> %op1, splat (i64 63)314 store <8 x i64> %res, ptr %a315 ret void316}317 318;319; MUL320;321 322define void @mul_v64i8(ptr %a) #0 {323; CHECK-LABEL: mul_v64i8:324; CHECK: // %bb.0:325; CHECK-NEXT: ptrue p0.b, vl64326; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]327; CHECK-NEXT: mul z0.b, z0.b, #7328; CHECK-NEXT: st1b { z0.b }, p0, [x0]329; CHECK-NEXT: ret330 %op1 = load <64 x i8>, ptr %a331 %res = mul <64 x i8> %op1, splat (i8 7)332 store <64 x i8> %res, ptr %a333 ret void334}335 336define void @mul_v32i16(ptr %a) #0 {337; CHECK-LABEL: mul_v32i16:338; CHECK: // %bb.0:339; CHECK-NEXT: ptrue p0.h, vl32340; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]341; CHECK-NEXT: mul z0.h, z0.h, #15342; CHECK-NEXT: st1h { z0.h }, p0, [x0]343; CHECK-NEXT: ret344 %op1 = load <32 x i16>, ptr %a345 %res = mul <32 x i16> %op1, splat (i16 15)346 store <32 x i16> %res, ptr %a347 ret void348}349 350define void @mul_v16i32(ptr %a) #0 {351; CHECK-LABEL: mul_v16i32:352; CHECK: // %bb.0:353; CHECK-NEXT: ptrue p0.s, vl16354; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]355; CHECK-NEXT: mul z0.s, z0.s, #31356; CHECK-NEXT: st1w { z0.s }, p0, [x0]357; CHECK-NEXT: ret358 %op1 = load <16 x i32>, ptr %a359 %res = mul <16 x i32> %op1, splat (i32 31)360 store <16 x i32> %res, ptr %a361 ret void362}363 364define void @mul_v8i64(ptr %a) #0 {365; CHECK-LABEL: mul_v8i64:366; CHECK: // %bb.0:367; CHECK-NEXT: ptrue p0.d, vl8368; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]369; CHECK-NEXT: mul z0.d, z0.d, #63370; CHECK-NEXT: st1d { z0.d }, p0, [x0]371; CHECK-NEXT: ret372 %op1 = load <8 x i64>, ptr %a373 %res = mul <8 x i64> %op1, splat (i64 63)374 store <8 x i64> %res, ptr %a375 ret void376}377 378;379; OR380;381 382define void @or_v64i8(ptr %a) #0 {383; CHECK-LABEL: or_v64i8:384; CHECK: // %bb.0:385; CHECK-NEXT: ptrue p0.b, vl64386; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]387; CHECK-NEXT: orr z0.b, z0.b, #0x7388; CHECK-NEXT: st1b { z0.b }, p0, [x0]389; CHECK-NEXT: ret390 %op1 = load <64 x i8>, ptr %a391 %res = or <64 x i8> %op1, splat (i8 7)392 store <64 x i8> %res, ptr %a393 ret void394}395 396define void @or_v32i16(ptr %a) #0 {397; CHECK-LABEL: or_v32i16:398; CHECK: // %bb.0:399; CHECK-NEXT: ptrue p0.h, vl32400; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]401; CHECK-NEXT: orr z0.h, z0.h, #0xf402; CHECK-NEXT: st1h { z0.h }, p0, [x0]403; CHECK-NEXT: ret404 %op1 = load <32 x i16>, ptr %a405 %res = or <32 x i16> %op1, splat (i16 15)406 store <32 x i16> %res, ptr %a407 ret void408}409 410define void @or_v16i32(ptr %a) #0 {411; CHECK-LABEL: or_v16i32:412; CHECK: // %bb.0:413; CHECK-NEXT: ptrue p0.s, vl16414; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]415; CHECK-NEXT: orr z0.s, z0.s, #0x1f416; CHECK-NEXT: st1w { z0.s }, p0, [x0]417; CHECK-NEXT: ret418 %op1 = load <16 x i32>, ptr %a419 %res = or <16 x i32> %op1, splat (i32 31)420 store <16 x i32> %res, ptr %a421 ret void422}423 424define void @or_v8i64(ptr %a) #0 {425; CHECK-LABEL: or_v8i64:426; CHECK: // %bb.0:427; CHECK-NEXT: ptrue p0.d, vl8428; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]429; CHECK-NEXT: orr z0.d, z0.d, #0x3f430; CHECK-NEXT: st1d { z0.d }, p0, [x0]431; CHECK-NEXT: ret432 %op1 = load <8 x i64>, ptr %a433 %res = or <8 x i64> %op1, splat (i64 63)434 store <8 x i64> %res, ptr %a435 ret void436}437 438;439; SHL440;441 442define void @shl_v64i8(ptr %a) #0 {443; CHECK-LABEL: shl_v64i8:444; CHECK: // %bb.0:445; CHECK-NEXT: ptrue p0.b, vl64446; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]447; CHECK-NEXT: lsl z0.b, z0.b, #7448; CHECK-NEXT: st1b { z0.b }, p0, [x0]449; CHECK-NEXT: ret450 %op1 = load <64 x i8>, ptr %a451 %res = shl <64 x i8> %op1, splat (i8 7)452 store <64 x i8> %res, ptr %a453 ret void454}455 456define void @shl_v32i16(ptr %a) #0 {457; CHECK-LABEL: shl_v32i16:458; CHECK: // %bb.0:459; CHECK-NEXT: ptrue p0.h, vl32460; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]461; CHECK-NEXT: lsl z0.h, z0.h, #15462; CHECK-NEXT: st1h { z0.h }, p0, [x0]463; CHECK-NEXT: ret464 %op1 = load <32 x i16>, ptr %a465 %res = shl <32 x i16> %op1, splat (i16 15)466 store <32 x i16> %res, ptr %a467 ret void468}469 470define void @shl_v16i32(ptr %a) #0 {471; CHECK-LABEL: shl_v16i32:472; CHECK: // %bb.0:473; CHECK-NEXT: ptrue p0.s, vl16474; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]475; CHECK-NEXT: lsl z0.s, z0.s, #31476; CHECK-NEXT: st1w { z0.s }, p0, [x0]477; CHECK-NEXT: ret478 %op1 = load <16 x i32>, ptr %a479 %res = shl <16 x i32> %op1, splat (i32 31)480 store <16 x i32> %res, ptr %a481 ret void482}483 484define void @shl_v8i64(ptr %a) #0 {485; CHECK-LABEL: shl_v8i64:486; CHECK: // %bb.0:487; CHECK-NEXT: ptrue p0.d, vl8488; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]489; CHECK-NEXT: lsl z0.d, z0.d, #63490; CHECK-NEXT: st1d { z0.d }, p0, [x0]491; CHECK-NEXT: ret492 %op1 = load <8 x i64>, ptr %a493 %res = shl <8 x i64> %op1, splat (i64 63)494 store <8 x i64> %res, ptr %a495 ret void496}497 498;499; SMAX500;501 502define void @smax_v64i8(ptr %a) #0 {503; CHECK-LABEL: smax_v64i8:504; CHECK: // %bb.0:505; CHECK-NEXT: ptrue p0.b, vl64506; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]507; CHECK-NEXT: smax z0.b, z0.b, #7508; CHECK-NEXT: st1b { z0.b }, p0, [x0]509; CHECK-NEXT: ret510 %op1 = load <64 x i8>, ptr %a511 %res = call <64 x i8> @llvm.smax.v64i8(<64 x i8> %op1, <64 x i8> splat (i8 7))512 store <64 x i8> %res, ptr %a513 ret void514}515 516define void @smax_v32i16(ptr %a) #0 {517; CHECK-LABEL: smax_v32i16:518; CHECK: // %bb.0:519; CHECK-NEXT: ptrue p0.h, vl32520; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]521; CHECK-NEXT: smax z0.h, z0.h, #15522; CHECK-NEXT: st1h { z0.h }, p0, [x0]523; CHECK-NEXT: ret524 %op1 = load <32 x i16>, ptr %a525 %res = call <32 x i16> @llvm.smax.v32i16(<32 x i16> %op1, <32 x i16> splat (i16 15))526 store <32 x i16> %res, ptr %a527 ret void528}529 530define void @smax_v16i32(ptr %a) #0 {531; CHECK-LABEL: smax_v16i32:532; CHECK: // %bb.0:533; CHECK-NEXT: ptrue p0.s, vl16534; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]535; CHECK-NEXT: smax z0.s, z0.s, #31536; CHECK-NEXT: st1w { z0.s }, p0, [x0]537; CHECK-NEXT: ret538 %op1 = load <16 x i32>, ptr %a539 %res = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %op1, <16 x i32> splat (i32 31))540 store <16 x i32> %res, ptr %a541 ret void542}543 544define void @smax_v8i64(ptr %a) #0 {545; CHECK-LABEL: smax_v8i64:546; CHECK: // %bb.0:547; CHECK-NEXT: ptrue p0.d, vl8548; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]549; CHECK-NEXT: smax z0.d, z0.d, #63550; CHECK-NEXT: st1d { z0.d }, p0, [x0]551; CHECK-NEXT: ret552 %op1 = load <8 x i64>, ptr %a553 %res = call <8 x i64> @llvm.smax.v8i64(<8 x i64> %op1, <8 x i64> splat (i64 63))554 store <8 x i64> %res, ptr %a555 ret void556}557 558;559; SMIN560;561 562define void @smin_v64i8(ptr %a) #0 {563; CHECK-LABEL: smin_v64i8:564; CHECK: // %bb.0:565; CHECK-NEXT: ptrue p0.b, vl64566; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]567; CHECK-NEXT: smin z0.b, z0.b, #7568; CHECK-NEXT: st1b { z0.b }, p0, [x0]569; CHECK-NEXT: ret570 %op1 = load <64 x i8>, ptr %a571 %res = call <64 x i8> @llvm.smin.v64i8(<64 x i8> %op1, <64 x i8> splat (i8 7))572 store <64 x i8> %res, ptr %a573 ret void574}575 576define void @smin_v32i16(ptr %a) #0 {577; CHECK-LABEL: smin_v32i16:578; CHECK: // %bb.0:579; CHECK-NEXT: ptrue p0.h, vl32580; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]581; CHECK-NEXT: smin z0.h, z0.h, #15582; CHECK-NEXT: st1h { z0.h }, p0, [x0]583; CHECK-NEXT: ret584 %op1 = load <32 x i16>, ptr %a585 %res = call <32 x i16> @llvm.smin.v32i16(<32 x i16> %op1, <32 x i16> splat (i16 15))586 store <32 x i16> %res, ptr %a587 ret void588}589 590define void @smin_v16i32(ptr %a) #0 {591; CHECK-LABEL: smin_v16i32:592; CHECK: // %bb.0:593; CHECK-NEXT: ptrue p0.s, vl16594; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]595; CHECK-NEXT: smin z0.s, z0.s, #31596; CHECK-NEXT: st1w { z0.s }, p0, [x0]597; CHECK-NEXT: ret598 %op1 = load <16 x i32>, ptr %a599 %res = call <16 x i32> @llvm.smin.v16i32(<16 x i32> %op1, <16 x i32> splat (i32 31))600 store <16 x i32> %res, ptr %a601 ret void602}603 604define void @smin_v8i64(ptr %a) #0 {605; CHECK-LABEL: smin_v8i64:606; CHECK: // %bb.0:607; CHECK-NEXT: ptrue p0.d, vl8608; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]609; CHECK-NEXT: smin z0.d, z0.d, #63610; CHECK-NEXT: st1d { z0.d }, p0, [x0]611; CHECK-NEXT: ret612 %op1 = load <8 x i64>, ptr %a613 %res = call <8 x i64> @llvm.smin.v8i64(<8 x i64> %op1, <8 x i64> splat (i64 63))614 store <8 x i64> %res, ptr %a615 ret void616}617 618;619; SUB620;621 622define void @sub_v64i8(ptr %a) #0 {623; CHECK-LABEL: sub_v64i8:624; CHECK: // %bb.0:625; CHECK-NEXT: ptrue p0.b, vl64626; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]627; CHECK-NEXT: sub z0.b, z0.b, #7 // =0x7628; CHECK-NEXT: st1b { z0.b }, p0, [x0]629; CHECK-NEXT: ret630 %op1 = load <64 x i8>, ptr %a631 %res = sub <64 x i8> %op1, splat (i8 7)632 store <64 x i8> %res, ptr %a633 ret void634}635 636define void @sub_v32i16(ptr %a) #0 {637; CHECK-LABEL: sub_v32i16:638; CHECK: // %bb.0:639; CHECK-NEXT: ptrue p0.h, vl32640; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]641; CHECK-NEXT: sub z0.h, z0.h, #15 // =0xf642; CHECK-NEXT: st1h { z0.h }, p0, [x0]643; CHECK-NEXT: ret644 %op1 = load <32 x i16>, ptr %a645 %res = sub <32 x i16> %op1, splat (i16 15)646 store <32 x i16> %res, ptr %a647 ret void648}649 650define void @sub_v16i32(ptr %a) #0 {651; CHECK-LABEL: sub_v16i32:652; CHECK: // %bb.0:653; CHECK-NEXT: ptrue p0.s, vl16654; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]655; CHECK-NEXT: sub z0.s, z0.s, #31 // =0x1f656; CHECK-NEXT: st1w { z0.s }, p0, [x0]657; CHECK-NEXT: ret658 %op1 = load <16 x i32>, ptr %a659 %res = sub <16 x i32> %op1, splat (i32 31)660 store <16 x i32> %res, ptr %a661 ret void662}663 664define void @sub_v8i64(ptr %a) #0 {665; CHECK-LABEL: sub_v8i64:666; CHECK: // %bb.0:667; CHECK-NEXT: ptrue p0.d, vl8668; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]669; CHECK-NEXT: sub z0.d, z0.d, #63 // =0x3f670; CHECK-NEXT: st1d { z0.d }, p0, [x0]671; CHECK-NEXT: ret672 %op1 = load <8 x i64>, ptr %a673 %res = sub <8 x i64> %op1, splat (i64 63)674 store <8 x i64> %res, ptr %a675 ret void676}677 678;679; UMAX680;681 682define void @umax_v64i8(ptr %a) #0 {683; CHECK-LABEL: umax_v64i8:684; CHECK: // %bb.0:685; CHECK-NEXT: ptrue p0.b, vl64686; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]687; CHECK-NEXT: umax z0.b, z0.b, #7688; CHECK-NEXT: st1b { z0.b }, p0, [x0]689; CHECK-NEXT: ret690 %op1 = load <64 x i8>, ptr %a691 %res = call <64 x i8> @llvm.umax.v64i8(<64 x i8> %op1, <64 x i8> splat (i8 7))692 store <64 x i8> %res, ptr %a693 ret void694}695 696define void @umax_v32i16(ptr %a) #0 {697; CHECK-LABEL: umax_v32i16:698; CHECK: // %bb.0:699; CHECK-NEXT: ptrue p0.h, vl32700; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]701; CHECK-NEXT: umax z0.h, z0.h, #15702; CHECK-NEXT: st1h { z0.h }, p0, [x0]703; CHECK-NEXT: ret704 %op1 = load <32 x i16>, ptr %a705 %res = call <32 x i16> @llvm.umax.v32i16(<32 x i16> %op1, <32 x i16> splat (i16 15))706 store <32 x i16> %res, ptr %a707 ret void708}709 710define void @umax_v16i32(ptr %a) #0 {711; CHECK-LABEL: umax_v16i32:712; CHECK: // %bb.0:713; CHECK-NEXT: ptrue p0.s, vl16714; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]715; CHECK-NEXT: umax z0.s, z0.s, #31716; CHECK-NEXT: st1w { z0.s }, p0, [x0]717; CHECK-NEXT: ret718 %op1 = load <16 x i32>, ptr %a719 %res = call <16 x i32> @llvm.umax.v16i32(<16 x i32> %op1, <16 x i32> splat (i32 31))720 store <16 x i32> %res, ptr %a721 ret void722}723 724define void @umax_v8i64(ptr %a) #0 {725; CHECK-LABEL: umax_v8i64:726; CHECK: // %bb.0:727; CHECK-NEXT: ptrue p0.d, vl8728; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]729; CHECK-NEXT: umax z0.d, z0.d, #63730; CHECK-NEXT: st1d { z0.d }, p0, [x0]731; CHECK-NEXT: ret732 %op1 = load <8 x i64>, ptr %a733 %res = call <8 x i64> @llvm.umax.v8i64(<8 x i64> %op1, <8 x i64> splat (i64 63))734 store <8 x i64> %res, ptr %a735 ret void736}737 738;739; UMIN740;741 742define void @umin_v64i8(ptr %a) #0 {743; CHECK-LABEL: umin_v64i8:744; CHECK: // %bb.0:745; CHECK-NEXT: ptrue p0.b, vl64746; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]747; CHECK-NEXT: umin z0.b, z0.b, #7748; CHECK-NEXT: st1b { z0.b }, p0, [x0]749; CHECK-NEXT: ret750 %op1 = load <64 x i8>, ptr %a751 %res = call <64 x i8> @llvm.umin.v64i8(<64 x i8> %op1, <64 x i8> splat (i8 7))752 store <64 x i8> %res, ptr %a753 ret void754}755 756define void @umin_v32i16(ptr %a) #0 {757; CHECK-LABEL: umin_v32i16:758; CHECK: // %bb.0:759; CHECK-NEXT: ptrue p0.h, vl32760; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]761; CHECK-NEXT: umin z0.h, z0.h, #15762; CHECK-NEXT: st1h { z0.h }, p0, [x0]763; CHECK-NEXT: ret764 %op1 = load <32 x i16>, ptr %a765 %res = call <32 x i16> @llvm.umin.v32i16(<32 x i16> %op1, <32 x i16> splat (i16 15))766 store <32 x i16> %res, ptr %a767 ret void768}769 770define void @umin_v16i32(ptr %a) #0 {771; CHECK-LABEL: umin_v16i32:772; CHECK: // %bb.0:773; CHECK-NEXT: ptrue p0.s, vl16774; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]775; CHECK-NEXT: umin z0.s, z0.s, #31776; CHECK-NEXT: st1w { z0.s }, p0, [x0]777; CHECK-NEXT: ret778 %op1 = load <16 x i32>, ptr %a779 %res = call <16 x i32> @llvm.umin.v16i32(<16 x i32> %op1, <16 x i32> splat (i32 31))780 store <16 x i32> %res, ptr %a781 ret void782}783 784define void @umin_v8i64(ptr %a) #0 {785; CHECK-LABEL: umin_v8i64:786; CHECK: // %bb.0:787; CHECK-NEXT: ptrue p0.d, vl8788; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]789; CHECK-NEXT: umin z0.d, z0.d, #63790; CHECK-NEXT: st1d { z0.d }, p0, [x0]791; CHECK-NEXT: ret792 %op1 = load <8 x i64>, ptr %a793 %res = call <8 x i64> @llvm.umin.v8i64(<8 x i64> %op1, <8 x i64> splat (i64 63))794 store <8 x i64> %res, ptr %a795 ret void796}797 798;799; XOR800;801 802define void @xor_v64i8(ptr %a) #0 {803; CHECK-LABEL: xor_v64i8:804; CHECK: // %bb.0:805; CHECK-NEXT: ptrue p0.b, vl64806; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]807; CHECK-NEXT: eor z0.b, z0.b, #0x7808; CHECK-NEXT: st1b { z0.b }, p0, [x0]809; CHECK-NEXT: ret810 %op1 = load <64 x i8>, ptr %a811 %res = xor <64 x i8> %op1, splat (i8 7)812 store <64 x i8> %res, ptr %a813 ret void814}815 816define void @xor_v32i16(ptr %a) #0 {817; CHECK-LABEL: xor_v32i16:818; CHECK: // %bb.0:819; CHECK-NEXT: ptrue p0.h, vl32820; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]821; CHECK-NEXT: eor z0.h, z0.h, #0xf822; CHECK-NEXT: st1h { z0.h }, p0, [x0]823; CHECK-NEXT: ret824 %op1 = load <32 x i16>, ptr %a825 %res = xor <32 x i16> %op1, splat (i16 15)826 store <32 x i16> %res, ptr %a827 ret void828}829 830define void @xor_v16i32(ptr %a) #0 {831; CHECK-LABEL: xor_v16i32:832; CHECK: // %bb.0:833; CHECK-NEXT: ptrue p0.s, vl16834; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]835; CHECK-NEXT: eor z0.s, z0.s, #0x1f836; CHECK-NEXT: st1w { z0.s }, p0, [x0]837; CHECK-NEXT: ret838 %op1 = load <16 x i32>, ptr %a839 %res = xor <16 x i32> %op1, splat (i32 31)840 store <16 x i32> %res, ptr %a841 ret void842}843 844define void @xor_v8i64(ptr %a) #0 {845; CHECK-LABEL: xor_v8i64:846; CHECK: // %bb.0:847; CHECK-NEXT: ptrue p0.d, vl8848; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]849; CHECK-NEXT: eor z0.d, z0.d, #0x3f850; CHECK-NEXT: st1d { z0.d }, p0, [x0]851; CHECK-NEXT: ret852 %op1 = load <8 x i64>, ptr %a853 %res = xor <8 x i64> %op1, splat (i64 63)854 store <8 x i64> %res, ptr %a855 ret void856}857 858declare <64 x i8> @llvm.smax.v64i8(<64 x i8>, <64 x i8>)859declare <32 x i16> @llvm.smax.v32i16(<32 x i16>, <32 x i16>)860declare <16 x i32> @llvm.smax.v16i32(<16 x i32>, <16 x i32>)861declare <8 x i64> @llvm.smax.v8i64(<8 x i64>, <8 x i64>)862 863declare <64 x i8> @llvm.smin.v64i8(<64 x i8>, <64 x i8>)864declare <32 x i16> @llvm.smin.v32i16(<32 x i16>, <32 x i16>)865declare <16 x i32> @llvm.smin.v16i32(<16 x i32>, <16 x i32>)866declare <8 x i64> @llvm.smin.v8i64(<8 x i64>, <8 x i64>)867 868declare <64 x i8> @llvm.umax.v64i8(<64 x i8>, <64 x i8>)869declare <32 x i16> @llvm.umax.v32i16(<32 x i16>, <32 x i16>)870declare <16 x i32> @llvm.umax.v16i32(<16 x i32>, <16 x i32>)871declare <8 x i64> @llvm.umax.v8i64(<8 x i64>, <8 x i64>)872 873declare <64 x i8> @llvm.umin.v64i8(<64 x i8>, <64 x i8>)874declare <32 x i16> @llvm.umin.v32i16(<32 x i16>, <32 x i16>)875declare <16 x i32> @llvm.umin.v16i32(<16 x i32>, <16 x i32>)876declare <8 x i64> @llvm.umin.v8i64(<8 x i64>, <8 x i64>)877 878attributes #0 = { "target-features"="+sve" }879