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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; AND10;11 12; Don't use SVE for 64-bit vectors.13define <8 x i8> @and_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {14; CHECK-LABEL: and_v8i8:15; CHECK: // %bb.0:16; CHECK-NEXT: and v0.8b, v0.8b, v1.8b17; CHECK-NEXT: ret18 %res = and <8 x i8> %op1, %op219 ret <8 x i8> %res20}21 22; Don't use SVE for 128-bit vectors.23define <16 x i8> @and_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 {24; CHECK-LABEL: and_v16i8:25; CHECK: // %bb.0:26; CHECK-NEXT: and v0.16b, v0.16b, v1.16b27; CHECK-NEXT: ret28 %res = and <16 x i8> %op1, %op229 ret <16 x i8> %res30}31 32define void @and_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {33; CHECK-LABEL: and_v32i8:34; CHECK: // %bb.0:35; CHECK-NEXT: ptrue p0.b, vl3236; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]37; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]38; CHECK-NEXT: and z0.d, z0.d, z1.d39; CHECK-NEXT: st1b { z0.b }, p0, [x0]40; CHECK-NEXT: ret41 %op1 = load <32 x i8>, ptr %a42 %op2 = load <32 x i8>, ptr %b43 %res = and <32 x i8> %op1, %op244 store <32 x i8> %res, ptr %a45 ret void46}47 48define void @and_v64i8(ptr %a, ptr %b) #0 {49; VBITS_GE_256-LABEL: and_v64i8:50; VBITS_GE_256: // %bb.0:51; VBITS_GE_256-NEXT: ptrue p0.b, vl3252; VBITS_GE_256-NEXT: mov w8, #32 // =0x2053; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]54; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]55; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]56; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]57; VBITS_GE_256-NEXT: and z0.d, z0.d, z1.d58; VBITS_GE_256-NEXT: and z1.d, z2.d, z3.d59; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]60; VBITS_GE_256-NEXT: st1b { z1.b }, p0, [x0]61; VBITS_GE_256-NEXT: ret62;63; VBITS_GE_512-LABEL: and_v64i8:64; VBITS_GE_512: // %bb.0:65; VBITS_GE_512-NEXT: ptrue p0.b, vl6466; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]67; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]68; VBITS_GE_512-NEXT: and z0.d, z0.d, z1.d69; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]70; VBITS_GE_512-NEXT: ret71 %op1 = load <64 x i8>, ptr %a72 %op2 = load <64 x i8>, ptr %b73 %res = and <64 x i8> %op1, %op274 store <64 x i8> %res, ptr %a75 ret void76}77 78define void @and_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {79; CHECK-LABEL: and_v128i8:80; CHECK: // %bb.0:81; CHECK-NEXT: ptrue p0.b, vl12882; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]83; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]84; CHECK-NEXT: and z0.d, z0.d, z1.d85; CHECK-NEXT: st1b { z0.b }, p0, [x0]86; CHECK-NEXT: ret87 %op1 = load <128 x i8>, ptr %a88 %op2 = load <128 x i8>, ptr %b89 %res = and <128 x i8> %op1, %op290 store <128 x i8> %res, ptr %a91 ret void92}93 94define void @and_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {95; CHECK-LABEL: and_v256i8:96; CHECK: // %bb.0:97; CHECK-NEXT: ptrue p0.b, vl25698; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]99; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]100; CHECK-NEXT: and z0.d, z0.d, z1.d101; CHECK-NEXT: st1b { z0.b }, p0, [x0]102; CHECK-NEXT: ret103 %op1 = load <256 x i8>, ptr %a104 %op2 = load <256 x i8>, ptr %b105 %res = and <256 x i8> %op1, %op2106 store <256 x i8> %res, ptr %a107 ret void108}109 110; Don't use SVE for 64-bit vectors.111define <4 x i16> @and_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 {112; CHECK-LABEL: and_v4i16:113; CHECK: // %bb.0:114; CHECK-NEXT: and v0.8b, v0.8b, v1.8b115; CHECK-NEXT: ret116 %res = and <4 x i16> %op1, %op2117 ret <4 x i16> %res118}119 120; Don't use SVE for 128-bit vectors.121define <8 x i16> @and_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 {122; CHECK-LABEL: and_v8i16:123; CHECK: // %bb.0:124; CHECK-NEXT: and v0.16b, v0.16b, v1.16b125; CHECK-NEXT: ret126 %res = and <8 x i16> %op1, %op2127 ret <8 x i16> %res128}129 130define void @and_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {131; CHECK-LABEL: and_v16i16:132; CHECK: // %bb.0:133; CHECK-NEXT: ptrue p0.h, vl16134; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]135; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]136; CHECK-NEXT: and z0.d, z0.d, z1.d137; CHECK-NEXT: st1h { z0.h }, p0, [x0]138; CHECK-NEXT: ret139 %op1 = load <16 x i16>, ptr %a140 %op2 = load <16 x i16>, ptr %b141 %res = and <16 x i16> %op1, %op2142 store <16 x i16> %res, ptr %a143 ret void144}145 146define void @and_v32i16(ptr %a, ptr %b) #0 {147; VBITS_GE_256-LABEL: and_v32i16:148; VBITS_GE_256: // %bb.0:149; VBITS_GE_256-NEXT: ptrue p0.h, vl16150; VBITS_GE_256-NEXT: mov x8, #16 // =0x10151; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]152; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]153; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]154; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]155; VBITS_GE_256-NEXT: and z0.d, z0.d, z1.d156; VBITS_GE_256-NEXT: and z1.d, z2.d, z3.d157; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]158; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x0]159; VBITS_GE_256-NEXT: ret160;161; VBITS_GE_512-LABEL: and_v32i16:162; VBITS_GE_512: // %bb.0:163; VBITS_GE_512-NEXT: ptrue p0.h, vl32164; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]165; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]166; VBITS_GE_512-NEXT: and z0.d, z0.d, z1.d167; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]168; VBITS_GE_512-NEXT: ret169 %op1 = load <32 x i16>, ptr %a170 %op2 = load <32 x i16>, ptr %b171 %res = and <32 x i16> %op1, %op2172 store <32 x i16> %res, ptr %a173 ret void174}175 176define void @and_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {177; CHECK-LABEL: and_v64i16:178; CHECK: // %bb.0:179; CHECK-NEXT: ptrue p0.h, vl64180; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]181; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]182; CHECK-NEXT: and z0.d, z0.d, z1.d183; CHECK-NEXT: st1h { z0.h }, p0, [x0]184; CHECK-NEXT: ret185 %op1 = load <64 x i16>, ptr %a186 %op2 = load <64 x i16>, ptr %b187 %res = and <64 x i16> %op1, %op2188 store <64 x i16> %res, ptr %a189 ret void190}191 192define void @and_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {193; CHECK-LABEL: and_v128i16:194; CHECK: // %bb.0:195; CHECK-NEXT: ptrue p0.h, vl128196; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]197; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]198; CHECK-NEXT: and z0.d, z0.d, z1.d199; CHECK-NEXT: st1h { z0.h }, p0, [x0]200; CHECK-NEXT: ret201 %op1 = load <128 x i16>, ptr %a202 %op2 = load <128 x i16>, ptr %b203 %res = and <128 x i16> %op1, %op2204 store <128 x i16> %res, ptr %a205 ret void206}207 208; Don't use SVE for 64-bit vectors.209define <2 x i32> @and_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) #0 {210; CHECK-LABEL: and_v2i32:211; CHECK: // %bb.0:212; CHECK-NEXT: and v0.8b, v0.8b, v1.8b213; CHECK-NEXT: ret214 %res = and <2 x i32> %op1, %op2215 ret <2 x i32> %res216}217 218; Don't use SVE for 128-bit vectors.219define <4 x i32> @and_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 {220; CHECK-LABEL: and_v4i32:221; CHECK: // %bb.0:222; CHECK-NEXT: and v0.16b, v0.16b, v1.16b223; CHECK-NEXT: ret224 %res = and <4 x i32> %op1, %op2225 ret <4 x i32> %res226}227 228define void @and_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {229; CHECK-LABEL: and_v8i32:230; CHECK: // %bb.0:231; CHECK-NEXT: ptrue p0.s, vl8232; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]233; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]234; CHECK-NEXT: and z0.d, z0.d, z1.d235; CHECK-NEXT: st1w { z0.s }, p0, [x0]236; CHECK-NEXT: ret237 %op1 = load <8 x i32>, ptr %a238 %op2 = load <8 x i32>, ptr %b239 %res = and <8 x i32> %op1, %op2240 store <8 x i32> %res, ptr %a241 ret void242}243 244define void @and_v16i32(ptr %a, ptr %b) #0 {245; VBITS_GE_256-LABEL: and_v16i32:246; VBITS_GE_256: // %bb.0:247; VBITS_GE_256-NEXT: ptrue p0.s, vl8248; VBITS_GE_256-NEXT: mov x8, #8 // =0x8249; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]250; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]251; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]252; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]253; VBITS_GE_256-NEXT: and z0.d, z0.d, z1.d254; VBITS_GE_256-NEXT: and z1.d, z2.d, z3.d255; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]256; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]257; VBITS_GE_256-NEXT: ret258;259; VBITS_GE_512-LABEL: and_v16i32:260; VBITS_GE_512: // %bb.0:261; VBITS_GE_512-NEXT: ptrue p0.s, vl16262; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]263; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]264; VBITS_GE_512-NEXT: and z0.d, z0.d, z1.d265; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]266; VBITS_GE_512-NEXT: ret267 %op1 = load <16 x i32>, ptr %a268 %op2 = load <16 x i32>, ptr %b269 %res = and <16 x i32> %op1, %op2270 store <16 x i32> %res, ptr %a271 ret void272}273 274define void @and_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {275; CHECK-LABEL: and_v32i32:276; CHECK: // %bb.0:277; CHECK-NEXT: ptrue p0.s, vl32278; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]279; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]280; CHECK-NEXT: and z0.d, z0.d, z1.d281; CHECK-NEXT: st1w { z0.s }, p0, [x0]282; CHECK-NEXT: ret283 %op1 = load <32 x i32>, ptr %a284 %op2 = load <32 x i32>, ptr %b285 %res = and <32 x i32> %op1, %op2286 store <32 x i32> %res, ptr %a287 ret void288}289 290define void @and_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {291; CHECK-LABEL: and_v64i32:292; CHECK: // %bb.0:293; CHECK-NEXT: ptrue p0.s, vl64294; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]295; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]296; CHECK-NEXT: and z0.d, z0.d, z1.d297; CHECK-NEXT: st1w { z0.s }, p0, [x0]298; CHECK-NEXT: ret299 %op1 = load <64 x i32>, ptr %a300 %op2 = load <64 x i32>, ptr %b301 %res = and <64 x i32> %op1, %op2302 store <64 x i32> %res, ptr %a303 ret void304}305 306; Don't use SVE for 64-bit vectors.307define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0) #0 {308; CHECK-LABEL: and_v1i64:309; CHECK: // %bb.0:310; CHECK-NEXT: and v0.8b, v0.8b, v1.8b311; CHECK-NEXT: ret312 %res = and <1 x i64> %op1, %op2313 ret <1 x i64> %res314}315 316; Don't use SVE for 128-bit vectors.317define <2 x i64> @and_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 {318; CHECK-LABEL: and_v2i64:319; CHECK: // %bb.0:320; CHECK-NEXT: and v0.16b, v0.16b, v1.16b321; CHECK-NEXT: ret322 %res = and <2 x i64> %op1, %op2323 ret <2 x i64> %res324}325 326define void @and_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {327; CHECK-LABEL: and_v4i64:328; CHECK: // %bb.0:329; CHECK-NEXT: ptrue p0.d, vl4330; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]331; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]332; CHECK-NEXT: and z0.d, z0.d, z1.d333; CHECK-NEXT: st1d { z0.d }, p0, [x0]334; CHECK-NEXT: ret335 %op1 = load <4 x i64>, ptr %a336 %op2 = load <4 x i64>, ptr %b337 %res = and <4 x i64> %op1, %op2338 store <4 x i64> %res, ptr %a339 ret void340}341 342define void @and_v8i64(ptr %a, ptr %b) #0 {343; VBITS_GE_256-LABEL: and_v8i64:344; VBITS_GE_256: // %bb.0:345; VBITS_GE_256-NEXT: ptrue p0.d, vl4346; VBITS_GE_256-NEXT: mov x8, #4 // =0x4347; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]348; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]349; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]350; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]351; VBITS_GE_256-NEXT: and z0.d, z0.d, z1.d352; VBITS_GE_256-NEXT: and z1.d, z2.d, z3.d353; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]354; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]355; VBITS_GE_256-NEXT: ret356;357; VBITS_GE_512-LABEL: and_v8i64:358; VBITS_GE_512: // %bb.0:359; VBITS_GE_512-NEXT: ptrue p0.d, vl8360; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]361; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]362; VBITS_GE_512-NEXT: and z0.d, z0.d, z1.d363; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]364; VBITS_GE_512-NEXT: ret365 %op1 = load <8 x i64>, ptr %a366 %op2 = load <8 x i64>, ptr %b367 %res = and <8 x i64> %op1, %op2368 store <8 x i64> %res, ptr %a369 ret void370}371 372define void @and_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {373; CHECK-LABEL: and_v16i64:374; CHECK: // %bb.0:375; CHECK-NEXT: ptrue p0.d, vl16376; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]377; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]378; CHECK-NEXT: and z0.d, z0.d, z1.d379; CHECK-NEXT: st1d { z0.d }, p0, [x0]380; CHECK-NEXT: ret381 %op1 = load <16 x i64>, ptr %a382 %op2 = load <16 x i64>, ptr %b383 %res = and <16 x i64> %op1, %op2384 store <16 x i64> %res, ptr %a385 ret void386}387 388define void @and_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {389; CHECK-LABEL: and_v32i64:390; CHECK: // %bb.0:391; CHECK-NEXT: ptrue p0.d, vl32392; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]393; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]394; CHECK-NEXT: and z0.d, z0.d, z1.d395; CHECK-NEXT: st1d { z0.d }, p0, [x0]396; CHECK-NEXT: ret397 %op1 = load <32 x i64>, ptr %a398 %op2 = load <32 x i64>, ptr %b399 %res = and <32 x i64> %op1, %op2400 store <32 x i64> %res, ptr %a401 ret void402}403 404;405; OR406;407 408; Don't use SVE for 64-bit vectors.409define <8 x i8> @or_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {410; CHECK-LABEL: or_v8i8:411; CHECK: // %bb.0:412; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b413; CHECK-NEXT: ret414 %res = or <8 x i8> %op1, %op2415 ret <8 x i8> %res416}417 418; Don't use SVE for 128-bit vectors.419define <16 x i8> @or_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 {420; CHECK-LABEL: or_v16i8:421; CHECK: // %bb.0:422; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b423; CHECK-NEXT: ret424 %res = or <16 x i8> %op1, %op2425 ret <16 x i8> %res426}427 428define void @or_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {429; CHECK-LABEL: or_v32i8:430; CHECK: // %bb.0:431; CHECK-NEXT: ptrue p0.b, vl32432; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]433; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]434; CHECK-NEXT: orr z0.d, z0.d, z1.d435; CHECK-NEXT: st1b { z0.b }, p0, [x0]436; CHECK-NEXT: ret437 %op1 = load <32 x i8>, ptr %a438 %op2 = load <32 x i8>, ptr %b439 %res = or <32 x i8> %op1, %op2440 store <32 x i8> %res, ptr %a441 ret void442}443 444define void @or_v64i8(ptr %a, ptr %b) #0 {445; VBITS_GE_256-LABEL: or_v64i8:446; VBITS_GE_256: // %bb.0:447; VBITS_GE_256-NEXT: ptrue p0.b, vl32448; VBITS_GE_256-NEXT: mov w8, #32 // =0x20449; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]450; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]451; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]452; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]453; VBITS_GE_256-NEXT: orr z0.d, z0.d, z1.d454; VBITS_GE_256-NEXT: orr z1.d, z2.d, z3.d455; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]456; VBITS_GE_256-NEXT: st1b { z1.b }, p0, [x0]457; VBITS_GE_256-NEXT: ret458;459; VBITS_GE_512-LABEL: or_v64i8:460; VBITS_GE_512: // %bb.0:461; VBITS_GE_512-NEXT: ptrue p0.b, vl64462; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]463; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]464; VBITS_GE_512-NEXT: orr z0.d, z0.d, z1.d465; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]466; VBITS_GE_512-NEXT: ret467 %op1 = load <64 x i8>, ptr %a468 %op2 = load <64 x i8>, ptr %b469 %res = or <64 x i8> %op1, %op2470 store <64 x i8> %res, ptr %a471 ret void472}473 474define void @or_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {475; CHECK-LABEL: or_v128i8:476; CHECK: // %bb.0:477; CHECK-NEXT: ptrue p0.b, vl128478; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]479; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]480; CHECK-NEXT: orr z0.d, z0.d, z1.d481; CHECK-NEXT: st1b { z0.b }, p0, [x0]482; CHECK-NEXT: ret483 %op1 = load <128 x i8>, ptr %a484 %op2 = load <128 x i8>, ptr %b485 %res = or <128 x i8> %op1, %op2486 store <128 x i8> %res, ptr %a487 ret void488}489 490define void @or_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {491; CHECK-LABEL: or_v256i8:492; CHECK: // %bb.0:493; CHECK-NEXT: ptrue p0.b, vl256494; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]495; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]496; CHECK-NEXT: orr z0.d, z0.d, z1.d497; CHECK-NEXT: st1b { z0.b }, p0, [x0]498; CHECK-NEXT: ret499 %op1 = load <256 x i8>, ptr %a500 %op2 = load <256 x i8>, ptr %b501 %res = or <256 x i8> %op1, %op2502 store <256 x i8> %res, ptr %a503 ret void504}505 506; Don't use SVE for 64-bit vectors.507define <4 x i16> @or_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 {508; CHECK-LABEL: or_v4i16:509; CHECK: // %bb.0:510; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b511; CHECK-NEXT: ret512 %res = or <4 x i16> %op1, %op2513 ret <4 x i16> %res514}515 516; Don't use SVE for 128-bit vectors.517define <8 x i16> @or_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 {518; CHECK-LABEL: or_v8i16:519; CHECK: // %bb.0:520; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b521; CHECK-NEXT: ret522 %res = or <8 x i16> %op1, %op2523 ret <8 x i16> %res524}525 526define void @or_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {527; CHECK-LABEL: or_v16i16:528; CHECK: // %bb.0:529; CHECK-NEXT: ptrue p0.h, vl16530; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]531; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]532; CHECK-NEXT: orr z0.d, z0.d, z1.d533; CHECK-NEXT: st1h { z0.h }, p0, [x0]534; CHECK-NEXT: ret535 %op1 = load <16 x i16>, ptr %a536 %op2 = load <16 x i16>, ptr %b537 %res = or <16 x i16> %op1, %op2538 store <16 x i16> %res, ptr %a539 ret void540}541 542define void @or_v32i16(ptr %a, ptr %b) #0 {543; VBITS_GE_256-LABEL: or_v32i16:544; VBITS_GE_256: // %bb.0:545; VBITS_GE_256-NEXT: ptrue p0.h, vl16546; VBITS_GE_256-NEXT: mov x8, #16 // =0x10547; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]548; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]549; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]550; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]551; VBITS_GE_256-NEXT: orr z0.d, z0.d, z1.d552; VBITS_GE_256-NEXT: orr z1.d, z2.d, z3.d553; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]554; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x0]555; VBITS_GE_256-NEXT: ret556;557; VBITS_GE_512-LABEL: or_v32i16:558; VBITS_GE_512: // %bb.0:559; VBITS_GE_512-NEXT: ptrue p0.h, vl32560; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]561; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]562; VBITS_GE_512-NEXT: orr z0.d, z0.d, z1.d563; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]564; VBITS_GE_512-NEXT: ret565 %op1 = load <32 x i16>, ptr %a566 %op2 = load <32 x i16>, ptr %b567 %res = or <32 x i16> %op1, %op2568 store <32 x i16> %res, ptr %a569 ret void570}571 572define void @or_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {573; CHECK-LABEL: or_v64i16:574; CHECK: // %bb.0:575; CHECK-NEXT: ptrue p0.h, vl64576; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]577; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]578; CHECK-NEXT: orr z0.d, z0.d, z1.d579; CHECK-NEXT: st1h { z0.h }, p0, [x0]580; CHECK-NEXT: ret581 %op1 = load <64 x i16>, ptr %a582 %op2 = load <64 x i16>, ptr %b583 %res = or <64 x i16> %op1, %op2584 store <64 x i16> %res, ptr %a585 ret void586}587 588define void @or_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {589; CHECK-LABEL: or_v128i16:590; CHECK: // %bb.0:591; CHECK-NEXT: ptrue p0.h, vl128592; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]593; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]594; CHECK-NEXT: orr z0.d, z0.d, z1.d595; CHECK-NEXT: st1h { z0.h }, p0, [x0]596; CHECK-NEXT: ret597 %op1 = load <128 x i16>, ptr %a598 %op2 = load <128 x i16>, ptr %b599 %res = or <128 x i16> %op1, %op2600 store <128 x i16> %res, ptr %a601 ret void602}603 604; Don't use SVE for 64-bit vectors.605define <2 x i32> @or_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) #0 {606; CHECK-LABEL: or_v2i32:607; CHECK: // %bb.0:608; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b609; CHECK-NEXT: ret610 %res = or <2 x i32> %op1, %op2611 ret <2 x i32> %res612}613 614; Don't use SVE for 128-bit vectors.615define <4 x i32> @or_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 {616; CHECK-LABEL: or_v4i32:617; CHECK: // %bb.0:618; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b619; CHECK-NEXT: ret620 %res = or <4 x i32> %op1, %op2621 ret <4 x i32> %res622}623 624define void @or_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {625; CHECK-LABEL: or_v8i32:626; CHECK: // %bb.0:627; CHECK-NEXT: ptrue p0.s, vl8628; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]629; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]630; CHECK-NEXT: orr z0.d, z0.d, z1.d631; CHECK-NEXT: st1w { z0.s }, p0, [x0]632; CHECK-NEXT: ret633 %op1 = load <8 x i32>, ptr %a634 %op2 = load <8 x i32>, ptr %b635 %res = or <8 x i32> %op1, %op2636 store <8 x i32> %res, ptr %a637 ret void638}639 640define void @or_v16i32(ptr %a, ptr %b) #0 {641; VBITS_GE_256-LABEL: or_v16i32:642; VBITS_GE_256: // %bb.0:643; VBITS_GE_256-NEXT: ptrue p0.s, vl8644; VBITS_GE_256-NEXT: mov x8, #8 // =0x8645; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]646; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]647; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]648; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]649; VBITS_GE_256-NEXT: orr z0.d, z0.d, z1.d650; VBITS_GE_256-NEXT: orr z1.d, z2.d, z3.d651; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]652; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]653; VBITS_GE_256-NEXT: ret654;655; VBITS_GE_512-LABEL: or_v16i32:656; VBITS_GE_512: // %bb.0:657; VBITS_GE_512-NEXT: ptrue p0.s, vl16658; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]659; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]660; VBITS_GE_512-NEXT: orr z0.d, z0.d, z1.d661; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]662; VBITS_GE_512-NEXT: ret663 %op1 = load <16 x i32>, ptr %a664 %op2 = load <16 x i32>, ptr %b665 %res = or <16 x i32> %op1, %op2666 store <16 x i32> %res, ptr %a667 ret void668}669 670define void @or_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {671; CHECK-LABEL: or_v32i32:672; CHECK: // %bb.0:673; CHECK-NEXT: ptrue p0.s, vl32674; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]675; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]676; CHECK-NEXT: orr z0.d, z0.d, z1.d677; CHECK-NEXT: st1w { z0.s }, p0, [x0]678; CHECK-NEXT: ret679 %op1 = load <32 x i32>, ptr %a680 %op2 = load <32 x i32>, ptr %b681 %res = or <32 x i32> %op1, %op2682 store <32 x i32> %res, ptr %a683 ret void684}685 686define void @or_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {687; CHECK-LABEL: or_v64i32:688; CHECK: // %bb.0:689; CHECK-NEXT: ptrue p0.s, vl64690; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]691; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]692; CHECK-NEXT: orr z0.d, z0.d, z1.d693; CHECK-NEXT: st1w { z0.s }, p0, [x0]694; CHECK-NEXT: ret695 %op1 = load <64 x i32>, ptr %a696 %op2 = load <64 x i32>, ptr %b697 %res = or <64 x i32> %op1, %op2698 store <64 x i32> %res, ptr %a699 ret void700}701 702; Don't use SVE for 64-bit vectors.703define <1 x i64> @or_v1i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0) #0 {704; CHECK-LABEL: or_v1i64:705; CHECK: // %bb.0:706; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b707; CHECK-NEXT: ret708 %res = or <1 x i64> %op1, %op2709 ret <1 x i64> %res710}711 712; Don't use SVE for 128-bit vectors.713define <2 x i64> @or_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 {714; CHECK-LABEL: or_v2i64:715; CHECK: // %bb.0:716; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b717; CHECK-NEXT: ret718 %res = or <2 x i64> %op1, %op2719 ret <2 x i64> %res720}721 722define void @or_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {723; CHECK-LABEL: or_v4i64:724; CHECK: // %bb.0:725; CHECK-NEXT: ptrue p0.d, vl4726; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]727; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]728; CHECK-NEXT: orr z0.d, z0.d, z1.d729; CHECK-NEXT: st1d { z0.d }, p0, [x0]730; CHECK-NEXT: ret731 %op1 = load <4 x i64>, ptr %a732 %op2 = load <4 x i64>, ptr %b733 %res = or <4 x i64> %op1, %op2734 store <4 x i64> %res, ptr %a735 ret void736}737 738define void @or_v8i64(ptr %a, ptr %b) #0 {739; VBITS_GE_256-LABEL: or_v8i64:740; VBITS_GE_256: // %bb.0:741; VBITS_GE_256-NEXT: ptrue p0.d, vl4742; VBITS_GE_256-NEXT: mov x8, #4 // =0x4743; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]744; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]745; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]746; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]747; VBITS_GE_256-NEXT: orr z0.d, z0.d, z1.d748; VBITS_GE_256-NEXT: orr z1.d, z2.d, z3.d749; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]750; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]751; VBITS_GE_256-NEXT: ret752;753; VBITS_GE_512-LABEL: or_v8i64:754; VBITS_GE_512: // %bb.0:755; VBITS_GE_512-NEXT: ptrue p0.d, vl8756; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]757; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]758; VBITS_GE_512-NEXT: orr z0.d, z0.d, z1.d759; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]760; VBITS_GE_512-NEXT: ret761 %op1 = load <8 x i64>, ptr %a762 %op2 = load <8 x i64>, ptr %b763 %res = or <8 x i64> %op1, %op2764 store <8 x i64> %res, ptr %a765 ret void766}767 768define void @or_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {769; CHECK-LABEL: or_v16i64:770; CHECK: // %bb.0:771; CHECK-NEXT: ptrue p0.d, vl16772; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]773; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]774; CHECK-NEXT: orr z0.d, z0.d, z1.d775; CHECK-NEXT: st1d { z0.d }, p0, [x0]776; CHECK-NEXT: ret777 %op1 = load <16 x i64>, ptr %a778 %op2 = load <16 x i64>, ptr %b779 %res = or <16 x i64> %op1, %op2780 store <16 x i64> %res, ptr %a781 ret void782}783 784define void @or_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {785; CHECK-LABEL: or_v32i64:786; CHECK: // %bb.0:787; CHECK-NEXT: ptrue p0.d, vl32788; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]789; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]790; CHECK-NEXT: orr z0.d, z0.d, z1.d791; CHECK-NEXT: st1d { z0.d }, p0, [x0]792; CHECK-NEXT: ret793 %op1 = load <32 x i64>, ptr %a794 %op2 = load <32 x i64>, ptr %b795 %res = or <32 x i64> %op1, %op2796 store <32 x i64> %res, ptr %a797 ret void798}799 800;801; XOR802;803 804; Don't use SVE for 64-bit vectors.805define <8 x i8> @xor_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {806; CHECK-LABEL: xor_v8i8:807; CHECK: // %bb.0:808; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b809; CHECK-NEXT: ret810 %res = xor <8 x i8> %op1, %op2811 ret <8 x i8> %res812}813 814; Don't use SVE for 128-bit vectors.815define <16 x i8> @xor_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 {816; CHECK-LABEL: xor_v16i8:817; CHECK: // %bb.0:818; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b819; CHECK-NEXT: ret820 %res = xor <16 x i8> %op1, %op2821 ret <16 x i8> %res822}823 824define void @xor_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {825; CHECK-LABEL: xor_v32i8:826; CHECK: // %bb.0:827; CHECK-NEXT: ptrue p0.b, vl32828; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]829; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]830; CHECK-NEXT: eor z0.d, z0.d, z1.d831; CHECK-NEXT: st1b { z0.b }, p0, [x0]832; CHECK-NEXT: ret833 %op1 = load <32 x i8>, ptr %a834 %op2 = load <32 x i8>, ptr %b835 %res = xor <32 x i8> %op1, %op2836 store <32 x i8> %res, ptr %a837 ret void838}839 840define void @xor_v64i8(ptr %a, ptr %b) #0 {841; VBITS_GE_256-LABEL: xor_v64i8:842; VBITS_GE_256: // %bb.0:843; VBITS_GE_256-NEXT: ptrue p0.b, vl32844; VBITS_GE_256-NEXT: mov w8, #32 // =0x20845; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]846; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]847; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]848; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]849; VBITS_GE_256-NEXT: eor z0.d, z0.d, z1.d850; VBITS_GE_256-NEXT: eor z1.d, z2.d, z3.d851; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]852; VBITS_GE_256-NEXT: st1b { z1.b }, p0, [x0]853; VBITS_GE_256-NEXT: ret854;855; VBITS_GE_512-LABEL: xor_v64i8:856; VBITS_GE_512: // %bb.0:857; VBITS_GE_512-NEXT: ptrue p0.b, vl64858; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]859; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]860; VBITS_GE_512-NEXT: eor z0.d, z0.d, z1.d861; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]862; VBITS_GE_512-NEXT: ret863 %op1 = load <64 x i8>, ptr %a864 %op2 = load <64 x i8>, ptr %b865 %res = xor <64 x i8> %op1, %op2866 store <64 x i8> %res, ptr %a867 ret void868}869 870define void @xor_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {871; CHECK-LABEL: xor_v128i8:872; CHECK: // %bb.0:873; CHECK-NEXT: ptrue p0.b, vl128874; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]875; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]876; CHECK-NEXT: eor z0.d, z0.d, z1.d877; CHECK-NEXT: st1b { z0.b }, p0, [x0]878; CHECK-NEXT: ret879 %op1 = load <128 x i8>, ptr %a880 %op2 = load <128 x i8>, ptr %b881 %res = xor <128 x i8> %op1, %op2882 store <128 x i8> %res, ptr %a883 ret void884}885 886define void @xor_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {887; CHECK-LABEL: xor_v256i8:888; CHECK: // %bb.0:889; CHECK-NEXT: ptrue p0.b, vl256890; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]891; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]892; CHECK-NEXT: eor z0.d, z0.d, z1.d893; CHECK-NEXT: st1b { z0.b }, p0, [x0]894; CHECK-NEXT: ret895 %op1 = load <256 x i8>, ptr %a896 %op2 = load <256 x i8>, ptr %b897 %res = xor <256 x i8> %op1, %op2898 store <256 x i8> %res, ptr %a899 ret void900}901 902; Don't use SVE for 64-bit vectors.903define <4 x i16> @xor_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 {904; CHECK-LABEL: xor_v4i16:905; CHECK: // %bb.0:906; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b907; CHECK-NEXT: ret908 %res = xor <4 x i16> %op1, %op2909 ret <4 x i16> %res910}911 912; Don't use SVE for 128-bit vectors.913define <8 x i16> @xor_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 {914; CHECK-LABEL: xor_v8i16:915; CHECK: // %bb.0:916; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b917; CHECK-NEXT: ret918 %res = xor <8 x i16> %op1, %op2919 ret <8 x i16> %res920}921 922define void @xor_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {923; CHECK-LABEL: xor_v16i16:924; CHECK: // %bb.0:925; CHECK-NEXT: ptrue p0.h, vl16926; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]927; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]928; CHECK-NEXT: eor z0.d, z0.d, z1.d929; CHECK-NEXT: st1h { z0.h }, p0, [x0]930; CHECK-NEXT: ret931 %op1 = load <16 x i16>, ptr %a932 %op2 = load <16 x i16>, ptr %b933 %res = xor <16 x i16> %op1, %op2934 store <16 x i16> %res, ptr %a935 ret void936}937 938define void @xor_v32i16(ptr %a, ptr %b) #0 {939; VBITS_GE_256-LABEL: xor_v32i16:940; VBITS_GE_256: // %bb.0:941; VBITS_GE_256-NEXT: ptrue p0.h, vl16942; VBITS_GE_256-NEXT: mov x8, #16 // =0x10943; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]944; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]945; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]946; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]947; VBITS_GE_256-NEXT: eor z0.d, z0.d, z1.d948; VBITS_GE_256-NEXT: eor z1.d, z2.d, z3.d949; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]950; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x0]951; VBITS_GE_256-NEXT: ret952;953; VBITS_GE_512-LABEL: xor_v32i16:954; VBITS_GE_512: // %bb.0:955; VBITS_GE_512-NEXT: ptrue p0.h, vl32956; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]957; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]958; VBITS_GE_512-NEXT: eor z0.d, z0.d, z1.d959; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]960; VBITS_GE_512-NEXT: ret961 %op1 = load <32 x i16>, ptr %a962 %op2 = load <32 x i16>, ptr %b963 %res = xor <32 x i16> %op1, %op2964 store <32 x i16> %res, ptr %a965 ret void966}967 968define void @xor_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {969; CHECK-LABEL: xor_v64i16:970; CHECK: // %bb.0:971; CHECK-NEXT: ptrue p0.h, vl64972; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]973; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]974; CHECK-NEXT: eor z0.d, z0.d, z1.d975; CHECK-NEXT: st1h { z0.h }, p0, [x0]976; CHECK-NEXT: ret977 %op1 = load <64 x i16>, ptr %a978 %op2 = load <64 x i16>, ptr %b979 %res = xor <64 x i16> %op1, %op2980 store <64 x i16> %res, ptr %a981 ret void982}983 984define void @xor_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {985; CHECK-LABEL: xor_v128i16:986; CHECK: // %bb.0:987; CHECK-NEXT: ptrue p0.h, vl128988; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]989; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]990; CHECK-NEXT: eor z0.d, z0.d, z1.d991; CHECK-NEXT: st1h { z0.h }, p0, [x0]992; CHECK-NEXT: ret993 %op1 = load <128 x i16>, ptr %a994 %op2 = load <128 x i16>, ptr %b995 %res = xor <128 x i16> %op1, %op2996 store <128 x i16> %res, ptr %a997 ret void998}999 1000; Don't use SVE for 64-bit vectors.1001define <2 x i32> @xor_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) #0 {1002; CHECK-LABEL: xor_v2i32:1003; CHECK: // %bb.0:1004; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b1005; CHECK-NEXT: ret1006 %res = xor <2 x i32> %op1, %op21007 ret <2 x i32> %res1008}1009 1010; Don't use SVE for 128-bit vectors.1011define <4 x i32> @xor_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 {1012; CHECK-LABEL: xor_v4i32:1013; CHECK: // %bb.0:1014; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b1015; CHECK-NEXT: ret1016 %res = xor <4 x i32> %op1, %op21017 ret <4 x i32> %res1018}1019 1020define void @xor_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {1021; CHECK-LABEL: xor_v8i32:1022; CHECK: // %bb.0:1023; CHECK-NEXT: ptrue p0.s, vl81024; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1025; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1026; CHECK-NEXT: eor z0.d, z0.d, z1.d1027; CHECK-NEXT: st1w { z0.s }, p0, [x0]1028; CHECK-NEXT: ret1029 %op1 = load <8 x i32>, ptr %a1030 %op2 = load <8 x i32>, ptr %b1031 %res = xor <8 x i32> %op1, %op21032 store <8 x i32> %res, ptr %a1033 ret void1034}1035 1036define void @xor_v16i32(ptr %a, ptr %b) #0 {1037; VBITS_GE_256-LABEL: xor_v16i32:1038; VBITS_GE_256: // %bb.0:1039; VBITS_GE_256-NEXT: ptrue p0.s, vl81040; VBITS_GE_256-NEXT: mov x8, #8 // =0x81041; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]1042; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]1043; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]1044; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]1045; VBITS_GE_256-NEXT: eor z0.d, z0.d, z1.d1046; VBITS_GE_256-NEXT: eor z1.d, z2.d, z3.d1047; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]1048; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]1049; VBITS_GE_256-NEXT: ret1050;1051; VBITS_GE_512-LABEL: xor_v16i32:1052; VBITS_GE_512: // %bb.0:1053; VBITS_GE_512-NEXT: ptrue p0.s, vl161054; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]1055; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]1056; VBITS_GE_512-NEXT: eor z0.d, z0.d, z1.d1057; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]1058; VBITS_GE_512-NEXT: ret1059 %op1 = load <16 x i32>, ptr %a1060 %op2 = load <16 x i32>, ptr %b1061 %res = xor <16 x i32> %op1, %op21062 store <16 x i32> %res, ptr %a1063 ret void1064}1065 1066define void @xor_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {1067; CHECK-LABEL: xor_v32i32:1068; CHECK: // %bb.0:1069; CHECK-NEXT: ptrue p0.s, vl321070; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1071; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1072; CHECK-NEXT: eor z0.d, z0.d, z1.d1073; CHECK-NEXT: st1w { z0.s }, p0, [x0]1074; CHECK-NEXT: ret1075 %op1 = load <32 x i32>, ptr %a1076 %op2 = load <32 x i32>, ptr %b1077 %res = xor <32 x i32> %op1, %op21078 store <32 x i32> %res, ptr %a1079 ret void1080}1081 1082define void @xor_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {1083; CHECK-LABEL: xor_v64i32:1084; CHECK: // %bb.0:1085; CHECK-NEXT: ptrue p0.s, vl641086; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1087; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1088; CHECK-NEXT: eor z0.d, z0.d, z1.d1089; CHECK-NEXT: st1w { z0.s }, p0, [x0]1090; CHECK-NEXT: ret1091 %op1 = load <64 x i32>, ptr %a1092 %op2 = load <64 x i32>, ptr %b1093 %res = xor <64 x i32> %op1, %op21094 store <64 x i32> %res, ptr %a1095 ret void1096}1097 1098; Don't use SVE for 64-bit vectors.1099define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0) #0 {1100; CHECK-LABEL: xor_v1i64:1101; CHECK: // %bb.0:1102; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b1103; CHECK-NEXT: ret1104 %res = xor <1 x i64> %op1, %op21105 ret <1 x i64> %res1106}1107 1108; Don't use SVE for 128-bit vectors.1109define <2 x i64> @xor_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 {1110; CHECK-LABEL: xor_v2i64:1111; CHECK: // %bb.0:1112; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b1113; CHECK-NEXT: ret1114 %res = xor <2 x i64> %op1, %op21115 ret <2 x i64> %res1116}1117 1118define void @xor_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {1119; CHECK-LABEL: xor_v4i64:1120; CHECK: // %bb.0:1121; CHECK-NEXT: ptrue p0.d, vl41122; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1123; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1124; CHECK-NEXT: eor z0.d, z0.d, z1.d1125; CHECK-NEXT: st1d { z0.d }, p0, [x0]1126; CHECK-NEXT: ret1127 %op1 = load <4 x i64>, ptr %a1128 %op2 = load <4 x i64>, ptr %b1129 %res = xor <4 x i64> %op1, %op21130 store <4 x i64> %res, ptr %a1131 ret void1132}1133 1134define void @xor_v8i64(ptr %a, ptr %b) #0 {1135; VBITS_GE_256-LABEL: xor_v8i64:1136; VBITS_GE_256: // %bb.0:1137; VBITS_GE_256-NEXT: ptrue p0.d, vl41138; VBITS_GE_256-NEXT: mov x8, #4 // =0x41139; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]1140; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]1141; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]1142; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]1143; VBITS_GE_256-NEXT: eor z0.d, z0.d, z1.d1144; VBITS_GE_256-NEXT: eor z1.d, z2.d, z3.d1145; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]1146; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]1147; VBITS_GE_256-NEXT: ret1148;1149; VBITS_GE_512-LABEL: xor_v8i64:1150; VBITS_GE_512: // %bb.0:1151; VBITS_GE_512-NEXT: ptrue p0.d, vl81152; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]1153; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]1154; VBITS_GE_512-NEXT: eor z0.d, z0.d, z1.d1155; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]1156; VBITS_GE_512-NEXT: ret1157 %op1 = load <8 x i64>, ptr %a1158 %op2 = load <8 x i64>, ptr %b1159 %res = xor <8 x i64> %op1, %op21160 store <8 x i64> %res, ptr %a1161 ret void1162}1163 1164define void @xor_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {1165; CHECK-LABEL: xor_v16i64:1166; CHECK: // %bb.0:1167; CHECK-NEXT: ptrue p0.d, vl161168; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1169; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1170; CHECK-NEXT: eor z0.d, z0.d, z1.d1171; CHECK-NEXT: st1d { z0.d }, p0, [x0]1172; CHECK-NEXT: ret1173 %op1 = load <16 x i64>, ptr %a1174 %op2 = load <16 x i64>, ptr %b1175 %res = xor <16 x i64> %op1, %op21176 store <16 x i64> %res, ptr %a1177 ret void1178}1179 1180define void @xor_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {1181; CHECK-LABEL: xor_v32i64:1182; CHECK: // %bb.0:1183; CHECK-NEXT: ptrue p0.d, vl321184; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1185; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1186; CHECK-NEXT: eor z0.d, z0.d, z1.d1187; CHECK-NEXT: st1d { z0.d }, p0, [x0]1188; CHECK-NEXT: ret1189 %op1 = load <32 x i64>, ptr %a1190 %op2 = load <32 x i64>, ptr %b1191 %res = xor <32 x i64> %op1, %op21192 store <32 x i64> %res, ptr %a1193 ret void1194}1195 1196attributes #0 = { "target-features"="+sve" }1197