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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; SMAX10;11 12; Don't use SVE for 64-bit vectors.13define <8 x i8> @smax_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {14; CHECK-LABEL: smax_v8i8:15; CHECK: // %bb.0:16; CHECK-NEXT: smax v0.8b, v0.8b, v1.8b17; CHECK-NEXT: ret18 %res = call <8 x i8> @llvm.smax.v8i8(<8 x i8> %op1, <8 x i8> %op2)19 ret <8 x i8> %res20}21 22; Don't use SVE for 128-bit vectors.23define <16 x i8> @smax_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 {24; CHECK-LABEL: smax_v16i8:25; CHECK: // %bb.0:26; CHECK-NEXT: smax v0.16b, v0.16b, v1.16b27; CHECK-NEXT: ret28 %res = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %op1, <16 x i8> %op2)29 ret <16 x i8> %res30}31 32define void @smax_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {33; CHECK-LABEL: smax_v32i8:34; CHECK: // %bb.0:35; CHECK-NEXT: ptrue p0.b, vl3236; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]37; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]38; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b39; CHECK-NEXT: st1b { z0.b }, p0, [x0]40; CHECK-NEXT: ret41 %op1 = load <32 x i8>, ptr %a42 %op2 = load <32 x i8>, ptr %b43 %res = call <32 x i8> @llvm.smax.v32i8(<32 x i8> %op1, <32 x i8> %op2)44 store <32 x i8> %res, ptr %a45 ret void46}47 48define void @smax_v64i8(ptr %a, ptr %b) #0 {49; VBITS_GE_256-LABEL: smax_v64i8:50; VBITS_GE_256: // %bb.0:51; VBITS_GE_256-NEXT: ptrue p0.b, vl3252; VBITS_GE_256-NEXT: mov w8, #32 // =0x2053; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]54; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]55; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]56; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]57; VBITS_GE_256-NEXT: smax z0.b, p0/m, z0.b, z1.b58; VBITS_GE_256-NEXT: smax z2.b, p0/m, z2.b, z3.b59; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]60; VBITS_GE_256-NEXT: st1b { z2.b }, p0, [x0]61; VBITS_GE_256-NEXT: ret62;63; VBITS_GE_512-LABEL: smax_v64i8:64; VBITS_GE_512: // %bb.0:65; VBITS_GE_512-NEXT: ptrue p0.b, vl6466; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]67; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]68; VBITS_GE_512-NEXT: smax z0.b, p0/m, z0.b, z1.b69; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]70; VBITS_GE_512-NEXT: ret71 %op1 = load <64 x i8>, ptr %a72 %op2 = load <64 x i8>, ptr %b73 %res = call <64 x i8> @llvm.smax.v64i8(<64 x i8> %op1, <64 x i8> %op2)74 store <64 x i8> %res, ptr %a75 ret void76}77 78define void @smax_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {79; CHECK-LABEL: smax_v128i8:80; CHECK: // %bb.0:81; CHECK-NEXT: ptrue p0.b, vl12882; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]83; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]84; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b85; CHECK-NEXT: st1b { z0.b }, p0, [x0]86; CHECK-NEXT: ret87 %op1 = load <128 x i8>, ptr %a88 %op2 = load <128 x i8>, ptr %b89 %res = call <128 x i8> @llvm.smax.v128i8(<128 x i8> %op1, <128 x i8> %op2)90 store <128 x i8> %res, ptr %a91 ret void92}93 94define void @smax_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {95; CHECK-LABEL: smax_v256i8:96; CHECK: // %bb.0:97; CHECK-NEXT: ptrue p0.b, vl25698; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]99; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]100; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b101; CHECK-NEXT: st1b { z0.b }, p0, [x0]102; CHECK-NEXT: ret103 %op1 = load <256 x i8>, ptr %a104 %op2 = load <256 x i8>, ptr %b105 %res = call <256 x i8> @llvm.smax.v256i8(<256 x i8> %op1, <256 x i8> %op2)106 store <256 x i8> %res, ptr %a107 ret void108}109 110; Don't use SVE for 64-bit vectors.111define <4 x i16> @smax_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 {112; CHECK-LABEL: smax_v4i16:113; CHECK: // %bb.0:114; CHECK-NEXT: smax v0.4h, v0.4h, v1.4h115; CHECK-NEXT: ret116 %res = call <4 x i16> @llvm.smax.v4i16(<4 x i16> %op1, <4 x i16> %op2)117 ret <4 x i16> %res118}119 120; Don't use SVE for 128-bit vectors.121define <8 x i16> @smax_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 {122; CHECK-LABEL: smax_v8i16:123; CHECK: // %bb.0:124; CHECK-NEXT: smax v0.8h, v0.8h, v1.8h125; CHECK-NEXT: ret126 %res = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %op1, <8 x i16> %op2)127 ret <8 x i16> %res128}129 130define void @smax_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {131; CHECK-LABEL: smax_v16i16:132; CHECK: // %bb.0:133; CHECK-NEXT: ptrue p0.h, vl16134; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]135; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]136; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h137; CHECK-NEXT: st1h { z0.h }, p0, [x0]138; CHECK-NEXT: ret139 %op1 = load <16 x i16>, ptr %a140 %op2 = load <16 x i16>, ptr %b141 %res = call <16 x i16> @llvm.smax.v16i16(<16 x i16> %op1, <16 x i16> %op2)142 store <16 x i16> %res, ptr %a143 ret void144}145 146define void @smax_v32i16(ptr %a, ptr %b) #0 {147; VBITS_GE_256-LABEL: smax_v32i16:148; VBITS_GE_256: // %bb.0:149; VBITS_GE_256-NEXT: ptrue p0.h, vl16150; VBITS_GE_256-NEXT: mov x8, #16 // =0x10151; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]152; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]153; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]154; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]155; VBITS_GE_256-NEXT: smax z0.h, p0/m, z0.h, z1.h156; VBITS_GE_256-NEXT: smax z2.h, p0/m, z2.h, z3.h157; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]158; VBITS_GE_256-NEXT: st1h { z2.h }, p0, [x0]159; VBITS_GE_256-NEXT: ret160;161; VBITS_GE_512-LABEL: smax_v32i16:162; VBITS_GE_512: // %bb.0:163; VBITS_GE_512-NEXT: ptrue p0.h, vl32164; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]165; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]166; VBITS_GE_512-NEXT: smax z0.h, p0/m, z0.h, z1.h167; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]168; VBITS_GE_512-NEXT: ret169 %op1 = load <32 x i16>, ptr %a170 %op2 = load <32 x i16>, ptr %b171 %res = call <32 x i16> @llvm.smax.v32i16(<32 x i16> %op1, <32 x i16> %op2)172 store <32 x i16> %res, ptr %a173 ret void174}175 176define void @smax_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {177; CHECK-LABEL: smax_v64i16:178; CHECK: // %bb.0:179; CHECK-NEXT: ptrue p0.h, vl64180; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]181; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]182; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h183; CHECK-NEXT: st1h { z0.h }, p0, [x0]184; CHECK-NEXT: ret185 %op1 = load <64 x i16>, ptr %a186 %op2 = load <64 x i16>, ptr %b187 %res = call <64 x i16> @llvm.smax.v64i16(<64 x i16> %op1, <64 x i16> %op2)188 store <64 x i16> %res, ptr %a189 ret void190}191 192define void @smax_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {193; CHECK-LABEL: smax_v128i16:194; CHECK: // %bb.0:195; CHECK-NEXT: ptrue p0.h, vl128196; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]197; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]198; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h199; CHECK-NEXT: st1h { z0.h }, p0, [x0]200; CHECK-NEXT: ret201 %op1 = load <128 x i16>, ptr %a202 %op2 = load <128 x i16>, ptr %b203 %res = call <128 x i16> @llvm.smax.v128i16(<128 x i16> %op1, <128 x i16> %op2)204 store <128 x i16> %res, ptr %a205 ret void206}207 208; Don't use SVE for 64-bit vectors.209define <2 x i32> @smax_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) #0 {210; CHECK-LABEL: smax_v2i32:211; CHECK: // %bb.0:212; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s213; CHECK-NEXT: ret214 %res = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %op1, <2 x i32> %op2)215 ret <2 x i32> %res216}217 218; Don't use SVE for 128-bit vectors.219define <4 x i32> @smax_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 {220; CHECK-LABEL: smax_v4i32:221; CHECK: // %bb.0:222; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s223; CHECK-NEXT: ret224 %res = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %op1, <4 x i32> %op2)225 ret <4 x i32> %res226}227 228define void @smax_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {229; CHECK-LABEL: smax_v8i32:230; CHECK: // %bb.0:231; CHECK-NEXT: ptrue p0.s, vl8232; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]233; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]234; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s235; CHECK-NEXT: st1w { z0.s }, p0, [x0]236; CHECK-NEXT: ret237 %op1 = load <8 x i32>, ptr %a238 %op2 = load <8 x i32>, ptr %b239 %res = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %op1, <8 x i32> %op2)240 store <8 x i32> %res, ptr %a241 ret void242}243 244define void @smax_v16i32(ptr %a, ptr %b) #0 {245; VBITS_GE_256-LABEL: smax_v16i32:246; VBITS_GE_256: // %bb.0:247; VBITS_GE_256-NEXT: ptrue p0.s, vl8248; VBITS_GE_256-NEXT: mov x8, #8 // =0x8249; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]250; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]251; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]252; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]253; VBITS_GE_256-NEXT: smax z0.s, p0/m, z0.s, z1.s254; VBITS_GE_256-NEXT: smax z2.s, p0/m, z2.s, z3.s255; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]256; VBITS_GE_256-NEXT: st1w { z2.s }, p0, [x0]257; VBITS_GE_256-NEXT: ret258;259; VBITS_GE_512-LABEL: smax_v16i32:260; VBITS_GE_512: // %bb.0:261; VBITS_GE_512-NEXT: ptrue p0.s, vl16262; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]263; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]264; VBITS_GE_512-NEXT: smax z0.s, p0/m, z0.s, z1.s265; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]266; VBITS_GE_512-NEXT: ret267 %op1 = load <16 x i32>, ptr %a268 %op2 = load <16 x i32>, ptr %b269 %res = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %op1, <16 x i32> %op2)270 store <16 x i32> %res, ptr %a271 ret void272}273 274define void @smax_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {275; CHECK-LABEL: smax_v32i32:276; CHECK: // %bb.0:277; CHECK-NEXT: ptrue p0.s, vl32278; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]279; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]280; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s281; CHECK-NEXT: st1w { z0.s }, p0, [x0]282; CHECK-NEXT: ret283 %op1 = load <32 x i32>, ptr %a284 %op2 = load <32 x i32>, ptr %b285 %res = call <32 x i32> @llvm.smax.v32i32(<32 x i32> %op1, <32 x i32> %op2)286 store <32 x i32> %res, ptr %a287 ret void288}289 290define void @smax_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {291; CHECK-LABEL: smax_v64i32:292; CHECK: // %bb.0:293; CHECK-NEXT: ptrue p0.s, vl64294; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]295; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]296; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s297; CHECK-NEXT: st1w { z0.s }, p0, [x0]298; CHECK-NEXT: ret299 %op1 = load <64 x i32>, ptr %a300 %op2 = load <64 x i32>, ptr %b301 %res = call <64 x i32> @llvm.smax.v64i32(<64 x i32> %op1, <64 x i32> %op2)302 store <64 x i32> %res, ptr %a303 ret void304}305 306; Vector i64 max are not legal for NEON so use SVE when available.307define <1 x i64> @smax_v1i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0) #0 {308; CHECK-LABEL: smax_v1i64:309; CHECK: // %bb.0:310; CHECK-NEXT: ptrue p0.d, vl1311; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0312; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1313; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d314; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0315; CHECK-NEXT: ret316 %res = call <1 x i64> @llvm.smax.v1i64(<1 x i64> %op1, <1 x i64> %op2)317 ret <1 x i64> %res318}319 320; Vector i64 max are not legal for NEON so use SVE when available.321define <2 x i64> @smax_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 {322; CHECK-LABEL: smax_v2i64:323; CHECK: // %bb.0:324; CHECK-NEXT: ptrue p0.d, vl2325; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0326; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1327; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d328; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0329; CHECK-NEXT: ret330 %res = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %op1, <2 x i64> %op2)331 ret <2 x i64> %res332}333 334define void @smax_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {335; CHECK-LABEL: smax_v4i64:336; CHECK: // %bb.0:337; CHECK-NEXT: ptrue p0.d, vl4338; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]339; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]340; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d341; CHECK-NEXT: st1d { z0.d }, p0, [x0]342; CHECK-NEXT: ret343 %op1 = load <4 x i64>, ptr %a344 %op2 = load <4 x i64>, ptr %b345 %res = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %op1, <4 x i64> %op2)346 store <4 x i64> %res, ptr %a347 ret void348}349 350define void @smax_v8i64(ptr %a, ptr %b) #0 {351; VBITS_GE_256-LABEL: smax_v8i64:352; VBITS_GE_256: // %bb.0:353; VBITS_GE_256-NEXT: ptrue p0.d, vl4354; VBITS_GE_256-NEXT: mov x8, #4 // =0x4355; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]356; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]357; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]358; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]359; VBITS_GE_256-NEXT: smax z0.d, p0/m, z0.d, z1.d360; VBITS_GE_256-NEXT: smax z2.d, p0/m, z2.d, z3.d361; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]362; VBITS_GE_256-NEXT: st1d { z2.d }, p0, [x0]363; VBITS_GE_256-NEXT: ret364;365; VBITS_GE_512-LABEL: smax_v8i64:366; VBITS_GE_512: // %bb.0:367; VBITS_GE_512-NEXT: ptrue p0.d, vl8368; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]369; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]370; VBITS_GE_512-NEXT: smax z0.d, p0/m, z0.d, z1.d371; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]372; VBITS_GE_512-NEXT: ret373 %op1 = load <8 x i64>, ptr %a374 %op2 = load <8 x i64>, ptr %b375 %res = call <8 x i64> @llvm.smax.v8i64(<8 x i64> %op1, <8 x i64> %op2)376 store <8 x i64> %res, ptr %a377 ret void378}379 380define void @smax_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {381; CHECK-LABEL: smax_v16i64:382; CHECK: // %bb.0:383; CHECK-NEXT: ptrue p0.d, vl16384; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]385; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]386; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d387; CHECK-NEXT: st1d { z0.d }, p0, [x0]388; CHECK-NEXT: ret389 %op1 = load <16 x i64>, ptr %a390 %op2 = load <16 x i64>, ptr %b391 %res = call <16 x i64> @llvm.smax.v16i64(<16 x i64> %op1, <16 x i64> %op2)392 store <16 x i64> %res, ptr %a393 ret void394}395 396define void @smax_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {397; CHECK-LABEL: smax_v32i64:398; CHECK: // %bb.0:399; CHECK-NEXT: ptrue p0.d, vl32400; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]401; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]402; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d403; CHECK-NEXT: st1d { z0.d }, p0, [x0]404; CHECK-NEXT: ret405 %op1 = load <32 x i64>, ptr %a406 %op2 = load <32 x i64>, ptr %b407 %res = call <32 x i64> @llvm.smax.v32i64(<32 x i64> %op1, <32 x i64> %op2)408 store <32 x i64> %res, ptr %a409 ret void410}411 412;413; SMIN414;415 416; Don't use SVE for 64-bit vectors.417define <8 x i8> @smin_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {418; CHECK-LABEL: smin_v8i8:419; CHECK: // %bb.0:420; CHECK-NEXT: smin v0.8b, v0.8b, v1.8b421; CHECK-NEXT: ret422 %res = call <8 x i8> @llvm.smin.v8i8(<8 x i8> %op1, <8 x i8> %op2)423 ret <8 x i8> %res424}425 426; Don't use SVE for 128-bit vectors.427define <16 x i8> @smin_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 {428; CHECK-LABEL: smin_v16i8:429; CHECK: // %bb.0:430; CHECK-NEXT: smin v0.16b, v0.16b, v1.16b431; CHECK-NEXT: ret432 %res = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %op1, <16 x i8> %op2)433 ret <16 x i8> %res434}435 436define void @smin_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {437; CHECK-LABEL: smin_v32i8:438; CHECK: // %bb.0:439; CHECK-NEXT: ptrue p0.b, vl32440; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]441; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]442; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b443; CHECK-NEXT: st1b { z0.b }, p0, [x0]444; CHECK-NEXT: ret445 %op1 = load <32 x i8>, ptr %a446 %op2 = load <32 x i8>, ptr %b447 %res = call <32 x i8> @llvm.smin.v32i8(<32 x i8> %op1, <32 x i8> %op2)448 store <32 x i8> %res, ptr %a449 ret void450}451 452define void @smin_v64i8(ptr %a, ptr %b) #0 {453; VBITS_GE_256-LABEL: smin_v64i8:454; VBITS_GE_256: // %bb.0:455; VBITS_GE_256-NEXT: ptrue p0.b, vl32456; VBITS_GE_256-NEXT: mov w8, #32 // =0x20457; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]458; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]459; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]460; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]461; VBITS_GE_256-NEXT: smin z0.b, p0/m, z0.b, z1.b462; VBITS_GE_256-NEXT: smin z2.b, p0/m, z2.b, z3.b463; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]464; VBITS_GE_256-NEXT: st1b { z2.b }, p0, [x0]465; VBITS_GE_256-NEXT: ret466;467; VBITS_GE_512-LABEL: smin_v64i8:468; VBITS_GE_512: // %bb.0:469; VBITS_GE_512-NEXT: ptrue p0.b, vl64470; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]471; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]472; VBITS_GE_512-NEXT: smin z0.b, p0/m, z0.b, z1.b473; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]474; VBITS_GE_512-NEXT: ret475 %op1 = load <64 x i8>, ptr %a476 %op2 = load <64 x i8>, ptr %b477 %res = call <64 x i8> @llvm.smin.v64i8(<64 x i8> %op1, <64 x i8> %op2)478 store <64 x i8> %res, ptr %a479 ret void480}481 482define void @smin_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {483; CHECK-LABEL: smin_v128i8:484; CHECK: // %bb.0:485; CHECK-NEXT: ptrue p0.b, vl128486; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]487; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]488; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b489; CHECK-NEXT: st1b { z0.b }, p0, [x0]490; CHECK-NEXT: ret491 %op1 = load <128 x i8>, ptr %a492 %op2 = load <128 x i8>, ptr %b493 %res = call <128 x i8> @llvm.smin.v128i8(<128 x i8> %op1, <128 x i8> %op2)494 store <128 x i8> %res, ptr %a495 ret void496}497 498define void @smin_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {499; CHECK-LABEL: smin_v256i8:500; CHECK: // %bb.0:501; CHECK-NEXT: ptrue p0.b, vl256502; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]503; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]504; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b505; CHECK-NEXT: st1b { z0.b }, p0, [x0]506; CHECK-NEXT: ret507 %op1 = load <256 x i8>, ptr %a508 %op2 = load <256 x i8>, ptr %b509 %res = call <256 x i8> @llvm.smin.v256i8(<256 x i8> %op1, <256 x i8> %op2)510 store <256 x i8> %res, ptr %a511 ret void512}513 514; Don't use SVE for 64-bit vectors.515define <4 x i16> @smin_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 {516; CHECK-LABEL: smin_v4i16:517; CHECK: // %bb.0:518; CHECK-NEXT: smin v0.4h, v0.4h, v1.4h519; CHECK-NEXT: ret520 %res = call <4 x i16> @llvm.smin.v4i16(<4 x i16> %op1, <4 x i16> %op2)521 ret <4 x i16> %res522}523 524; Don't use SVE for 128-bit vectors.525define <8 x i16> @smin_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 {526; CHECK-LABEL: smin_v8i16:527; CHECK: // %bb.0:528; CHECK-NEXT: smin v0.8h, v0.8h, v1.8h529; CHECK-NEXT: ret530 %res = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %op1, <8 x i16> %op2)531 ret <8 x i16> %res532}533 534define void @smin_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {535; CHECK-LABEL: smin_v16i16:536; CHECK: // %bb.0:537; CHECK-NEXT: ptrue p0.h, vl16538; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]539; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]540; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h541; CHECK-NEXT: st1h { z0.h }, p0, [x0]542; CHECK-NEXT: ret543 %op1 = load <16 x i16>, ptr %a544 %op2 = load <16 x i16>, ptr %b545 %res = call <16 x i16> @llvm.smin.v16i16(<16 x i16> %op1, <16 x i16> %op2)546 store <16 x i16> %res, ptr %a547 ret void548}549 550define void @smin_v32i16(ptr %a, ptr %b) #0 {551; VBITS_GE_256-LABEL: smin_v32i16:552; VBITS_GE_256: // %bb.0:553; VBITS_GE_256-NEXT: ptrue p0.h, vl16554; VBITS_GE_256-NEXT: mov x8, #16 // =0x10555; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]556; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]557; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]558; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]559; VBITS_GE_256-NEXT: smin z0.h, p0/m, z0.h, z1.h560; VBITS_GE_256-NEXT: smin z2.h, p0/m, z2.h, z3.h561; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]562; VBITS_GE_256-NEXT: st1h { z2.h }, p0, [x0]563; VBITS_GE_256-NEXT: ret564;565; VBITS_GE_512-LABEL: smin_v32i16:566; VBITS_GE_512: // %bb.0:567; VBITS_GE_512-NEXT: ptrue p0.h, vl32568; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]569; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]570; VBITS_GE_512-NEXT: smin z0.h, p0/m, z0.h, z1.h571; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]572; VBITS_GE_512-NEXT: ret573 %op1 = load <32 x i16>, ptr %a574 %op2 = load <32 x i16>, ptr %b575 %res = call <32 x i16> @llvm.smin.v32i16(<32 x i16> %op1, <32 x i16> %op2)576 store <32 x i16> %res, ptr %a577 ret void578}579 580define void @smin_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {581; CHECK-LABEL: smin_v64i16:582; CHECK: // %bb.0:583; CHECK-NEXT: ptrue p0.h, vl64584; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]585; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]586; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h587; CHECK-NEXT: st1h { z0.h }, p0, [x0]588; CHECK-NEXT: ret589 %op1 = load <64 x i16>, ptr %a590 %op2 = load <64 x i16>, ptr %b591 %res = call <64 x i16> @llvm.smin.v64i16(<64 x i16> %op1, <64 x i16> %op2)592 store <64 x i16> %res, ptr %a593 ret void594}595 596define void @smin_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {597; CHECK-LABEL: smin_v128i16:598; CHECK: // %bb.0:599; CHECK-NEXT: ptrue p0.h, vl128600; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]601; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]602; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h603; CHECK-NEXT: st1h { z0.h }, p0, [x0]604; CHECK-NEXT: ret605 %op1 = load <128 x i16>, ptr %a606 %op2 = load <128 x i16>, ptr %b607 %res = call <128 x i16> @llvm.smin.v128i16(<128 x i16> %op1, <128 x i16> %op2)608 store <128 x i16> %res, ptr %a609 ret void610}611 612; Don't use SVE for 64-bit vectors.613define <2 x i32> @smin_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) #0 {614; CHECK-LABEL: smin_v2i32:615; CHECK: // %bb.0:616; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s617; CHECK-NEXT: ret618 %res = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %op1, <2 x i32> %op2)619 ret <2 x i32> %res620}621 622; Don't use SVE for 128-bit vectors.623define <4 x i32> @smin_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 {624; CHECK-LABEL: smin_v4i32:625; CHECK: // %bb.0:626; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s627; CHECK-NEXT: ret628 %res = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %op1, <4 x i32> %op2)629 ret <4 x i32> %res630}631 632define void @smin_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {633; CHECK-LABEL: smin_v8i32:634; CHECK: // %bb.0:635; CHECK-NEXT: ptrue p0.s, vl8636; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]637; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]638; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s639; CHECK-NEXT: st1w { z0.s }, p0, [x0]640; CHECK-NEXT: ret641 %op1 = load <8 x i32>, ptr %a642 %op2 = load <8 x i32>, ptr %b643 %res = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %op1, <8 x i32> %op2)644 store <8 x i32> %res, ptr %a645 ret void646}647 648define void @smin_v16i32(ptr %a, ptr %b) #0 {649; VBITS_GE_256-LABEL: smin_v16i32:650; VBITS_GE_256: // %bb.0:651; VBITS_GE_256-NEXT: ptrue p0.s, vl8652; VBITS_GE_256-NEXT: mov x8, #8 // =0x8653; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]654; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]655; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]656; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]657; VBITS_GE_256-NEXT: smin z0.s, p0/m, z0.s, z1.s658; VBITS_GE_256-NEXT: smin z2.s, p0/m, z2.s, z3.s659; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]660; VBITS_GE_256-NEXT: st1w { z2.s }, p0, [x0]661; VBITS_GE_256-NEXT: ret662;663; VBITS_GE_512-LABEL: smin_v16i32:664; VBITS_GE_512: // %bb.0:665; VBITS_GE_512-NEXT: ptrue p0.s, vl16666; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]667; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]668; VBITS_GE_512-NEXT: smin z0.s, p0/m, z0.s, z1.s669; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]670; VBITS_GE_512-NEXT: ret671 %op1 = load <16 x i32>, ptr %a672 %op2 = load <16 x i32>, ptr %b673 %res = call <16 x i32> @llvm.smin.v16i32(<16 x i32> %op1, <16 x i32> %op2)674 store <16 x i32> %res, ptr %a675 ret void676}677 678define void @smin_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {679; CHECK-LABEL: smin_v32i32:680; CHECK: // %bb.0:681; CHECK-NEXT: ptrue p0.s, vl32682; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]683; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]684; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s685; CHECK-NEXT: st1w { z0.s }, p0, [x0]686; CHECK-NEXT: ret687 %op1 = load <32 x i32>, ptr %a688 %op2 = load <32 x i32>, ptr %b689 %res = call <32 x i32> @llvm.smin.v32i32(<32 x i32> %op1, <32 x i32> %op2)690 store <32 x i32> %res, ptr %a691 ret void692}693 694define void @smin_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {695; CHECK-LABEL: smin_v64i32:696; CHECK: // %bb.0:697; CHECK-NEXT: ptrue p0.s, vl64698; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]699; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]700; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s701; CHECK-NEXT: st1w { z0.s }, p0, [x0]702; CHECK-NEXT: ret703 %op1 = load <64 x i32>, ptr %a704 %op2 = load <64 x i32>, ptr %b705 %res = call <64 x i32> @llvm.smin.v64i32(<64 x i32> %op1, <64 x i32> %op2)706 store <64 x i32> %res, ptr %a707 ret void708}709 710; Vector i64 min are not legal for NEON so use SVE when available.711define <1 x i64> @smin_v1i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0) #0 {712; CHECK-LABEL: smin_v1i64:713; CHECK: // %bb.0:714; CHECK-NEXT: ptrue p0.d, vl1715; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0716; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1717; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d718; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0719; CHECK-NEXT: ret720 %res = call <1 x i64> @llvm.smin.v1i64(<1 x i64> %op1, <1 x i64> %op2)721 ret <1 x i64> %res722}723 724; Vector i64 min are not legal for NEON so use SVE when available.725define <2 x i64> @smin_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 {726; CHECK-LABEL: smin_v2i64:727; CHECK: // %bb.0:728; CHECK-NEXT: ptrue p0.d, vl2729; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0730; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1731; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d732; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0733; CHECK-NEXT: ret734 %res = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %op1, <2 x i64> %op2)735 ret <2 x i64> %res736}737 738define void @smin_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {739; CHECK-LABEL: smin_v4i64:740; CHECK: // %bb.0:741; CHECK-NEXT: ptrue p0.d, vl4742; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]743; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]744; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d745; CHECK-NEXT: st1d { z0.d }, p0, [x0]746; CHECK-NEXT: ret747 %op1 = load <4 x i64>, ptr %a748 %op2 = load <4 x i64>, ptr %b749 %res = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %op1, <4 x i64> %op2)750 store <4 x i64> %res, ptr %a751 ret void752}753 754define void @smin_v8i64(ptr %a, ptr %b) #0 {755; VBITS_GE_256-LABEL: smin_v8i64:756; VBITS_GE_256: // %bb.0:757; VBITS_GE_256-NEXT: ptrue p0.d, vl4758; VBITS_GE_256-NEXT: mov x8, #4 // =0x4759; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]760; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]761; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]762; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]763; VBITS_GE_256-NEXT: smin z0.d, p0/m, z0.d, z1.d764; VBITS_GE_256-NEXT: smin z2.d, p0/m, z2.d, z3.d765; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]766; VBITS_GE_256-NEXT: st1d { z2.d }, p0, [x0]767; VBITS_GE_256-NEXT: ret768;769; VBITS_GE_512-LABEL: smin_v8i64:770; VBITS_GE_512: // %bb.0:771; VBITS_GE_512-NEXT: ptrue p0.d, vl8772; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]773; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]774; VBITS_GE_512-NEXT: smin z0.d, p0/m, z0.d, z1.d775; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]776; VBITS_GE_512-NEXT: ret777 %op1 = load <8 x i64>, ptr %a778 %op2 = load <8 x i64>, ptr %b779 %res = call <8 x i64> @llvm.smin.v8i64(<8 x i64> %op1, <8 x i64> %op2)780 store <8 x i64> %res, ptr %a781 ret void782}783 784define void @smin_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {785; CHECK-LABEL: smin_v16i64:786; CHECK: // %bb.0:787; CHECK-NEXT: ptrue p0.d, vl16788; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]789; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]790; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d791; CHECK-NEXT: st1d { z0.d }, p0, [x0]792; CHECK-NEXT: ret793 %op1 = load <16 x i64>, ptr %a794 %op2 = load <16 x i64>, ptr %b795 %res = call <16 x i64> @llvm.smin.v16i64(<16 x i64> %op1, <16 x i64> %op2)796 store <16 x i64> %res, ptr %a797 ret void798}799 800define void @smin_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {801; CHECK-LABEL: smin_v32i64:802; CHECK: // %bb.0:803; CHECK-NEXT: ptrue p0.d, vl32804; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]805; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]806; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d807; CHECK-NEXT: st1d { z0.d }, p0, [x0]808; CHECK-NEXT: ret809 %op1 = load <32 x i64>, ptr %a810 %op2 = load <32 x i64>, ptr %b811 %res = call <32 x i64> @llvm.smin.v32i64(<32 x i64> %op1, <32 x i64> %op2)812 store <32 x i64> %res, ptr %a813 ret void814}815 816;817; UMAX818;819 820; Don't use SVE for 64-bit vectors.821define <8 x i8> @umax_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {822; CHECK-LABEL: umax_v8i8:823; CHECK: // %bb.0:824; CHECK-NEXT: umax v0.8b, v0.8b, v1.8b825; CHECK-NEXT: ret826 %res = call <8 x i8> @llvm.umax.v8i8(<8 x i8> %op1, <8 x i8> %op2)827 ret <8 x i8> %res828}829 830; Don't use SVE for 128-bit vectors.831define <16 x i8> @umax_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 {832; CHECK-LABEL: umax_v16i8:833; CHECK: // %bb.0:834; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b835; CHECK-NEXT: ret836 %res = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %op1, <16 x i8> %op2)837 ret <16 x i8> %res838}839 840define void @umax_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {841; CHECK-LABEL: umax_v32i8:842; CHECK: // %bb.0:843; CHECK-NEXT: ptrue p0.b, vl32844; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]845; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]846; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b847; CHECK-NEXT: st1b { z0.b }, p0, [x0]848; CHECK-NEXT: ret849 %op1 = load <32 x i8>, ptr %a850 %op2 = load <32 x i8>, ptr %b851 %res = call <32 x i8> @llvm.umax.v32i8(<32 x i8> %op1, <32 x i8> %op2)852 store <32 x i8> %res, ptr %a853 ret void854}855 856define void @umax_v64i8(ptr %a, ptr %b) #0 {857; VBITS_GE_256-LABEL: umax_v64i8:858; VBITS_GE_256: // %bb.0:859; VBITS_GE_256-NEXT: ptrue p0.b, vl32860; VBITS_GE_256-NEXT: mov w8, #32 // =0x20861; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]862; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]863; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]864; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]865; VBITS_GE_256-NEXT: umax z0.b, p0/m, z0.b, z1.b866; VBITS_GE_256-NEXT: umax z2.b, p0/m, z2.b, z3.b867; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]868; VBITS_GE_256-NEXT: st1b { z2.b }, p0, [x0]869; VBITS_GE_256-NEXT: ret870;871; VBITS_GE_512-LABEL: umax_v64i8:872; VBITS_GE_512: // %bb.0:873; VBITS_GE_512-NEXT: ptrue p0.b, vl64874; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]875; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]876; VBITS_GE_512-NEXT: umax z0.b, p0/m, z0.b, z1.b877; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]878; VBITS_GE_512-NEXT: ret879 %op1 = load <64 x i8>, ptr %a880 %op2 = load <64 x i8>, ptr %b881 %res = call <64 x i8> @llvm.umax.v64i8(<64 x i8> %op1, <64 x i8> %op2)882 store <64 x i8> %res, ptr %a883 ret void884}885 886define void @umax_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {887; CHECK-LABEL: umax_v128i8:888; CHECK: // %bb.0:889; CHECK-NEXT: ptrue p0.b, vl128890; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]891; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]892; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b893; CHECK-NEXT: st1b { z0.b }, p0, [x0]894; CHECK-NEXT: ret895 %op1 = load <128 x i8>, ptr %a896 %op2 = load <128 x i8>, ptr %b897 %res = call <128 x i8> @llvm.umax.v128i8(<128 x i8> %op1, <128 x i8> %op2)898 store <128 x i8> %res, ptr %a899 ret void900}901 902define void @umax_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {903; CHECK-LABEL: umax_v256i8:904; CHECK: // %bb.0:905; CHECK-NEXT: ptrue p0.b, vl256906; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]907; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]908; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b909; CHECK-NEXT: st1b { z0.b }, p0, [x0]910; CHECK-NEXT: ret911 %op1 = load <256 x i8>, ptr %a912 %op2 = load <256 x i8>, ptr %b913 %res = call <256 x i8> @llvm.umax.v256i8(<256 x i8> %op1, <256 x i8> %op2)914 store <256 x i8> %res, ptr %a915 ret void916}917 918; Don't use SVE for 64-bit vectors.919define <4 x i16> @umax_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 {920; CHECK-LABEL: umax_v4i16:921; CHECK: // %bb.0:922; CHECK-NEXT: umax v0.4h, v0.4h, v1.4h923; CHECK-NEXT: ret924 %res = call <4 x i16> @llvm.umax.v4i16(<4 x i16> %op1, <4 x i16> %op2)925 ret <4 x i16> %res926}927 928; Don't use SVE for 128-bit vectors.929define <8 x i16> @umax_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 {930; CHECK-LABEL: umax_v8i16:931; CHECK: // %bb.0:932; CHECK-NEXT: umax v0.8h, v0.8h, v1.8h933; CHECK-NEXT: ret934 %res = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %op1, <8 x i16> %op2)935 ret <8 x i16> %res936}937 938define void @umax_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {939; CHECK-LABEL: umax_v16i16:940; CHECK: // %bb.0:941; CHECK-NEXT: ptrue p0.h, vl16942; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]943; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]944; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h945; CHECK-NEXT: st1h { z0.h }, p0, [x0]946; CHECK-NEXT: ret947 %op1 = load <16 x i16>, ptr %a948 %op2 = load <16 x i16>, ptr %b949 %res = call <16 x i16> @llvm.umax.v16i16(<16 x i16> %op1, <16 x i16> %op2)950 store <16 x i16> %res, ptr %a951 ret void952}953 954define void @umax_v32i16(ptr %a, ptr %b) #0 {955; VBITS_GE_256-LABEL: umax_v32i16:956; VBITS_GE_256: // %bb.0:957; VBITS_GE_256-NEXT: ptrue p0.h, vl16958; VBITS_GE_256-NEXT: mov x8, #16 // =0x10959; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]960; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]961; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]962; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]963; VBITS_GE_256-NEXT: umax z0.h, p0/m, z0.h, z1.h964; VBITS_GE_256-NEXT: umax z2.h, p0/m, z2.h, z3.h965; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]966; VBITS_GE_256-NEXT: st1h { z2.h }, p0, [x0]967; VBITS_GE_256-NEXT: ret968;969; VBITS_GE_512-LABEL: umax_v32i16:970; VBITS_GE_512: // %bb.0:971; VBITS_GE_512-NEXT: ptrue p0.h, vl32972; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]973; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]974; VBITS_GE_512-NEXT: umax z0.h, p0/m, z0.h, z1.h975; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]976; VBITS_GE_512-NEXT: ret977 %op1 = load <32 x i16>, ptr %a978 %op2 = load <32 x i16>, ptr %b979 %res = call <32 x i16> @llvm.umax.v32i16(<32 x i16> %op1, <32 x i16> %op2)980 store <32 x i16> %res, ptr %a981 ret void982}983 984define void @umax_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {985; CHECK-LABEL: umax_v64i16:986; CHECK: // %bb.0:987; CHECK-NEXT: ptrue p0.h, vl64988; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]989; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]990; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h991; CHECK-NEXT: st1h { z0.h }, p0, [x0]992; CHECK-NEXT: ret993 %op1 = load <64 x i16>, ptr %a994 %op2 = load <64 x i16>, ptr %b995 %res = call <64 x i16> @llvm.umax.v64i16(<64 x i16> %op1, <64 x i16> %op2)996 store <64 x i16> %res, ptr %a997 ret void998}999 1000define void @umax_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {1001; CHECK-LABEL: umax_v128i16:1002; CHECK: // %bb.0:1003; CHECK-NEXT: ptrue p0.h, vl1281004; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1005; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]1006; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h1007; CHECK-NEXT: st1h { z0.h }, p0, [x0]1008; CHECK-NEXT: ret1009 %op1 = load <128 x i16>, ptr %a1010 %op2 = load <128 x i16>, ptr %b1011 %res = call <128 x i16> @llvm.umax.v128i16(<128 x i16> %op1, <128 x i16> %op2)1012 store <128 x i16> %res, ptr %a1013 ret void1014}1015 1016; Don't use SVE for 64-bit vectors.1017define <2 x i32> @umax_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) #0 {1018; CHECK-LABEL: umax_v2i32:1019; CHECK: // %bb.0:1020; CHECK-NEXT: umax v0.2s, v0.2s, v1.2s1021; CHECK-NEXT: ret1022 %res = call <2 x i32> @llvm.umax.v2i32(<2 x i32> %op1, <2 x i32> %op2)1023 ret <2 x i32> %res1024}1025 1026; Don't use SVE for 128-bit vectors.1027define <4 x i32> @umax_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 {1028; CHECK-LABEL: umax_v4i32:1029; CHECK: // %bb.0:1030; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s1031; CHECK-NEXT: ret1032 %res = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %op1, <4 x i32> %op2)1033 ret <4 x i32> %res1034}1035 1036define void @umax_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {1037; CHECK-LABEL: umax_v8i32:1038; CHECK: // %bb.0:1039; CHECK-NEXT: ptrue p0.s, vl81040; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1041; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1042; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s1043; CHECK-NEXT: st1w { z0.s }, p0, [x0]1044; CHECK-NEXT: ret1045 %op1 = load <8 x i32>, ptr %a1046 %op2 = load <8 x i32>, ptr %b1047 %res = call <8 x i32> @llvm.umax.v8i32(<8 x i32> %op1, <8 x i32> %op2)1048 store <8 x i32> %res, ptr %a1049 ret void1050}1051 1052define void @umax_v16i32(ptr %a, ptr %b) #0 {1053; VBITS_GE_256-LABEL: umax_v16i32:1054; VBITS_GE_256: // %bb.0:1055; VBITS_GE_256-NEXT: ptrue p0.s, vl81056; VBITS_GE_256-NEXT: mov x8, #8 // =0x81057; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]1058; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]1059; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]1060; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]1061; VBITS_GE_256-NEXT: umax z0.s, p0/m, z0.s, z1.s1062; VBITS_GE_256-NEXT: umax z2.s, p0/m, z2.s, z3.s1063; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]1064; VBITS_GE_256-NEXT: st1w { z2.s }, p0, [x0]1065; VBITS_GE_256-NEXT: ret1066;1067; VBITS_GE_512-LABEL: umax_v16i32:1068; VBITS_GE_512: // %bb.0:1069; VBITS_GE_512-NEXT: ptrue p0.s, vl161070; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]1071; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]1072; VBITS_GE_512-NEXT: umax z0.s, p0/m, z0.s, z1.s1073; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]1074; VBITS_GE_512-NEXT: ret1075 %op1 = load <16 x i32>, ptr %a1076 %op2 = load <16 x i32>, ptr %b1077 %res = call <16 x i32> @llvm.umax.v16i32(<16 x i32> %op1, <16 x i32> %op2)1078 store <16 x i32> %res, ptr %a1079 ret void1080}1081 1082define void @umax_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {1083; CHECK-LABEL: umax_v32i32:1084; CHECK: // %bb.0:1085; CHECK-NEXT: ptrue p0.s, vl321086; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1087; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1088; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s1089; CHECK-NEXT: st1w { z0.s }, p0, [x0]1090; CHECK-NEXT: ret1091 %op1 = load <32 x i32>, ptr %a1092 %op2 = load <32 x i32>, ptr %b1093 %res = call <32 x i32> @llvm.umax.v32i32(<32 x i32> %op1, <32 x i32> %op2)1094 store <32 x i32> %res, ptr %a1095 ret void1096}1097 1098define void @umax_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {1099; CHECK-LABEL: umax_v64i32:1100; CHECK: // %bb.0:1101; CHECK-NEXT: ptrue p0.s, vl641102; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1103; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1104; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s1105; CHECK-NEXT: st1w { z0.s }, p0, [x0]1106; CHECK-NEXT: ret1107 %op1 = load <64 x i32>, ptr %a1108 %op2 = load <64 x i32>, ptr %b1109 %res = call <64 x i32> @llvm.umax.v64i32(<64 x i32> %op1, <64 x i32> %op2)1110 store <64 x i32> %res, ptr %a1111 ret void1112}1113 1114; Vector i64 max are not legal for NEON so use SVE when available.1115define <1 x i64> @umax_v1i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0) #0 {1116; CHECK-LABEL: umax_v1i64:1117; CHECK: // %bb.0:1118; CHECK-NEXT: ptrue p0.d, vl11119; CHECK-NEXT: // kill: def $d0 killed $d0 def $z01120; CHECK-NEXT: // kill: def $d1 killed $d1 def $z11121; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d1122; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z01123; CHECK-NEXT: ret1124 %res = call <1 x i64> @llvm.umax.v1i64(<1 x i64> %op1, <1 x i64> %op2)1125 ret <1 x i64> %res1126}1127 1128; Vector i64 max are not legal for NEON so use SVE when available.1129define <2 x i64> @umax_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 {1130; CHECK-LABEL: umax_v2i64:1131; CHECK: // %bb.0:1132; CHECK-NEXT: ptrue p0.d, vl21133; CHECK-NEXT: // kill: def $q0 killed $q0 def $z01134; CHECK-NEXT: // kill: def $q1 killed $q1 def $z11135; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d1136; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z01137; CHECK-NEXT: ret1138 %res = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %op1, <2 x i64> %op2)1139 ret <2 x i64> %res1140}1141 1142define void @umax_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {1143; CHECK-LABEL: umax_v4i64:1144; CHECK: // %bb.0:1145; CHECK-NEXT: ptrue p0.d, vl41146; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1147; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1148; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d1149; CHECK-NEXT: st1d { z0.d }, p0, [x0]1150; CHECK-NEXT: ret1151 %op1 = load <4 x i64>, ptr %a1152 %op2 = load <4 x i64>, ptr %b1153 %res = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %op1, <4 x i64> %op2)1154 store <4 x i64> %res, ptr %a1155 ret void1156}1157 1158define void @umax_v8i64(ptr %a, ptr %b) #0 {1159; VBITS_GE_256-LABEL: umax_v8i64:1160; VBITS_GE_256: // %bb.0:1161; VBITS_GE_256-NEXT: ptrue p0.d, vl41162; VBITS_GE_256-NEXT: mov x8, #4 // =0x41163; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]1164; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]1165; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]1166; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]1167; VBITS_GE_256-NEXT: umax z0.d, p0/m, z0.d, z1.d1168; VBITS_GE_256-NEXT: umax z2.d, p0/m, z2.d, z3.d1169; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]1170; VBITS_GE_256-NEXT: st1d { z2.d }, p0, [x0]1171; VBITS_GE_256-NEXT: ret1172;1173; VBITS_GE_512-LABEL: umax_v8i64:1174; VBITS_GE_512: // %bb.0:1175; VBITS_GE_512-NEXT: ptrue p0.d, vl81176; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]1177; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]1178; VBITS_GE_512-NEXT: umax z0.d, p0/m, z0.d, z1.d1179; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]1180; VBITS_GE_512-NEXT: ret1181 %op1 = load <8 x i64>, ptr %a1182 %op2 = load <8 x i64>, ptr %b1183 %res = call <8 x i64> @llvm.umax.v8i64(<8 x i64> %op1, <8 x i64> %op2)1184 store <8 x i64> %res, ptr %a1185 ret void1186}1187 1188define void @umax_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {1189; CHECK-LABEL: umax_v16i64:1190; CHECK: // %bb.0:1191; CHECK-NEXT: ptrue p0.d, vl161192; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1193; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1194; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d1195; CHECK-NEXT: st1d { z0.d }, p0, [x0]1196; CHECK-NEXT: ret1197 %op1 = load <16 x i64>, ptr %a1198 %op2 = load <16 x i64>, ptr %b1199 %res = call <16 x i64> @llvm.umax.v16i64(<16 x i64> %op1, <16 x i64> %op2)1200 store <16 x i64> %res, ptr %a1201 ret void1202}1203 1204define void @umax_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {1205; CHECK-LABEL: umax_v32i64:1206; CHECK: // %bb.0:1207; CHECK-NEXT: ptrue p0.d, vl321208; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1209; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1210; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d1211; CHECK-NEXT: st1d { z0.d }, p0, [x0]1212; CHECK-NEXT: ret1213 %op1 = load <32 x i64>, ptr %a1214 %op2 = load <32 x i64>, ptr %b1215 %res = call <32 x i64> @llvm.umax.v32i64(<32 x i64> %op1, <32 x i64> %op2)1216 store <32 x i64> %res, ptr %a1217 ret void1218}1219 1220;1221; UMIN1222;1223 1224; Don't use SVE for 64-bit vectors.1225define <8 x i8> @umin_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {1226; CHECK-LABEL: umin_v8i8:1227; CHECK: // %bb.0:1228; CHECK-NEXT: umin v0.8b, v0.8b, v1.8b1229; CHECK-NEXT: ret1230 %res = call <8 x i8> @llvm.umin.v8i8(<8 x i8> %op1, <8 x i8> %op2)1231 ret <8 x i8> %res1232}1233 1234; Don't use SVE for 128-bit vectors.1235define <16 x i8> @umin_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 {1236; CHECK-LABEL: umin_v16i8:1237; CHECK: // %bb.0:1238; CHECK-NEXT: umin v0.16b, v0.16b, v1.16b1239; CHECK-NEXT: ret1240 %res = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %op1, <16 x i8> %op2)1241 ret <16 x i8> %res1242}1243 1244define void @umin_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {1245; CHECK-LABEL: umin_v32i8:1246; CHECK: // %bb.0:1247; CHECK-NEXT: ptrue p0.b, vl321248; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]1249; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]1250; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b1251; CHECK-NEXT: st1b { z0.b }, p0, [x0]1252; CHECK-NEXT: ret1253 %op1 = load <32 x i8>, ptr %a1254 %op2 = load <32 x i8>, ptr %b1255 %res = call <32 x i8> @llvm.umin.v32i8(<32 x i8> %op1, <32 x i8> %op2)1256 store <32 x i8> %res, ptr %a1257 ret void1258}1259 1260define void @umin_v64i8(ptr %a, ptr %b) #0 {1261; VBITS_GE_256-LABEL: umin_v64i8:1262; VBITS_GE_256: // %bb.0:1263; VBITS_GE_256-NEXT: ptrue p0.b, vl321264; VBITS_GE_256-NEXT: mov w8, #32 // =0x201265; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]1266; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]1267; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]1268; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]1269; VBITS_GE_256-NEXT: umin z0.b, p0/m, z0.b, z1.b1270; VBITS_GE_256-NEXT: umin z2.b, p0/m, z2.b, z3.b1271; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]1272; VBITS_GE_256-NEXT: st1b { z2.b }, p0, [x0]1273; VBITS_GE_256-NEXT: ret1274;1275; VBITS_GE_512-LABEL: umin_v64i8:1276; VBITS_GE_512: // %bb.0:1277; VBITS_GE_512-NEXT: ptrue p0.b, vl641278; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]1279; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]1280; VBITS_GE_512-NEXT: umin z0.b, p0/m, z0.b, z1.b1281; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]1282; VBITS_GE_512-NEXT: ret1283 %op1 = load <64 x i8>, ptr %a1284 %op2 = load <64 x i8>, ptr %b1285 %res = call <64 x i8> @llvm.umin.v64i8(<64 x i8> %op1, <64 x i8> %op2)1286 store <64 x i8> %res, ptr %a1287 ret void1288}1289 1290define void @umin_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {1291; CHECK-LABEL: umin_v128i8:1292; CHECK: // %bb.0:1293; CHECK-NEXT: ptrue p0.b, vl1281294; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]1295; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]1296; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b1297; CHECK-NEXT: st1b { z0.b }, p0, [x0]1298; CHECK-NEXT: ret1299 %op1 = load <128 x i8>, ptr %a1300 %op2 = load <128 x i8>, ptr %b1301 %res = call <128 x i8> @llvm.umin.v128i8(<128 x i8> %op1, <128 x i8> %op2)1302 store <128 x i8> %res, ptr %a1303 ret void1304}1305 1306define void @umin_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {1307; CHECK-LABEL: umin_v256i8:1308; CHECK: // %bb.0:1309; CHECK-NEXT: ptrue p0.b, vl2561310; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]1311; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]1312; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b1313; CHECK-NEXT: st1b { z0.b }, p0, [x0]1314; CHECK-NEXT: ret1315 %op1 = load <256 x i8>, ptr %a1316 %op2 = load <256 x i8>, ptr %b1317 %res = call <256 x i8> @llvm.umin.v256i8(<256 x i8> %op1, <256 x i8> %op2)1318 store <256 x i8> %res, ptr %a1319 ret void1320}1321 1322; Don't use SVE for 64-bit vectors.1323define <4 x i16> @umin_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 {1324; CHECK-LABEL: umin_v4i16:1325; CHECK: // %bb.0:1326; CHECK-NEXT: umin v0.4h, v0.4h, v1.4h1327; CHECK-NEXT: ret1328 %res = call <4 x i16> @llvm.umin.v4i16(<4 x i16> %op1, <4 x i16> %op2)1329 ret <4 x i16> %res1330}1331 1332; Don't use SVE for 128-bit vectors.1333define <8 x i16> @umin_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 {1334; CHECK-LABEL: umin_v8i16:1335; CHECK: // %bb.0:1336; CHECK-NEXT: umin v0.8h, v0.8h, v1.8h1337; CHECK-NEXT: ret1338 %res = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %op1, <8 x i16> %op2)1339 ret <8 x i16> %res1340}1341 1342define void @umin_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {1343; CHECK-LABEL: umin_v16i16:1344; CHECK: // %bb.0:1345; CHECK-NEXT: ptrue p0.h, vl161346; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1347; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]1348; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h1349; CHECK-NEXT: st1h { z0.h }, p0, [x0]1350; CHECK-NEXT: ret1351 %op1 = load <16 x i16>, ptr %a1352 %op2 = load <16 x i16>, ptr %b1353 %res = call <16 x i16> @llvm.umin.v16i16(<16 x i16> %op1, <16 x i16> %op2)1354 store <16 x i16> %res, ptr %a1355 ret void1356}1357 1358define void @umin_v32i16(ptr %a, ptr %b) #0 {1359; VBITS_GE_256-LABEL: umin_v32i16:1360; VBITS_GE_256: // %bb.0:1361; VBITS_GE_256-NEXT: ptrue p0.h, vl161362; VBITS_GE_256-NEXT: mov x8, #16 // =0x101363; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]1364; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]1365; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]1366; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]1367; VBITS_GE_256-NEXT: umin z0.h, p0/m, z0.h, z1.h1368; VBITS_GE_256-NEXT: umin z2.h, p0/m, z2.h, z3.h1369; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]1370; VBITS_GE_256-NEXT: st1h { z2.h }, p0, [x0]1371; VBITS_GE_256-NEXT: ret1372;1373; VBITS_GE_512-LABEL: umin_v32i16:1374; VBITS_GE_512: // %bb.0:1375; VBITS_GE_512-NEXT: ptrue p0.h, vl321376; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]1377; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]1378; VBITS_GE_512-NEXT: umin z0.h, p0/m, z0.h, z1.h1379; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]1380; VBITS_GE_512-NEXT: ret1381 %op1 = load <32 x i16>, ptr %a1382 %op2 = load <32 x i16>, ptr %b1383 %res = call <32 x i16> @llvm.umin.v32i16(<32 x i16> %op1, <32 x i16> %op2)1384 store <32 x i16> %res, ptr %a1385 ret void1386}1387 1388define void @umin_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {1389; CHECK-LABEL: umin_v64i16:1390; CHECK: // %bb.0:1391; CHECK-NEXT: ptrue p0.h, vl641392; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1393; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]1394; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h1395; CHECK-NEXT: st1h { z0.h }, p0, [x0]1396; CHECK-NEXT: ret1397 %op1 = load <64 x i16>, ptr %a1398 %op2 = load <64 x i16>, ptr %b1399 %res = call <64 x i16> @llvm.umin.v64i16(<64 x i16> %op1, <64 x i16> %op2)1400 store <64 x i16> %res, ptr %a1401 ret void1402}1403 1404define void @umin_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {1405; CHECK-LABEL: umin_v128i16:1406; CHECK: // %bb.0:1407; CHECK-NEXT: ptrue p0.h, vl1281408; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1409; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]1410; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h1411; CHECK-NEXT: st1h { z0.h }, p0, [x0]1412; CHECK-NEXT: ret1413 %op1 = load <128 x i16>, ptr %a1414 %op2 = load <128 x i16>, ptr %b1415 %res = call <128 x i16> @llvm.umin.v128i16(<128 x i16> %op1, <128 x i16> %op2)1416 store <128 x i16> %res, ptr %a1417 ret void1418}1419 1420; Don't use SVE for 64-bit vectors.1421define <2 x i32> @umin_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) #0 {1422; CHECK-LABEL: umin_v2i32:1423; CHECK: // %bb.0:1424; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s1425; CHECK-NEXT: ret1426 %res = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %op1, <2 x i32> %op2)1427 ret <2 x i32> %res1428}1429 1430; Don't use SVE for 128-bit vectors.1431define <4 x i32> @umin_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 {1432; CHECK-LABEL: umin_v4i32:1433; CHECK: // %bb.0:1434; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s1435; CHECK-NEXT: ret1436 %res = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %op1, <4 x i32> %op2)1437 ret <4 x i32> %res1438}1439 1440define void @umin_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {1441; CHECK-LABEL: umin_v8i32:1442; CHECK: // %bb.0:1443; CHECK-NEXT: ptrue p0.s, vl81444; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1445; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1446; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s1447; CHECK-NEXT: st1w { z0.s }, p0, [x0]1448; CHECK-NEXT: ret1449 %op1 = load <8 x i32>, ptr %a1450 %op2 = load <8 x i32>, ptr %b1451 %res = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %op1, <8 x i32> %op2)1452 store <8 x i32> %res, ptr %a1453 ret void1454}1455 1456define void @umin_v16i32(ptr %a, ptr %b) #0 {1457; VBITS_GE_256-LABEL: umin_v16i32:1458; VBITS_GE_256: // %bb.0:1459; VBITS_GE_256-NEXT: ptrue p0.s, vl81460; VBITS_GE_256-NEXT: mov x8, #8 // =0x81461; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]1462; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]1463; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]1464; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]1465; VBITS_GE_256-NEXT: umin z0.s, p0/m, z0.s, z1.s1466; VBITS_GE_256-NEXT: umin z2.s, p0/m, z2.s, z3.s1467; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]1468; VBITS_GE_256-NEXT: st1w { z2.s }, p0, [x0]1469; VBITS_GE_256-NEXT: ret1470;1471; VBITS_GE_512-LABEL: umin_v16i32:1472; VBITS_GE_512: // %bb.0:1473; VBITS_GE_512-NEXT: ptrue p0.s, vl161474; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]1475; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]1476; VBITS_GE_512-NEXT: umin z0.s, p0/m, z0.s, z1.s1477; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]1478; VBITS_GE_512-NEXT: ret1479 %op1 = load <16 x i32>, ptr %a1480 %op2 = load <16 x i32>, ptr %b1481 %res = call <16 x i32> @llvm.umin.v16i32(<16 x i32> %op1, <16 x i32> %op2)1482 store <16 x i32> %res, ptr %a1483 ret void1484}1485 1486define void @umin_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {1487; CHECK-LABEL: umin_v32i32:1488; CHECK: // %bb.0:1489; CHECK-NEXT: ptrue p0.s, vl321490; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1491; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1492; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s1493; CHECK-NEXT: st1w { z0.s }, p0, [x0]1494; CHECK-NEXT: ret1495 %op1 = load <32 x i32>, ptr %a1496 %op2 = load <32 x i32>, ptr %b1497 %res = call <32 x i32> @llvm.umin.v32i32(<32 x i32> %op1, <32 x i32> %op2)1498 store <32 x i32> %res, ptr %a1499 ret void1500}1501 1502define void @umin_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {1503; CHECK-LABEL: umin_v64i32:1504; CHECK: // %bb.0:1505; CHECK-NEXT: ptrue p0.s, vl641506; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1507; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]1508; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s1509; CHECK-NEXT: st1w { z0.s }, p0, [x0]1510; CHECK-NEXT: ret1511 %op1 = load <64 x i32>, ptr %a1512 %op2 = load <64 x i32>, ptr %b1513 %res = call <64 x i32> @llvm.umin.v64i32(<64 x i32> %op1, <64 x i32> %op2)1514 store <64 x i32> %res, ptr %a1515 ret void1516}1517 1518; Vector i64 min are not legal for NEON so use SVE when available.1519define <1 x i64> @umin_v1i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0) #0 {1520; CHECK-LABEL: umin_v1i64:1521; CHECK: // %bb.0:1522; CHECK-NEXT: ptrue p0.d, vl11523; CHECK-NEXT: // kill: def $d0 killed $d0 def $z01524; CHECK-NEXT: // kill: def $d1 killed $d1 def $z11525; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d1526; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z01527; CHECK-NEXT: ret1528 %res = call <1 x i64> @llvm.umin.v1i64(<1 x i64> %op1, <1 x i64> %op2)1529 ret <1 x i64> %res1530}1531 1532; Vector i64 min are not legal for NEON so use SVE when available.1533define <2 x i64> @umin_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 {1534; CHECK-LABEL: umin_v2i64:1535; CHECK: // %bb.0:1536; CHECK-NEXT: ptrue p0.d, vl21537; CHECK-NEXT: // kill: def $q0 killed $q0 def $z01538; CHECK-NEXT: // kill: def $q1 killed $q1 def $z11539; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d1540; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z01541; CHECK-NEXT: ret1542 %res = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %op1, <2 x i64> %op2)1543 ret <2 x i64> %res1544}1545 1546define void @umin_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {1547; CHECK-LABEL: umin_v4i64:1548; CHECK: // %bb.0:1549; CHECK-NEXT: ptrue p0.d, vl41550; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1551; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1552; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d1553; CHECK-NEXT: st1d { z0.d }, p0, [x0]1554; CHECK-NEXT: ret1555 %op1 = load <4 x i64>, ptr %a1556 %op2 = load <4 x i64>, ptr %b1557 %res = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %op1, <4 x i64> %op2)1558 store <4 x i64> %res, ptr %a1559 ret void1560}1561 1562define void @umin_v8i64(ptr %a, ptr %b) #0 {1563; VBITS_GE_256-LABEL: umin_v8i64:1564; VBITS_GE_256: // %bb.0:1565; VBITS_GE_256-NEXT: ptrue p0.d, vl41566; VBITS_GE_256-NEXT: mov x8, #4 // =0x41567; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]1568; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]1569; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]1570; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]1571; VBITS_GE_256-NEXT: umin z0.d, p0/m, z0.d, z1.d1572; VBITS_GE_256-NEXT: umin z2.d, p0/m, z2.d, z3.d1573; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]1574; VBITS_GE_256-NEXT: st1d { z2.d }, p0, [x0]1575; VBITS_GE_256-NEXT: ret1576;1577; VBITS_GE_512-LABEL: umin_v8i64:1578; VBITS_GE_512: // %bb.0:1579; VBITS_GE_512-NEXT: ptrue p0.d, vl81580; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]1581; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]1582; VBITS_GE_512-NEXT: umin z0.d, p0/m, z0.d, z1.d1583; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]1584; VBITS_GE_512-NEXT: ret1585 %op1 = load <8 x i64>, ptr %a1586 %op2 = load <8 x i64>, ptr %b1587 %res = call <8 x i64> @llvm.umin.v8i64(<8 x i64> %op1, <8 x i64> %op2)1588 store <8 x i64> %res, ptr %a1589 ret void1590}1591 1592define void @umin_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {1593; CHECK-LABEL: umin_v16i64:1594; CHECK: // %bb.0:1595; CHECK-NEXT: ptrue p0.d, vl161596; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1597; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1598; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d1599; CHECK-NEXT: st1d { z0.d }, p0, [x0]1600; CHECK-NEXT: ret1601 %op1 = load <16 x i64>, ptr %a1602 %op2 = load <16 x i64>, ptr %b1603 %res = call <16 x i64> @llvm.umin.v16i64(<16 x i64> %op1, <16 x i64> %op2)1604 store <16 x i64> %res, ptr %a1605 ret void1606}1607 1608define void @umin_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {1609; CHECK-LABEL: umin_v32i64:1610; CHECK: // %bb.0:1611; CHECK-NEXT: ptrue p0.d, vl321612; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1613; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1614; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d1615; CHECK-NEXT: st1d { z0.d }, p0, [x0]1616; CHECK-NEXT: ret1617 %op1 = load <32 x i64>, ptr %a1618 %op2 = load <32 x i64>, ptr %b1619 %res = call <32 x i64> @llvm.umin.v32i64(<32 x i64> %op1, <32 x i64> %op2)1620 store <32 x i64> %res, ptr %a1621 ret void1622}1623 1624attributes #0 = { "target-features"="+sve" }1625 1626declare <8 x i8> @llvm.smin.v8i8(<8 x i8>, <8 x i8>)1627declare <16 x i8> @llvm.smin.v16i8(<16 x i8>, <16 x i8>)1628declare <32 x i8> @llvm.smin.v32i8(<32 x i8>, <32 x i8>)1629declare <64 x i8> @llvm.smin.v64i8(<64 x i8>, <64 x i8>)1630declare <128 x i8> @llvm.smin.v128i8(<128 x i8>, <128 x i8>)1631declare <256 x i8> @llvm.smin.v256i8(<256 x i8>, <256 x i8>)1632declare <4 x i16> @llvm.smin.v4i16(<4 x i16>, <4 x i16>)1633declare <8 x i16> @llvm.smin.v8i16(<8 x i16>, <8 x i16>)1634declare <16 x i16> @llvm.smin.v16i16(<16 x i16>, <16 x i16>)1635declare <32 x i16> @llvm.smin.v32i16(<32 x i16>, <32 x i16>)1636declare <64 x i16> @llvm.smin.v64i16(<64 x i16>, <64 x i16>)1637declare <128 x i16> @llvm.smin.v128i16(<128 x i16>, <128 x i16>)1638declare <2 x i32> @llvm.smin.v2i32(<2 x i32>, <2 x i32>)1639declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)1640declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)1641declare <16 x i32> @llvm.smin.v16i32(<16 x i32>, <16 x i32>)1642declare <32 x i32> @llvm.smin.v32i32(<32 x i32>, <32 x i32>)1643declare <64 x i32> @llvm.smin.v64i32(<64 x i32>, <64 x i32>)1644declare <1 x i64> @llvm.smin.v1i64(<1 x i64>, <1 x i64>)1645declare <2 x i64> @llvm.smin.v2i64(<2 x i64>, <2 x i64>)1646declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>)1647declare <8 x i64> @llvm.smin.v8i64(<8 x i64>, <8 x i64>)1648declare <16 x i64> @llvm.smin.v16i64(<16 x i64>, <16 x i64>)1649declare <32 x i64> @llvm.smin.v32i64(<32 x i64>, <32 x i64>)1650 1651declare <8 x i8> @llvm.smax.v8i8(<8 x i8>, <8 x i8>)1652declare <16 x i8> @llvm.smax.v16i8(<16 x i8>, <16 x i8>)1653declare <32 x i8> @llvm.smax.v32i8(<32 x i8>, <32 x i8>)1654declare <64 x i8> @llvm.smax.v64i8(<64 x i8>, <64 x i8>)1655declare <128 x i8> @llvm.smax.v128i8(<128 x i8>, <128 x i8>)1656declare <256 x i8> @llvm.smax.v256i8(<256 x i8>, <256 x i8>)1657declare <4 x i16> @llvm.smax.v4i16(<4 x i16>, <4 x i16>)1658declare <8 x i16> @llvm.smax.v8i16(<8 x i16>, <8 x i16>)1659declare <16 x i16> @llvm.smax.v16i16(<16 x i16>, <16 x i16>)1660declare <32 x i16> @llvm.smax.v32i16(<32 x i16>, <32 x i16>)1661declare <64 x i16> @llvm.smax.v64i16(<64 x i16>, <64 x i16>)1662declare <128 x i16> @llvm.smax.v128i16(<128 x i16>, <128 x i16>)1663declare <2 x i32> @llvm.smax.v2i32(<2 x i32>, <2 x i32>)1664declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)1665declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>)1666declare <16 x i32> @llvm.smax.v16i32(<16 x i32>, <16 x i32>)1667declare <32 x i32> @llvm.smax.v32i32(<32 x i32>, <32 x i32>)1668declare <64 x i32> @llvm.smax.v64i32(<64 x i32>, <64 x i32>)1669declare <1 x i64> @llvm.smax.v1i64(<1 x i64>, <1 x i64>)1670declare <2 x i64> @llvm.smax.v2i64(<2 x i64>, <2 x i64>)1671declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)1672declare <8 x i64> @llvm.smax.v8i64(<8 x i64>, <8 x i64>)1673declare <16 x i64> @llvm.smax.v16i64(<16 x i64>, <16 x i64>)1674declare <32 x i64> @llvm.smax.v32i64(<32 x i64>, <32 x i64>)1675 1676declare <8 x i8> @llvm.umin.v8i8(<8 x i8>, <8 x i8>)1677declare <16 x i8> @llvm.umin.v16i8(<16 x i8>, <16 x i8>)1678declare <32 x i8> @llvm.umin.v32i8(<32 x i8>, <32 x i8>)1679declare <64 x i8> @llvm.umin.v64i8(<64 x i8>, <64 x i8>)1680declare <128 x i8> @llvm.umin.v128i8(<128 x i8>, <128 x i8>)1681declare <256 x i8> @llvm.umin.v256i8(<256 x i8>, <256 x i8>)1682declare <4 x i16> @llvm.umin.v4i16(<4 x i16>, <4 x i16>)1683declare <8 x i16> @llvm.umin.v8i16(<8 x i16>, <8 x i16>)1684declare <16 x i16> @llvm.umin.v16i16(<16 x i16>, <16 x i16>)1685declare <32 x i16> @llvm.umin.v32i16(<32 x i16>, <32 x i16>)1686declare <64 x i16> @llvm.umin.v64i16(<64 x i16>, <64 x i16>)1687declare <128 x i16> @llvm.umin.v128i16(<128 x i16>, <128 x i16>)1688declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)1689declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)1690declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)1691declare <16 x i32> @llvm.umin.v16i32(<16 x i32>, <16 x i32>)1692declare <32 x i32> @llvm.umin.v32i32(<32 x i32>, <32 x i32>)1693declare <64 x i32> @llvm.umin.v64i32(<64 x i32>, <64 x i32>)1694declare <1 x i64> @llvm.umin.v1i64(<1 x i64>, <1 x i64>)1695declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>)1696declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)1697declare <8 x i64> @llvm.umin.v8i64(<8 x i64>, <8 x i64>)1698declare <16 x i64> @llvm.umin.v16i64(<16 x i64>, <16 x i64>)1699declare <32 x i64> @llvm.umin.v32i64(<32 x i64>, <32 x i64>)1700 1701declare <8 x i8> @llvm.umax.v8i8(<8 x i8>, <8 x i8>)1702declare <16 x i8> @llvm.umax.v16i8(<16 x i8>, <16 x i8>)1703declare <32 x i8> @llvm.umax.v32i8(<32 x i8>, <32 x i8>)1704declare <64 x i8> @llvm.umax.v64i8(<64 x i8>, <64 x i8>)1705declare <128 x i8> @llvm.umax.v128i8(<128 x i8>, <128 x i8>)1706declare <256 x i8> @llvm.umax.v256i8(<256 x i8>, <256 x i8>)1707declare <4 x i16> @llvm.umax.v4i16(<4 x i16>, <4 x i16>)1708declare <8 x i16> @llvm.umax.v8i16(<8 x i16>, <8 x i16>)1709declare <16 x i16> @llvm.umax.v16i16(<16 x i16>, <16 x i16>)1710declare <32 x i16> @llvm.umax.v32i16(<32 x i16>, <32 x i16>)1711declare <64 x i16> @llvm.umax.v64i16(<64 x i16>, <64 x i16>)1712declare <128 x i16> @llvm.umax.v128i16(<128 x i16>, <128 x i16>)1713declare <2 x i32> @llvm.umax.v2i32(<2 x i32>, <2 x i32>)1714declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)1715declare <8 x i32> @llvm.umax.v8i32(<8 x i32>, <8 x i32>)1716declare <16 x i32> @llvm.umax.v16i32(<16 x i32>, <16 x i32>)1717declare <32 x i32> @llvm.umax.v32i32(<32 x i32>, <32 x i32>)1718declare <64 x i32> @llvm.umax.v64i32(<64 x i32>, <64 x i32>)1719declare <1 x i64> @llvm.umax.v1i64(<1 x i64>, <1 x i64>)1720declare <2 x i64> @llvm.umax.v2i64(<2 x i64>, <2 x i64>)1721declare <4 x i64> @llvm.umax.v4i64(<4 x i64>, <4 x i64>)1722declare <8 x i64> @llvm.umax.v8i64(<8 x i64>, <8 x i64>)1723declare <16 x i64> @llvm.umax.v16i64(<16 x i64>, <16 x i64>)1724declare <32 x i64> @llvm.umax.v32i64(<32 x i64>, <32 x i64>)1725