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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8; Don't use SVE for 64-bit vectors.9define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) vscale_range(2,0) #0 {10; CHECK-LABEL: select_v8i8:11; CHECK: // %bb.0:12; CHECK-NEXT: tst w0, #0x113; CHECK-NEXT: csetm w8, ne14; CHECK-NEXT: dup v2.8b, w815; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b16; CHECK-NEXT: ret17 %sel = select i1 %mask, <8 x i8> %op1, <8 x i8> %op218 ret <8 x i8> %sel19}20 21; Don't use SVE for 128-bit vectors.22define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) vscale_range(2,0) #0 {23; CHECK-LABEL: select_v16i8:24; CHECK: // %bb.0:25; CHECK-NEXT: tst w0, #0x126; CHECK-NEXT: csetm w8, ne27; CHECK-NEXT: dup v2.16b, w828; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b29; CHECK-NEXT: ret30 %sel = select i1 %mask, <16 x i8> %op1, <16 x i8> %op231 ret <16 x i8> %sel32}33 34define void @select_v32i8(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 {35; CHECK-LABEL: select_v32i8:36; CHECK: // %bb.0:37; CHECK-NEXT: mov z0.b, w238; CHECK-NEXT: ptrue p0.b39; CHECK-NEXT: ptrue p1.b, vl3240; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, #041; CHECK-NEXT: ld1b { z0.b }, p1/z, [x0]42; CHECK-NEXT: ld1b { z1.b }, p1/z, [x1]43; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b44; CHECK-NEXT: st1b { z0.b }, p1, [x0]45; CHECK-NEXT: ret46 %op1 = load volatile <32 x i8>, ptr %a47 %op2 = load volatile <32 x i8>, ptr %b48 %sel = select i1 %mask, <32 x i8> %op1, <32 x i8> %op249 store <32 x i8> %sel, ptr %a50 ret void51}52 53define void @select_v64i8(ptr %a, ptr %b, i1 %mask) #0 {54; VBITS_GE_256-LABEL: select_v64i8:55; VBITS_GE_256: // %bb.0:56; VBITS_GE_256-NEXT: mov z0.b, w257; VBITS_GE_256-NEXT: ptrue p0.b58; VBITS_GE_256-NEXT: mov w8, #32 // =0x2059; VBITS_GE_256-NEXT: ptrue p1.b, vl3260; VBITS_GE_256-NEXT: cmpne p0.b, p0/z, z0.b, #061; VBITS_GE_256-NEXT: ld1b { z0.b }, p1/z, [x0, x8]62; VBITS_GE_256-NEXT: ld1b { z1.b }, p1/z, [x0]63; VBITS_GE_256-NEXT: ld1b { z2.b }, p1/z, [x1, x8]64; VBITS_GE_256-NEXT: ld1b { z3.b }, p1/z, [x1]65; VBITS_GE_256-NEXT: sel z0.b, p0, z0.b, z2.b66; VBITS_GE_256-NEXT: sel z1.b, p0, z1.b, z3.b67; VBITS_GE_256-NEXT: st1b { z0.b }, p1, [x0, x8]68; VBITS_GE_256-NEXT: st1b { z1.b }, p1, [x0]69; VBITS_GE_256-NEXT: ret70;71; VBITS_GE_512-LABEL: select_v64i8:72; VBITS_GE_512: // %bb.0:73; VBITS_GE_512-NEXT: mov z0.b, w274; VBITS_GE_512-NEXT: ptrue p0.b75; VBITS_GE_512-NEXT: ptrue p1.b, vl6476; VBITS_GE_512-NEXT: cmpne p0.b, p0/z, z0.b, #077; VBITS_GE_512-NEXT: ld1b { z0.b }, p1/z, [x0]78; VBITS_GE_512-NEXT: ld1b { z1.b }, p1/z, [x1]79; VBITS_GE_512-NEXT: sel z0.b, p0, z0.b, z1.b80; VBITS_GE_512-NEXT: st1b { z0.b }, p1, [x0]81; VBITS_GE_512-NEXT: ret82 %op1 = load volatile <64 x i8>, ptr %a83 %op2 = load volatile <64 x i8>, ptr %b84 %sel = select i1 %mask, <64 x i8> %op1, <64 x i8> %op285 store <64 x i8> %sel, ptr %a86 ret void87}88 89define void @select_v128i8(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 {90; CHECK-LABEL: select_v128i8:91; CHECK: // %bb.0:92; CHECK-NEXT: mov z0.b, w293; CHECK-NEXT: ptrue p0.b94; CHECK-NEXT: ptrue p1.b, vl12895; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, #096; CHECK-NEXT: ld1b { z0.b }, p1/z, [x0]97; CHECK-NEXT: ld1b { z1.b }, p1/z, [x1]98; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b99; CHECK-NEXT: st1b { z0.b }, p1, [x0]100; CHECK-NEXT: ret101 %op1 = load volatile <128 x i8>, ptr %a102 %op2 = load volatile <128 x i8>, ptr %b103 %sel = select i1 %mask, <128 x i8> %op1, <128 x i8> %op2104 store <128 x i8> %sel, ptr %a105 ret void106}107 108define void @select_v256i8(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 {109; CHECK-LABEL: select_v256i8:110; CHECK: // %bb.0:111; CHECK-NEXT: mov z0.b, w2112; CHECK-NEXT: ptrue p0.b113; CHECK-NEXT: ptrue p1.b, vl256114; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, #0115; CHECK-NEXT: ld1b { z0.b }, p1/z, [x0]116; CHECK-NEXT: ld1b { z1.b }, p1/z, [x1]117; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b118; CHECK-NEXT: st1b { z0.b }, p1, [x0]119; CHECK-NEXT: ret120 %op1 = load volatile <256 x i8>, ptr %a121 %op2 = load volatile <256 x i8>, ptr %b122 %sel = select i1 %mask, <256 x i8> %op1, <256 x i8> %op2123 store <256 x i8> %sel, ptr %a124 ret void125}126 127; Don't use SVE for 64-bit vectors.128define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) vscale_range(2,0) #0 {129; CHECK-LABEL: select_v4i16:130; CHECK: // %bb.0:131; CHECK-NEXT: tst w0, #0x1132; CHECK-NEXT: csetm w8, ne133; CHECK-NEXT: dup v2.4h, w8134; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b135; CHECK-NEXT: ret136 %sel = select i1 %mask, <4 x i16> %op1, <4 x i16> %op2137 ret <4 x i16> %sel138}139 140; Don't use SVE for 128-bit vectors.141define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) vscale_range(2,0) #0 {142; CHECK-LABEL: select_v8i16:143; CHECK: // %bb.0:144; CHECK-NEXT: tst w0, #0x1145; CHECK-NEXT: csetm w8, ne146; CHECK-NEXT: dup v2.8h, w8147; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b148; CHECK-NEXT: ret149 %sel = select i1 %mask, <8 x i16> %op1, <8 x i16> %op2150 ret <8 x i16> %sel151}152 153define void @select_v16i16(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 {154; CHECK-LABEL: select_v16i16:155; CHECK: // %bb.0:156; CHECK-NEXT: mov z0.h, w2157; CHECK-NEXT: ptrue p0.h158; CHECK-NEXT: ptrue p1.h, vl16159; CHECK-NEXT: and z0.h, z0.h, #0x1160; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0161; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0]162; CHECK-NEXT: ld1h { z1.h }, p1/z, [x1]163; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h164; CHECK-NEXT: st1h { z0.h }, p1, [x0]165; CHECK-NEXT: ret166 %op1 = load volatile <16 x i16>, ptr %a167 %op2 = load volatile <16 x i16>, ptr %b168 %sel = select i1 %mask, <16 x i16> %op1, <16 x i16> %op2169 store <16 x i16> %sel, ptr %a170 ret void171}172 173define void @select_v32i16(ptr %a, ptr %b, i1 %mask) #0 {174; VBITS_GE_256-LABEL: select_v32i16:175; VBITS_GE_256: // %bb.0:176; VBITS_GE_256-NEXT: mov z0.h, w2177; VBITS_GE_256-NEXT: ptrue p0.h178; VBITS_GE_256-NEXT: mov x8, #16 // =0x10179; VBITS_GE_256-NEXT: ptrue p1.h, vl16180; VBITS_GE_256-NEXT: and z0.h, z0.h, #0x1181; VBITS_GE_256-NEXT: cmpne p0.h, p0/z, z0.h, #0182; VBITS_GE_256-NEXT: ld1h { z0.h }, p1/z, [x0, x8, lsl #1]183; VBITS_GE_256-NEXT: ld1h { z1.h }, p1/z, [x0]184; VBITS_GE_256-NEXT: ld1h { z2.h }, p1/z, [x1, x8, lsl #1]185; VBITS_GE_256-NEXT: ld1h { z3.h }, p1/z, [x1]186; VBITS_GE_256-NEXT: sel z0.h, p0, z0.h, z2.h187; VBITS_GE_256-NEXT: sel z1.h, p0, z1.h, z3.h188; VBITS_GE_256-NEXT: st1h { z0.h }, p1, [x0, x8, lsl #1]189; VBITS_GE_256-NEXT: st1h { z1.h }, p1, [x0]190; VBITS_GE_256-NEXT: ret191;192; VBITS_GE_512-LABEL: select_v32i16:193; VBITS_GE_512: // %bb.0:194; VBITS_GE_512-NEXT: mov z0.h, w2195; VBITS_GE_512-NEXT: ptrue p0.h196; VBITS_GE_512-NEXT: ptrue p1.h, vl32197; VBITS_GE_512-NEXT: and z0.h, z0.h, #0x1198; VBITS_GE_512-NEXT: cmpne p0.h, p0/z, z0.h, #0199; VBITS_GE_512-NEXT: ld1h { z0.h }, p1/z, [x0]200; VBITS_GE_512-NEXT: ld1h { z1.h }, p1/z, [x1]201; VBITS_GE_512-NEXT: sel z0.h, p0, z0.h, z1.h202; VBITS_GE_512-NEXT: st1h { z0.h }, p1, [x0]203; VBITS_GE_512-NEXT: ret204 %op1 = load volatile <32 x i16>, ptr %a205 %op2 = load volatile <32 x i16>, ptr %b206 %sel = select i1 %mask, <32 x i16> %op1, <32 x i16> %op2207 store <32 x i16> %sel, ptr %a208 ret void209}210 211define void @select_v64i16(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 {212; CHECK-LABEL: select_v64i16:213; CHECK: // %bb.0:214; CHECK-NEXT: mov z0.h, w2215; CHECK-NEXT: ptrue p0.h216; CHECK-NEXT: ptrue p1.h, vl64217; CHECK-NEXT: and z0.h, z0.h, #0x1218; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0219; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0]220; CHECK-NEXT: ld1h { z1.h }, p1/z, [x1]221; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h222; CHECK-NEXT: st1h { z0.h }, p1, [x0]223; CHECK-NEXT: ret224 %op1 = load volatile <64 x i16>, ptr %a225 %op2 = load volatile <64 x i16>, ptr %b226 %sel = select i1 %mask, <64 x i16> %op1, <64 x i16> %op2227 store <64 x i16> %sel, ptr %a228 ret void229}230 231define void @select_v128i16(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 {232; CHECK-LABEL: select_v128i16:233; CHECK: // %bb.0:234; CHECK-NEXT: mov z0.h, w2235; CHECK-NEXT: ptrue p0.h236; CHECK-NEXT: ptrue p1.h, vl128237; CHECK-NEXT: and z0.h, z0.h, #0x1238; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0239; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0]240; CHECK-NEXT: ld1h { z1.h }, p1/z, [x1]241; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h242; CHECK-NEXT: st1h { z0.h }, p1, [x0]243; CHECK-NEXT: ret244 %op1 = load volatile <128 x i16>, ptr %a245 %op2 = load volatile <128 x i16>, ptr %b246 %sel = select i1 %mask, <128 x i16> %op1, <128 x i16> %op2247 store <128 x i16> %sel, ptr %a248 ret void249}250 251; Don't use SVE for 64-bit vectors.252define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) vscale_range(2,0) #0 {253; CHECK-LABEL: select_v2i32:254; CHECK: // %bb.0:255; CHECK-NEXT: tst w0, #0x1256; CHECK-NEXT: csetm w8, ne257; CHECK-NEXT: dup v2.2s, w8258; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b259; CHECK-NEXT: ret260 %sel = select i1 %mask, <2 x i32> %op1, <2 x i32> %op2261 ret <2 x i32> %sel262}263 264; Don't use SVE for 128-bit vectors.265define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) vscale_range(2,0) #0 {266; CHECK-LABEL: select_v4i32:267; CHECK: // %bb.0:268; CHECK-NEXT: tst w0, #0x1269; CHECK-NEXT: csetm w8, ne270; CHECK-NEXT: dup v2.4s, w8271; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b272; CHECK-NEXT: ret273 %sel = select i1 %mask, <4 x i32> %op1, <4 x i32> %op2274 ret <4 x i32> %sel275}276 277define void @select_v8i32(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 {278; CHECK-LABEL: select_v8i32:279; CHECK: // %bb.0:280; CHECK-NEXT: and w8, w2, #0x1281; CHECK-NEXT: ptrue p0.s282; CHECK-NEXT: mov z0.s, w8283; CHECK-NEXT: ptrue p1.s, vl8284; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0285; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]286; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]287; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s288; CHECK-NEXT: st1w { z0.s }, p1, [x0]289; CHECK-NEXT: ret290 %op1 = load volatile <8 x i32>, ptr %a291 %op2 = load volatile <8 x i32>, ptr %b292 %sel = select i1 %mask, <8 x i32> %op1, <8 x i32> %op2293 store <8 x i32> %sel, ptr %a294 ret void295}296 297define void @select_v16i32(ptr %a, ptr %b, i1 %mask) #0 {298; VBITS_GE_256-LABEL: select_v16i32:299; VBITS_GE_256: // %bb.0:300; VBITS_GE_256-NEXT: and w8, w2, #0x1301; VBITS_GE_256-NEXT: ptrue p0.s302; VBITS_GE_256-NEXT: mov z0.s, w8303; VBITS_GE_256-NEXT: ptrue p1.s, vl8304; VBITS_GE_256-NEXT: mov x8, #8 // =0x8305; VBITS_GE_256-NEXT: cmpne p0.s, p0/z, z0.s, #0306; VBITS_GE_256-NEXT: ld1w { z0.s }, p1/z, [x0, x8, lsl #2]307; VBITS_GE_256-NEXT: ld1w { z1.s }, p1/z, [x0]308; VBITS_GE_256-NEXT: ld1w { z2.s }, p1/z, [x1, x8, lsl #2]309; VBITS_GE_256-NEXT: ld1w { z3.s }, p1/z, [x1]310; VBITS_GE_256-NEXT: sel z0.s, p0, z0.s, z2.s311; VBITS_GE_256-NEXT: sel z1.s, p0, z1.s, z3.s312; VBITS_GE_256-NEXT: st1w { z0.s }, p1, [x0, x8, lsl #2]313; VBITS_GE_256-NEXT: st1w { z1.s }, p1, [x0]314; VBITS_GE_256-NEXT: ret315;316; VBITS_GE_512-LABEL: select_v16i32:317; VBITS_GE_512: // %bb.0:318; VBITS_GE_512-NEXT: and w8, w2, #0x1319; VBITS_GE_512-NEXT: ptrue p0.s320; VBITS_GE_512-NEXT: mov z0.s, w8321; VBITS_GE_512-NEXT: ptrue p1.s, vl16322; VBITS_GE_512-NEXT: cmpne p0.s, p0/z, z0.s, #0323; VBITS_GE_512-NEXT: ld1w { z0.s }, p1/z, [x0]324; VBITS_GE_512-NEXT: ld1w { z1.s }, p1/z, [x1]325; VBITS_GE_512-NEXT: sel z0.s, p0, z0.s, z1.s326; VBITS_GE_512-NEXT: st1w { z0.s }, p1, [x0]327; VBITS_GE_512-NEXT: ret328 %op1 = load volatile <16 x i32>, ptr %a329 %op2 = load volatile <16 x i32>, ptr %b330 %sel = select i1 %mask, <16 x i32> %op1, <16 x i32> %op2331 store <16 x i32> %sel, ptr %a332 ret void333}334 335define void @select_v32i32(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 {336; CHECK-LABEL: select_v32i32:337; CHECK: // %bb.0:338; CHECK-NEXT: and w8, w2, #0x1339; CHECK-NEXT: ptrue p0.s340; CHECK-NEXT: mov z0.s, w8341; CHECK-NEXT: ptrue p1.s, vl32342; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0343; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]344; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]345; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s346; CHECK-NEXT: st1w { z0.s }, p1, [x0]347; CHECK-NEXT: ret348 %op1 = load volatile <32 x i32>, ptr %a349 %op2 = load volatile <32 x i32>, ptr %b350 %sel = select i1 %mask, <32 x i32> %op1, <32 x i32> %op2351 store <32 x i32> %sel, ptr %a352 ret void353}354 355define void @select_v64i32(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 {356; CHECK-LABEL: select_v64i32:357; CHECK: // %bb.0:358; CHECK-NEXT: and w8, w2, #0x1359; CHECK-NEXT: ptrue p0.s360; CHECK-NEXT: mov z0.s, w8361; CHECK-NEXT: ptrue p1.s, vl64362; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0363; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]364; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]365; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s366; CHECK-NEXT: st1w { z0.s }, p1, [x0]367; CHECK-NEXT: ret368 %op1 = load volatile <64 x i32>, ptr %a369 %op2 = load volatile <64 x i32>, ptr %b370 %sel = select i1 %mask, <64 x i32> %op1, <64 x i32> %op2371 store <64 x i32> %sel, ptr %a372 ret void373}374 375; Don't use SVE for 64-bit vectors.376define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) vscale_range(2,0) #0 {377; CHECK-LABEL: select_v1i64:378; CHECK: // %bb.0:379; CHECK-NEXT: tst w0, #0x1380; CHECK-NEXT: csetm x8, ne381; CHECK-NEXT: fmov d2, x8382; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b383; CHECK-NEXT: ret384 %sel = select i1 %mask, <1 x i64> %op1, <1 x i64> %op2385 ret <1 x i64> %sel386}387 388; Don't use SVE for 128-bit vectors.389define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) vscale_range(2,0) #0 {390; CHECK-LABEL: select_v2i64:391; CHECK: // %bb.0:392; CHECK-NEXT: tst w0, #0x1393; CHECK-NEXT: csetm x8, ne394; CHECK-NEXT: dup v2.2d, x8395; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b396; CHECK-NEXT: ret397 %sel = select i1 %mask, <2 x i64> %op1, <2 x i64> %op2398 ret <2 x i64> %sel399}400 401define void @select_v4i64(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 {402; CHECK-LABEL: select_v4i64:403; CHECK: // %bb.0:404; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2405; CHECK-NEXT: and x8, x2, #0x1406; CHECK-NEXT: ptrue p0.d407; CHECK-NEXT: mov z0.d, x8408; CHECK-NEXT: ptrue p1.d, vl4409; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0410; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]411; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]412; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d413; CHECK-NEXT: st1d { z0.d }, p1, [x0]414; CHECK-NEXT: ret415 %op1 = load volatile <4 x i64>, ptr %a416 %op2 = load volatile <4 x i64>, ptr %b417 %sel = select i1 %mask, <4 x i64> %op1, <4 x i64> %op2418 store <4 x i64> %sel, ptr %a419 ret void420}421 422define void @select_v8i64(ptr %a, ptr %b, i1 %mask) #0 {423; VBITS_GE_256-LABEL: select_v8i64:424; VBITS_GE_256: // %bb.0:425; VBITS_GE_256-NEXT: // kill: def $w2 killed $w2 def $x2426; VBITS_GE_256-NEXT: and x8, x2, #0x1427; VBITS_GE_256-NEXT: ptrue p0.d428; VBITS_GE_256-NEXT: mov z0.d, x8429; VBITS_GE_256-NEXT: ptrue p1.d, vl4430; VBITS_GE_256-NEXT: mov x8, #4 // =0x4431; VBITS_GE_256-NEXT: cmpne p0.d, p0/z, z0.d, #0432; VBITS_GE_256-NEXT: ld1d { z0.d }, p1/z, [x0, x8, lsl #3]433; VBITS_GE_256-NEXT: ld1d { z1.d }, p1/z, [x0]434; VBITS_GE_256-NEXT: ld1d { z2.d }, p1/z, [x1, x8, lsl #3]435; VBITS_GE_256-NEXT: ld1d { z3.d }, p1/z, [x1]436; VBITS_GE_256-NEXT: sel z0.d, p0, z0.d, z2.d437; VBITS_GE_256-NEXT: sel z1.d, p0, z1.d, z3.d438; VBITS_GE_256-NEXT: st1d { z0.d }, p1, [x0, x8, lsl #3]439; VBITS_GE_256-NEXT: st1d { z1.d }, p1, [x0]440; VBITS_GE_256-NEXT: ret441;442; VBITS_GE_512-LABEL: select_v8i64:443; VBITS_GE_512: // %bb.0:444; VBITS_GE_512-NEXT: // kill: def $w2 killed $w2 def $x2445; VBITS_GE_512-NEXT: and x8, x2, #0x1446; VBITS_GE_512-NEXT: ptrue p0.d447; VBITS_GE_512-NEXT: mov z0.d, x8448; VBITS_GE_512-NEXT: ptrue p1.d, vl8449; VBITS_GE_512-NEXT: cmpne p0.d, p0/z, z0.d, #0450; VBITS_GE_512-NEXT: ld1d { z0.d }, p1/z, [x0]451; VBITS_GE_512-NEXT: ld1d { z1.d }, p1/z, [x1]452; VBITS_GE_512-NEXT: sel z0.d, p0, z0.d, z1.d453; VBITS_GE_512-NEXT: st1d { z0.d }, p1, [x0]454; VBITS_GE_512-NEXT: ret455 %op1 = load volatile <8 x i64>, ptr %a456 %op2 = load volatile <8 x i64>, ptr %b457 %sel = select i1 %mask, <8 x i64> %op1, <8 x i64> %op2458 store <8 x i64> %sel, ptr %a459 ret void460}461 462define void @select_v16i64(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 {463; CHECK-LABEL: select_v16i64:464; CHECK: // %bb.0:465; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2466; CHECK-NEXT: and x8, x2, #0x1467; CHECK-NEXT: ptrue p0.d468; CHECK-NEXT: mov z0.d, x8469; CHECK-NEXT: ptrue p1.d, vl16470; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0471; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]472; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]473; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d474; CHECK-NEXT: st1d { z0.d }, p1, [x0]475; CHECK-NEXT: ret476 %op1 = load volatile <16 x i64>, ptr %a477 %op2 = load volatile <16 x i64>, ptr %b478 %sel = select i1 %mask, <16 x i64> %op1, <16 x i64> %op2479 store <16 x i64> %sel, ptr %a480 ret void481}482 483define void @select_v32i64(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 {484; CHECK-LABEL: select_v32i64:485; CHECK: // %bb.0:486; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2487; CHECK-NEXT: and x8, x2, #0x1488; CHECK-NEXT: ptrue p0.d489; CHECK-NEXT: mov z0.d, x8490; CHECK-NEXT: ptrue p1.d, vl32491; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0492; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]493; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]494; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d495; CHECK-NEXT: st1d { z0.d }, p1, [x0]496; CHECK-NEXT: ret497 %op1 = load volatile <32 x i64>, ptr %a498 %op2 = load volatile <32 x i64>, ptr %b499 %sel = select i1 %mask, <32 x i64> %op1, <32 x i64> %op2500 store <32 x i64> %sel, ptr %a501 ret void502}503 504attributes #0 = { "target-features"="+sve" }505