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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; UCVTF H -> H10;11 12; Don't use SVE for 64-bit vectors.13define <4 x half> @ucvtf_v4i16_v4f16(<4 x i16> %op1) vscale_range(2,0) #0 {14; CHECK-LABEL: ucvtf_v4i16_v4f16:15; CHECK: // %bb.0:16; CHECK-NEXT: ucvtf v0.4h, v0.4h17; CHECK-NEXT: ret18 %res = uitofp <4 x i16> %op1 to <4 x half>19 ret <4 x half> %res20}21 22; Don't use SVE for 128-bit vectors.23define void @ucvtf_v8i16_v8f16(ptr %a, ptr %b) vscale_range(2,0) #0 {24; CHECK-LABEL: ucvtf_v8i16_v8f16:25; CHECK: // %bb.0:26; CHECK-NEXT: ldr q0, [x0]27; CHECK-NEXT: ucvtf v0.8h, v0.8h28; CHECK-NEXT: str q0, [x1]29; CHECK-NEXT: ret30 %op1 = load <8 x i16>, ptr %a31 %res = uitofp <8 x i16> %op1 to <8 x half>32 store <8 x half> %res, ptr %b33 ret void34}35 36define void @ucvtf_v16i16_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {37; CHECK-LABEL: ucvtf_v16i16_v16f16:38; CHECK: // %bb.0:39; CHECK-NEXT: ptrue p0.h, vl1640; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]41; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h42; CHECK-NEXT: st1h { z0.h }, p0, [x1]43; CHECK-NEXT: ret44 %op1 = load <16 x i16>, ptr %a45 %res = uitofp <16 x i16> %op1 to <16 x half>46 store <16 x half> %res, ptr %b47 ret void48}49 50define void @ucvtf_v32i16_v32f16(ptr %a, ptr %b) #0 {51; VBITS_GE_256-LABEL: ucvtf_v32i16_v32f16:52; VBITS_GE_256: // %bb.0:53; VBITS_GE_256-NEXT: ptrue p0.h, vl1654; VBITS_GE_256-NEXT: mov x8, #16 // =0x1055; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]56; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]57; VBITS_GE_256-NEXT: ucvtf z0.h, p0/m, z0.h58; VBITS_GE_256-NEXT: ucvtf z1.h, p0/m, z1.h59; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]60; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x1]61; VBITS_GE_256-NEXT: ret62;63; VBITS_GE_512-LABEL: ucvtf_v32i16_v32f16:64; VBITS_GE_512: // %bb.0:65; VBITS_GE_512-NEXT: ptrue p0.h, vl3266; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]67; VBITS_GE_512-NEXT: ucvtf z0.h, p0/m, z0.h68; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1]69; VBITS_GE_512-NEXT: ret70 %op1 = load <32 x i16>, ptr %a71 %res = uitofp <32 x i16> %op1 to <32 x half>72 store <32 x half> %res, ptr %b73 ret void74}75 76define void @ucvtf_v64i16_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 {77; CHECK-LABEL: ucvtf_v64i16_v64f16:78; CHECK: // %bb.0:79; CHECK-NEXT: ptrue p0.h, vl6480; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]81; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h82; CHECK-NEXT: st1h { z0.h }, p0, [x1]83; CHECK-NEXT: ret84 %op1 = load <64 x i16>, ptr %a85 %res = uitofp <64 x i16> %op1 to <64 x half>86 store <64 x half> %res, ptr %b87 ret void88}89 90define void @ucvtf_v128i16_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 {91; CHECK-LABEL: ucvtf_v128i16_v128f16:92; CHECK: // %bb.0:93; CHECK-NEXT: ptrue p0.h, vl12894; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]95; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h96; CHECK-NEXT: st1h { z0.h }, p0, [x1]97; CHECK-NEXT: ret98 %op1 = load <128 x i16>, ptr %a99 %res = uitofp <128 x i16> %op1 to <128 x half>100 store <128 x half> %res, ptr %b101 ret void102}103 104;105; UCVTF H -> S106;107 108; Don't use SVE for 64-bit vectors.109define <2 x float> @ucvtf_v2i16_v2f32(<2 x i16> %op1) vscale_range(2,0) #0 {110; CHECK-LABEL: ucvtf_v2i16_v2f32:111; CHECK: // %bb.0:112; CHECK-NEXT: movi d1, #0x00ffff0000ffff113; CHECK-NEXT: and v0.8b, v0.8b, v1.8b114; CHECK-NEXT: ucvtf v0.2s, v0.2s115; CHECK-NEXT: ret116 %res = uitofp <2 x i16> %op1 to <2 x float>117 ret <2 x float> %res118}119 120; Don't use SVE for 128-bit vectors.121define <4 x float> @ucvtf_v4i16_v4f32(<4 x i16> %op1) vscale_range(2,0) #0 {122; CHECK-LABEL: ucvtf_v4i16_v4f32:123; CHECK: // %bb.0:124; CHECK-NEXT: ushll v0.4s, v0.4h, #0125; CHECK-NEXT: ucvtf v0.4s, v0.4s126; CHECK-NEXT: ret127 %res = uitofp <4 x i16> %op1 to <4 x float>128 ret <4 x float> %res129}130 131define void @ucvtf_v8i16_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {132; CHECK-LABEL: ucvtf_v8i16_v8f32:133; CHECK: // %bb.0:134; CHECK-NEXT: ldr q0, [x0]135; CHECK-NEXT: ptrue p0.s, vl8136; CHECK-NEXT: uunpklo z0.s, z0.h137; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s138; CHECK-NEXT: st1w { z0.s }, p0, [x1]139; CHECK-NEXT: ret140 %op1 = load <8 x i16>, ptr %a141 %res = uitofp <8 x i16> %op1 to <8 x float>142 store <8 x float> %res, ptr %b143 ret void144}145 146define void @ucvtf_v16i16_v16f32(ptr %a, ptr %b) #0 {147; VBITS_GE_256-LABEL: ucvtf_v16i16_v16f32:148; VBITS_GE_256: // %bb.0:149; VBITS_GE_256-NEXT: ptrue p0.h, vl16150; VBITS_GE_256-NEXT: mov x8, #8 // =0x8151; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0]152; VBITS_GE_256-NEXT: ptrue p0.s, vl8153; VBITS_GE_256-NEXT: movprfx z1, z0154; VBITS_GE_256-NEXT: ext z1.b, z1.b, z0.b, #16155; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h156; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h157; VBITS_GE_256-NEXT: ucvtf z0.s, p0/m, z0.s158; VBITS_GE_256-NEXT: ucvtf z1.s, p0/m, z1.s159; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1]160; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1, x8, lsl #2]161; VBITS_GE_256-NEXT: ret162;163; VBITS_GE_512-LABEL: ucvtf_v16i16_v16f32:164; VBITS_GE_512: // %bb.0:165; VBITS_GE_512-NEXT: ptrue p0.s, vl16166; VBITS_GE_512-NEXT: ld1h { z0.s }, p0/z, [x0]167; VBITS_GE_512-NEXT: ucvtf z0.s, p0/m, z0.s168; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]169; VBITS_GE_512-NEXT: ret170 %op1 = load <16 x i16>, ptr %a171 %res = uitofp <16 x i16> %op1 to <16 x float>172 store <16 x float> %res, ptr %b173 ret void174}175 176define void @ucvtf_v32i16_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 {177; CHECK-LABEL: ucvtf_v32i16_v32f32:178; CHECK: // %bb.0:179; CHECK-NEXT: ptrue p0.s, vl32180; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]181; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s182; CHECK-NEXT: st1w { z0.s }, p0, [x1]183; CHECK-NEXT: ret184 %op1 = load <32 x i16>, ptr %a185 %res = uitofp <32 x i16> %op1 to <32 x float>186 store <32 x float> %res, ptr %b187 ret void188}189 190define void @ucvtf_v64i16_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 {191; CHECK-LABEL: ucvtf_v64i16_v64f32:192; CHECK: // %bb.0:193; CHECK-NEXT: ptrue p0.s, vl64194; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]195; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s196; CHECK-NEXT: st1w { z0.s }, p0, [x1]197; CHECK-NEXT: ret198 %op1 = load <64 x i16>, ptr %a199 %res = uitofp <64 x i16> %op1 to <64 x float>200 store <64 x float> %res, ptr %b201 ret void202}203 204;205; UCVTF H -> D206;207 208; v1i16 is perfered to be widened to v4i16, which pushes the output into SVE types, so use SVE209define <1 x double> @ucvtf_v1i16_v1f64(<1 x i16> %op1) vscale_range(2,0) #0 {210; CHECK-LABEL: ucvtf_v1i16_v1f64:211; CHECK: // %bb.0:212; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0213; CHECK-NEXT: ptrue p0.d, vl4214; CHECK-NEXT: uunpklo z0.s, z0.h215; CHECK-NEXT: uunpklo z0.d, z0.s216; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d217; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0218; CHECK-NEXT: ret219 %res = uitofp <1 x i16> %op1 to <1 x double>220 ret <1 x double> %res221}222 223; Don't use SVE for 128-bit vectors.224define <2 x double> @ucvtf_v2i16_v2f64(<2 x i16> %op1) vscale_range(2,0) #0 {225; CHECK-LABEL: ucvtf_v2i16_v2f64:226; CHECK: // %bb.0:227; CHECK-NEXT: movi d1, #0x00ffff0000ffff228; CHECK-NEXT: and v0.8b, v0.8b, v1.8b229; CHECK-NEXT: ushll v0.2d, v0.2s, #0230; CHECK-NEXT: ucvtf v0.2d, v0.2d231; CHECK-NEXT: ret232 %res = uitofp <2 x i16> %op1 to <2 x double>233 ret <2 x double> %res234}235 236define void @ucvtf_v4i16_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {237; CHECK-LABEL: ucvtf_v4i16_v4f64:238; CHECK: // %bb.0:239; CHECK-NEXT: ldr d0, [x0]240; CHECK-NEXT: ptrue p0.d, vl4241; CHECK-NEXT: uunpklo z0.s, z0.h242; CHECK-NEXT: uunpklo z0.d, z0.s243; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d244; CHECK-NEXT: st1d { z0.d }, p0, [x1]245; CHECK-NEXT: ret246 %op1 = load <4 x i16>, ptr %a247 %res = uitofp <4 x i16> %op1 to <4 x double>248 store <4 x double> %res, ptr %b249 ret void250}251 252define void @ucvtf_v8i16_v8f64(ptr %a, ptr %b) #0 {253; VBITS_GE_256-LABEL: ucvtf_v8i16_v8f64:254; VBITS_GE_256: // %bb.0:255; VBITS_GE_256-NEXT: ldr q0, [x0]256; VBITS_GE_256-NEXT: ptrue p0.d, vl4257; VBITS_GE_256-NEXT: mov x8, #4 // =0x4258; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8259; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h260; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h261; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s262; VBITS_GE_256-NEXT: uunpklo z1.d, z1.s263; VBITS_GE_256-NEXT: ucvtf z0.d, p0/m, z0.d264; VBITS_GE_256-NEXT: ucvtf z1.d, p0/m, z1.d265; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1]266; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3]267; VBITS_GE_256-NEXT: ret268;269; VBITS_GE_512-LABEL: ucvtf_v8i16_v8f64:270; VBITS_GE_512: // %bb.0:271; VBITS_GE_512-NEXT: ldr q0, [x0]272; VBITS_GE_512-NEXT: ptrue p0.d, vl8273; VBITS_GE_512-NEXT: uunpklo z0.s, z0.h274; VBITS_GE_512-NEXT: uunpklo z0.d, z0.s275; VBITS_GE_512-NEXT: ucvtf z0.d, p0/m, z0.d276; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1]277; VBITS_GE_512-NEXT: ret278 %op1 = load <8 x i16>, ptr %a279 %res = uitofp <8 x i16> %op1 to <8 x double>280 store <8 x double> %res, ptr %b281 ret void282}283 284define void @ucvtf_v16i16_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {285; CHECK-LABEL: ucvtf_v16i16_v16f64:286; CHECK: // %bb.0:287; CHECK-NEXT: ptrue p0.d, vl16288; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]289; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d290; CHECK-NEXT: st1d { z0.d }, p0, [x1]291; CHECK-NEXT: ret292 %op1 = load <16 x i16>, ptr %a293 %res = uitofp <16 x i16> %op1 to <16 x double>294 store <16 x double> %res, ptr %b295 ret void296}297 298define void @ucvtf_v32i16_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {299; CHECK-LABEL: ucvtf_v32i16_v32f64:300; CHECK: // %bb.0:301; CHECK-NEXT: ptrue p0.d, vl32302; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]303; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d304; CHECK-NEXT: st1d { z0.d }, p0, [x1]305; CHECK-NEXT: ret306 %op1 = load <32 x i16>, ptr %a307 %res = uitofp <32 x i16> %op1 to <32 x double>308 store <32 x double> %res, ptr %b309 ret void310}311 312;313; UCVTF S -> H314;315 316; Don't use SVE for 64-bit vectors.317define <2 x half> @ucvtf_v2i32_v2f16(<2 x i32> %op1) vscale_range(2,0) #0 {318; CHECK-LABEL: ucvtf_v2i32_v2f16:319; CHECK: // %bb.0:320; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0321; CHECK-NEXT: ucvtf v0.4s, v0.4s322; CHECK-NEXT: fcvtn v0.4h, v0.4s323; CHECK-NEXT: ret324 %res = uitofp <2 x i32> %op1 to <2 x half>325 ret <2 x half> %res326}327 328; Don't use SVE for 128-bit vectors.329define <4 x half> @ucvtf_v4i32_v4f16(<4 x i32> %op1) vscale_range(2,0) #0 {330; CHECK-LABEL: ucvtf_v4i32_v4f16:331; CHECK: // %bb.0:332; CHECK-NEXT: ucvtf v0.4s, v0.4s333; CHECK-NEXT: fcvtn v0.4h, v0.4s334; CHECK-NEXT: ret335 %res = uitofp <4 x i32> %op1 to <4 x half>336 ret <4 x half> %res337}338 339define <8 x half> @ucvtf_v8i32_v8f16(ptr %a) vscale_range(2,0) #0 {340; CHECK-LABEL: ucvtf_v8i32_v8f16:341; CHECK: // %bb.0:342; CHECK-NEXT: ptrue p0.s, vl8343; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]344; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s345; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h346; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0347; CHECK-NEXT: ret348 %op1 = load <8 x i32>, ptr %a349 %res = uitofp <8 x i32> %op1 to <8 x half>350 ret <8 x half> %res351}352 353define void @ucvtf_v16i32_v16f16(ptr %a, ptr %b) #0 {354; VBITS_GE_256-LABEL: ucvtf_v16i32_v16f16:355; VBITS_GE_256: // %bb.0:356; VBITS_GE_256-NEXT: ptrue p0.s, vl8357; VBITS_GE_256-NEXT: mov x8, #8 // =0x8358; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]359; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]360; VBITS_GE_256-NEXT: ucvtf z0.h, p0/m, z0.s361; VBITS_GE_256-NEXT: ucvtf z1.h, p0/m, z1.s362; VBITS_GE_256-NEXT: ptrue p0.h, vl8363; VBITS_GE_256-NEXT: uzp1 z0.h, z0.h, z0.h364; VBITS_GE_256-NEXT: uzp1 z1.h, z1.h, z1.h365; VBITS_GE_256-NEXT: splice z1.h, p0, z1.h, z0.h366; VBITS_GE_256-NEXT: ptrue p0.h, vl16367; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x1]368; VBITS_GE_256-NEXT: ret369;370; VBITS_GE_512-LABEL: ucvtf_v16i32_v16f16:371; VBITS_GE_512: // %bb.0:372; VBITS_GE_512-NEXT: ptrue p0.s, vl16373; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]374; VBITS_GE_512-NEXT: ucvtf z0.h, p0/m, z0.s375; VBITS_GE_512-NEXT: ptrue p0.h, vl16376; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h377; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1]378; VBITS_GE_512-NEXT: ret379 %op1 = load <16 x i32>, ptr %a380 %res = uitofp <16 x i32> %op1 to <16 x half>381 store <16 x half> %res, ptr %b382 ret void383}384 385define void @ucvtf_v32i32_v32f16(ptr %a, ptr %b) vscale_range(8,0) #0 {386; CHECK-LABEL: ucvtf_v32i32_v32f16:387; CHECK: // %bb.0:388; CHECK-NEXT: ptrue p0.s, vl32389; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]390; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s391; CHECK-NEXT: ptrue p0.h, vl32392; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h393; CHECK-NEXT: st1h { z0.h }, p0, [x1]394; CHECK-NEXT: ret395 %op1 = load <32 x i32>, ptr %a396 %res = uitofp <32 x i32> %op1 to <32 x half>397 store <32 x half> %res, ptr %b398 ret void399}400 401define void @ucvtf_v64i32_v64f16(ptr %a, ptr %b) vscale_range(16,0) #0 {402; CHECK-LABEL: ucvtf_v64i32_v64f16:403; CHECK: // %bb.0:404; CHECK-NEXT: ptrue p0.s, vl64405; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]406; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s407; CHECK-NEXT: ptrue p0.h, vl64408; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h409; CHECK-NEXT: st1h { z0.h }, p0, [x1]410; CHECK-NEXT: ret411 %op1 = load <64 x i32>, ptr %a412 %res = uitofp <64 x i32> %op1 to <64 x half>413 store <64 x half> %res, ptr %b414 ret void415}416 417;418; UCVTF S -> S419;420 421; Don't use SVE for 64-bit vectors.422define <2 x float> @ucvtf_v2i32_v2f32(<2 x i32> %op1) vscale_range(2,0) #0 {423; CHECK-LABEL: ucvtf_v2i32_v2f32:424; CHECK: // %bb.0:425; CHECK-NEXT: ucvtf v0.2s, v0.2s426; CHECK-NEXT: ret427 %res = uitofp <2 x i32> %op1 to <2 x float>428 ret <2 x float> %res429}430 431; Don't use SVE for 128-bit vectors.432define <4 x float> @ucvtf_v4i32_v4f32(<4 x i32> %op1) vscale_range(2,0) #0 {433; CHECK-LABEL: ucvtf_v4i32_v4f32:434; CHECK: // %bb.0:435; CHECK-NEXT: ucvtf v0.4s, v0.4s436; CHECK-NEXT: ret437 %res = uitofp <4 x i32> %op1 to <4 x float>438 ret <4 x float> %res439}440 441define void @ucvtf_v8i32_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {442; CHECK-LABEL: ucvtf_v8i32_v8f32:443; CHECK: // %bb.0:444; CHECK-NEXT: ptrue p0.s, vl8445; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]446; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s447; CHECK-NEXT: st1w { z0.s }, p0, [x1]448; CHECK-NEXT: ret449 %op1 = load <8 x i32>, ptr %a450 %res = uitofp <8 x i32> %op1 to <8 x float>451 store <8 x float> %res, ptr %b452 ret void453}454 455define void @ucvtf_v16i32_v16f32(ptr %a, ptr %b) #0 {456; VBITS_GE_256-LABEL: ucvtf_v16i32_v16f32:457; VBITS_GE_256: // %bb.0:458; VBITS_GE_256-NEXT: ptrue p0.s, vl8459; VBITS_GE_256-NEXT: mov x8, #8 // =0x8460; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]461; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]462; VBITS_GE_256-NEXT: ucvtf z0.s, p0/m, z0.s463; VBITS_GE_256-NEXT: ucvtf z1.s, p0/m, z1.s464; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]465; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1]466; VBITS_GE_256-NEXT: ret467;468; VBITS_GE_512-LABEL: ucvtf_v16i32_v16f32:469; VBITS_GE_512: // %bb.0:470; VBITS_GE_512-NEXT: ptrue p0.s, vl16471; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]472; VBITS_GE_512-NEXT: ucvtf z0.s, p0/m, z0.s473; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]474; VBITS_GE_512-NEXT: ret475 %op1 = load <16 x i32>, ptr %a476 %res = uitofp <16 x i32> %op1 to <16 x float>477 store <16 x float> %res, ptr %b478 ret void479}480 481define void @ucvtf_v32i32_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 {482; CHECK-LABEL: ucvtf_v32i32_v32f32:483; CHECK: // %bb.0:484; CHECK-NEXT: ptrue p0.s, vl32485; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]486; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s487; CHECK-NEXT: st1w { z0.s }, p0, [x1]488; CHECK-NEXT: ret489 %op1 = load <32 x i32>, ptr %a490 %res = uitofp <32 x i32> %op1 to <32 x float>491 store <32 x float> %res, ptr %b492 ret void493}494 495define void @ucvtf_v64i32_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 {496; CHECK-LABEL: ucvtf_v64i32_v64f32:497; CHECK: // %bb.0:498; CHECK-NEXT: ptrue p0.s, vl64499; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]500; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s501; CHECK-NEXT: st1w { z0.s }, p0, [x1]502; CHECK-NEXT: ret503 %op1 = load <64 x i32>, ptr %a504 %res = uitofp <64 x i32> %op1 to <64 x float>505 store <64 x float> %res, ptr %b506 ret void507}508 509;510; UCVTF S -> D511;512 513; Don't use SVE for 64-bit vectors.514define <1 x double> @ucvtf_v1i32_v1f64(<1 x i32> %op1) vscale_range(2,0) #0 {515; CHECK-LABEL: ucvtf_v1i32_v1f64:516; CHECK: // %bb.0:517; CHECK-NEXT: ushll v0.2d, v0.2s, #0518; CHECK-NEXT: ucvtf v0.2d, v0.2d519; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0520; CHECK-NEXT: ret521 %res = uitofp <1 x i32> %op1 to <1 x double>522 ret <1 x double> %res523}524 525; Don't use SVE for 128-bit vectors.526define <2 x double> @ucvtf_v2i32_v2f64(<2 x i32> %op1) vscale_range(2,0) #0 {527; CHECK-LABEL: ucvtf_v2i32_v2f64:528; CHECK: // %bb.0:529; CHECK-NEXT: ushll v0.2d, v0.2s, #0530; CHECK-NEXT: ucvtf v0.2d, v0.2d531; CHECK-NEXT: ret532 %res = uitofp <2 x i32> %op1 to <2 x double>533 ret <2 x double> %res534}535 536define void @ucvtf_v4i32_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {537; CHECK-LABEL: ucvtf_v4i32_v4f64:538; CHECK: // %bb.0:539; CHECK-NEXT: ldr q0, [x0]540; CHECK-NEXT: ptrue p0.d, vl4541; CHECK-NEXT: uunpklo z0.d, z0.s542; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d543; CHECK-NEXT: st1d { z0.d }, p0, [x1]544; CHECK-NEXT: ret545 %op1 = load <4 x i32>, ptr %a546 %res = uitofp <4 x i32> %op1 to <4 x double>547 store <4 x double> %res, ptr %b548 ret void549}550 551define void @ucvtf_v8i32_v8f64(ptr %a, ptr %b) #0 {552; VBITS_GE_256-LABEL: ucvtf_v8i32_v8f64:553; VBITS_GE_256: // %bb.0:554; VBITS_GE_256-NEXT: ptrue p0.s, vl8555; VBITS_GE_256-NEXT: mov x8, #4 // =0x4556; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0]557; VBITS_GE_256-NEXT: ptrue p0.d, vl4558; VBITS_GE_256-NEXT: movprfx z1, z0559; VBITS_GE_256-NEXT: ext z1.b, z1.b, z0.b, #16560; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s561; VBITS_GE_256-NEXT: uunpklo z1.d, z1.s562; VBITS_GE_256-NEXT: ucvtf z0.d, p0/m, z0.d563; VBITS_GE_256-NEXT: ucvtf z1.d, p0/m, z1.d564; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1]565; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3]566; VBITS_GE_256-NEXT: ret567;568; VBITS_GE_512-LABEL: ucvtf_v8i32_v8f64:569; VBITS_GE_512: // %bb.0:570; VBITS_GE_512-NEXT: ptrue p0.d, vl8571; VBITS_GE_512-NEXT: ld1w { z0.d }, p0/z, [x0]572; VBITS_GE_512-NEXT: ucvtf z0.d, p0/m, z0.d573; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1]574; VBITS_GE_512-NEXT: ret575 %op1 = load <8 x i32>, ptr %a576 %res = uitofp <8 x i32> %op1 to <8 x double>577 store <8 x double> %res, ptr %b578 ret void579}580 581define void @ucvtf_v16i32_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {582; CHECK-LABEL: ucvtf_v16i32_v16f64:583; CHECK: // %bb.0:584; CHECK-NEXT: ptrue p0.d, vl16585; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]586; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d587; CHECK-NEXT: st1d { z0.d }, p0, [x1]588; CHECK-NEXT: ret589 %op1 = load <16 x i32>, ptr %a590 %res = uitofp <16 x i32> %op1 to <16 x double>591 store <16 x double> %res, ptr %b592 ret void593}594 595define void @ucvtf_v32i32_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {596; CHECK-LABEL: ucvtf_v32i32_v32f64:597; CHECK: // %bb.0:598; CHECK-NEXT: ptrue p0.d, vl32599; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]600; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d601; CHECK-NEXT: st1d { z0.d }, p0, [x1]602; CHECK-NEXT: ret603 %op1 = load <32 x i32>, ptr %a604 %res = uitofp <32 x i32> %op1 to <32 x double>605 store <32 x double> %res, ptr %b606 ret void607}608 609;610; UCVTF D -> H611;612 613; Don't use SVE for 64-bit vectors.614define <1 x half> @ucvtf_v1i64_v1f16(<1 x i64> %op1) vscale_range(2,0) #0 {615; CHECK-LABEL: ucvtf_v1i64_v1f16:616; CHECK: // %bb.0:617; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0618; CHECK-NEXT: fmov x8, d0619; CHECK-NEXT: ucvtf h0, x8620; CHECK-NEXT: ret621 %res = uitofp <1 x i64> %op1 to <1 x half>622 ret <1 x half> %res623}624 625; v2f16 is not legal for NEON, so use SVE626define <2 x half> @ucvtf_v2i64_v2f16(<2 x i64> %op1) vscale_range(2,0) #0 {627; CHECK-LABEL: ucvtf_v2i64_v2f16:628; CHECK: // %bb.0:629; CHECK-NEXT: ptrue p0.d, vl4630; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0631; CHECK-NEXT: ucvtf z0.h, p0/m, z0.d632; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s633; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h634; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0635; CHECK-NEXT: ret636 %res = uitofp <2 x i64> %op1 to <2 x half>637 ret <2 x half> %res638}639 640define <4 x half> @ucvtf_v4i64_v4f16(ptr %a) vscale_range(2,0) #0 {641; CHECK-LABEL: ucvtf_v4i64_v4f16:642; CHECK: // %bb.0:643; CHECK-NEXT: ptrue p0.d, vl4644; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]645; CHECK-NEXT: ucvtf z0.h, p0/m, z0.d646; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s647; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h648; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0649; CHECK-NEXT: ret650 %op1 = load <4 x i64>, ptr %a651 %res = uitofp <4 x i64> %op1 to <4 x half>652 ret <4 x half> %res653}654 655define <8 x half> @ucvtf_v8i64_v8f16(ptr %a) #0 {656; VBITS_GE_256-LABEL: ucvtf_v8i64_v8f16:657; VBITS_GE_256: // %bb.0:658; VBITS_GE_256-NEXT: ptrue p0.d, vl4659; VBITS_GE_256-NEXT: mov x8, #4 // =0x4660; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]661; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]662; VBITS_GE_256-NEXT: ucvtf z0.h, p0/m, z0.d663; VBITS_GE_256-NEXT: ucvtf z1.h, p0/m, z1.d664; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s665; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s666; VBITS_GE_256-NEXT: uzp1 z2.h, z0.h, z0.h667; VBITS_GE_256-NEXT: uzp1 z0.h, z1.h, z1.h668; VBITS_GE_256-NEXT: mov v0.d[1], v2.d[0]669; VBITS_GE_256-NEXT: // kill: def $q0 killed $q0 killed $z0670; VBITS_GE_256-NEXT: ret671;672; VBITS_GE_512-LABEL: ucvtf_v8i64_v8f16:673; VBITS_GE_512: // %bb.0:674; VBITS_GE_512-NEXT: ptrue p0.d, vl8675; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]676; VBITS_GE_512-NEXT: ucvtf z0.h, p0/m, z0.d677; VBITS_GE_512-NEXT: uzp1 z0.s, z0.s, z0.s678; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h679; VBITS_GE_512-NEXT: // kill: def $q0 killed $q0 killed $z0680; VBITS_GE_512-NEXT: ret681 %op1 = load <8 x i64>, ptr %a682 %res = uitofp <8 x i64> %op1 to <8 x half>683 ret <8 x half> %res684}685 686define void @ucvtf_v16i64_v16f16(ptr %a, ptr %b) vscale_range(8,0) #0 {687; CHECK-LABEL: ucvtf_v16i64_v16f16:688; CHECK: // %bb.0:689; CHECK-NEXT: ptrue p0.d, vl16690; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]691; CHECK-NEXT: ucvtf z0.h, p0/m, z0.d692; CHECK-NEXT: ptrue p0.s, vl16693; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s694; CHECK-NEXT: st1h { z0.s }, p0, [x1]695; CHECK-NEXT: ret696 %op1 = load <16 x i64>, ptr %a697 %res = uitofp <16 x i64> %op1 to <16 x half>698 store <16 x half> %res, ptr %b699 ret void700}701 702define void @ucvtf_v32i64_v32f16(ptr %a, ptr %b) vscale_range(16,0) #0 {703; CHECK-LABEL: ucvtf_v32i64_v32f16:704; CHECK: // %bb.0:705; CHECK-NEXT: ptrue p0.d, vl32706; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]707; CHECK-NEXT: ucvtf z0.h, p0/m, z0.d708; CHECK-NEXT: ptrue p0.s, vl32709; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s710; CHECK-NEXT: st1h { z0.s }, p0, [x1]711; CHECK-NEXT: ret712 %op1 = load <32 x i64>, ptr %a713 %res = uitofp <32 x i64> %op1 to <32 x half>714 store <32 x half> %res, ptr %b715 ret void716}717 718;719; UCVTF D -> S720;721 722; Don't use SVE for 64-bit vectors.723define <1 x float> @ucvtf_v1i64_v1f32(<1 x i64> %op1) vscale_range(2,0) #0 {724; CHECK-LABEL: ucvtf_v1i64_v1f32:725; CHECK: // %bb.0:726; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0727; CHECK-NEXT: fmov x8, d0728; CHECK-NEXT: movi d1, #0000000000000000729; CHECK-NEXT: ucvtf s0, x8730; CHECK-NEXT: mov v1.s[0], v0.s[0]731; CHECK-NEXT: fmov d0, d1732; CHECK-NEXT: ret733 %res = uitofp <1 x i64> %op1 to <1 x float>734 ret <1 x float> %res735}736 737; Don't use SVE for 128-bit vectors.738define <2 x float> @ucvtf_v2i64_v2f32(<2 x i64> %op1) vscale_range(2,0) #0 {739; CHECK-LABEL: ucvtf_v2i64_v2f32:740; CHECK: // %bb.0:741; CHECK-NEXT: mov x8, v0.d[1]742; CHECK-NEXT: fmov x9, d0743; CHECK-NEXT: ucvtf s0, x9744; CHECK-NEXT: ucvtf s1, x8745; CHECK-NEXT: mov v0.s[1], v1.s[0]746; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0747; CHECK-NEXT: ret748 %res = uitofp <2 x i64> %op1 to <2 x float>749 ret <2 x float> %res750}751 752define <4 x float> @ucvtf_v4i64_v4f32(ptr %a) vscale_range(2,0) #0 {753; CHECK-LABEL: ucvtf_v4i64_v4f32:754; CHECK: // %bb.0:755; CHECK-NEXT: ptrue p0.d, vl4756; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]757; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d758; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s759; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0760; CHECK-NEXT: ret761 %op1 = load <4 x i64>, ptr %a762 %res = uitofp <4 x i64> %op1 to <4 x float>763 ret <4 x float> %res764}765 766define void @ucvtf_v8i64_v8f32(ptr %a, ptr %b) #0 {767; VBITS_GE_256-LABEL: ucvtf_v8i64_v8f32:768; VBITS_GE_256: // %bb.0:769; VBITS_GE_256-NEXT: ptrue p0.d, vl4770; VBITS_GE_256-NEXT: mov x8, #4 // =0x4771; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]772; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]773; VBITS_GE_256-NEXT: ucvtf z0.s, p0/m, z0.d774; VBITS_GE_256-NEXT: ucvtf z1.s, p0/m, z1.d775; VBITS_GE_256-NEXT: ptrue p0.s, vl4776; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s777; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s778; VBITS_GE_256-NEXT: splice z1.s, p0, z1.s, z0.s779; VBITS_GE_256-NEXT: ptrue p0.s, vl8780; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1]781; VBITS_GE_256-NEXT: ret782;783; VBITS_GE_512-LABEL: ucvtf_v8i64_v8f32:784; VBITS_GE_512: // %bb.0:785; VBITS_GE_512-NEXT: ptrue p0.d, vl8786; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]787; VBITS_GE_512-NEXT: ucvtf z0.s, p0/m, z0.d788; VBITS_GE_512-NEXT: ptrue p0.s, vl8789; VBITS_GE_512-NEXT: uzp1 z0.s, z0.s, z0.s790; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]791; VBITS_GE_512-NEXT: ret792 %op1 = load <8 x i64>, ptr %a793 %res = uitofp <8 x i64> %op1 to <8 x float>794 store <8 x float> %res, ptr %b795 ret void796}797 798define void @ucvtf_v16i64_v16f32(ptr %a, ptr %b) vscale_range(8,0) #0 {799; CHECK-LABEL: ucvtf_v16i64_v16f32:800; CHECK: // %bb.0:801; CHECK-NEXT: ptrue p0.d, vl16802; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]803; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d804; CHECK-NEXT: ptrue p0.s, vl16805; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s806; CHECK-NEXT: st1w { z0.s }, p0, [x1]807; CHECK-NEXT: ret808 %op1 = load <16 x i64>, ptr %a809 %res = uitofp <16 x i64> %op1 to <16 x float>810 store <16 x float> %res, ptr %b811 ret void812}813 814define void @ucvtf_v32i64_v32f32(ptr %a, ptr %b) vscale_range(16,0) #0 {815; CHECK-LABEL: ucvtf_v32i64_v32f32:816; CHECK: // %bb.0:817; CHECK-NEXT: ptrue p0.d, vl32818; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]819; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d820; CHECK-NEXT: ptrue p0.s, vl32821; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s822; CHECK-NEXT: st1w { z0.s }, p0, [x1]823; CHECK-NEXT: ret824 %op1 = load <32 x i64>, ptr %a825 %res = uitofp <32 x i64> %op1 to <32 x float>826 store <32 x float> %res, ptr %b827 ret void828}829 830;831; UCVTF D -> D832;833 834; Don't use SVE for 64-bit vectors.835define <1 x double> @ucvtf_v1i64_v1f64(<1 x i64> %op1) vscale_range(2,0) #0 {836; CHECK-LABEL: ucvtf_v1i64_v1f64:837; CHECK: // %bb.0:838; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0839; CHECK-NEXT: ucvtf d0, d0840; CHECK-NEXT: ret841 %res = uitofp <1 x i64> %op1 to <1 x double>842 ret <1 x double> %res843}844 845; Don't use SVE for 128-bit vectors.846define <2 x double> @ucvtf_v2i64_v2f64(<2 x i64> %op1) vscale_range(2,0) #0 {847; CHECK-LABEL: ucvtf_v2i64_v2f64:848; CHECK: // %bb.0:849; CHECK-NEXT: ucvtf v0.2d, v0.2d850; CHECK-NEXT: ret851 %res = uitofp <2 x i64> %op1 to <2 x double>852 ret <2 x double> %res853}854 855define void @ucvtf_v4i64_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {856; CHECK-LABEL: ucvtf_v4i64_v4f64:857; CHECK: // %bb.0:858; CHECK-NEXT: ptrue p0.d, vl4859; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]860; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d861; CHECK-NEXT: st1d { z0.d }, p0, [x1]862; CHECK-NEXT: ret863 %op1 = load <4 x i64>, ptr %a864 %res = uitofp <4 x i64> %op1 to <4 x double>865 store <4 x double> %res, ptr %b866 ret void867}868 869define void @ucvtf_v8i64_v8f64(ptr %a, ptr %b) #0 {870; VBITS_GE_256-LABEL: ucvtf_v8i64_v8f64:871; VBITS_GE_256: // %bb.0:872; VBITS_GE_256-NEXT: ptrue p0.d, vl4873; VBITS_GE_256-NEXT: mov x8, #4 // =0x4874; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]875; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]876; VBITS_GE_256-NEXT: ucvtf z0.d, p0/m, z0.d877; VBITS_GE_256-NEXT: ucvtf z1.d, p0/m, z1.d878; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]879; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1]880; VBITS_GE_256-NEXT: ret881;882; VBITS_GE_512-LABEL: ucvtf_v8i64_v8f64:883; VBITS_GE_512: // %bb.0:884; VBITS_GE_512-NEXT: ptrue p0.d, vl8885; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]886; VBITS_GE_512-NEXT: ucvtf z0.d, p0/m, z0.d887; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1]888; VBITS_GE_512-NEXT: ret889 %op1 = load <8 x i64>, ptr %a890 %res = uitofp <8 x i64> %op1 to <8 x double>891 store <8 x double> %res, ptr %b892 ret void893}894 895define void @ucvtf_v16i64_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {896; CHECK-LABEL: ucvtf_v16i64_v16f64:897; CHECK: // %bb.0:898; CHECK-NEXT: ptrue p0.d, vl16899; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]900; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d901; CHECK-NEXT: st1d { z0.d }, p0, [x1]902; CHECK-NEXT: ret903 %op1 = load <16 x i64>, ptr %a904 %res = uitofp <16 x i64> %op1 to <16 x double>905 store <16 x double> %res, ptr %b906 ret void907}908 909define void @ucvtf_v32i64_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {910; CHECK-LABEL: ucvtf_v32i64_v32f64:911; CHECK: // %bb.0:912; CHECK-NEXT: ptrue p0.d, vl32913; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]914; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d915; CHECK-NEXT: st1d { z0.d }, p0, [x1]916; CHECK-NEXT: ret917 %op1 = load <32 x i64>, ptr %a918 %res = uitofp <32 x i64> %op1 to <32 x double>919 store <32 x double> %res, ptr %b920 ret void921}922 923;924; SCVTF H -> H925;926 927; Don't use SVE for 64-bit vectors.928define <4 x half> @scvtf_v4i16_v4f16(<4 x i16> %op1) vscale_range(2,0) #0 {929; CHECK-LABEL: scvtf_v4i16_v4f16:930; CHECK: // %bb.0:931; CHECK-NEXT: scvtf v0.4h, v0.4h932; CHECK-NEXT: ret933 %res = sitofp <4 x i16> %op1 to <4 x half>934 ret <4 x half> %res935}936 937; Don't use SVE for 128-bit vectors.938define void @scvtf_v8i16_v8f16(ptr %a, ptr %b) vscale_range(2,0) #0 {939; CHECK-LABEL: scvtf_v8i16_v8f16:940; CHECK: // %bb.0:941; CHECK-NEXT: ldr q0, [x0]942; CHECK-NEXT: scvtf v0.8h, v0.8h943; CHECK-NEXT: str q0, [x1]944; CHECK-NEXT: ret945 %op1 = load <8 x i16>, ptr %a946 %res = sitofp <8 x i16> %op1 to <8 x half>947 store <8 x half> %res, ptr %b948 ret void949}950 951define void @scvtf_v16i16_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {952; CHECK-LABEL: scvtf_v16i16_v16f16:953; CHECK: // %bb.0:954; CHECK-NEXT: ptrue p0.h, vl16955; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]956; CHECK-NEXT: scvtf z0.h, p0/m, z0.h957; CHECK-NEXT: st1h { z0.h }, p0, [x1]958; CHECK-NEXT: ret959 %op1 = load <16 x i16>, ptr %a960 %res = sitofp <16 x i16> %op1 to <16 x half>961 store <16 x half> %res, ptr %b962 ret void963}964 965define void @scvtf_v32i16_v32f16(ptr %a, ptr %b) #0 {966; VBITS_GE_256-LABEL: scvtf_v32i16_v32f16:967; VBITS_GE_256: // %bb.0:968; VBITS_GE_256-NEXT: ptrue p0.h, vl16969; VBITS_GE_256-NEXT: mov x8, #16 // =0x10970; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]971; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]972; VBITS_GE_256-NEXT: scvtf z0.h, p0/m, z0.h973; VBITS_GE_256-NEXT: scvtf z1.h, p0/m, z1.h974; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]975; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x1]976; VBITS_GE_256-NEXT: ret977;978; VBITS_GE_512-LABEL: scvtf_v32i16_v32f16:979; VBITS_GE_512: // %bb.0:980; VBITS_GE_512-NEXT: ptrue p0.h, vl32981; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]982; VBITS_GE_512-NEXT: scvtf z0.h, p0/m, z0.h983; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1]984; VBITS_GE_512-NEXT: ret985 %op1 = load <32 x i16>, ptr %a986 %res = sitofp <32 x i16> %op1 to <32 x half>987 store <32 x half> %res, ptr %b988 ret void989}990 991define void @scvtf_v64i16_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 {992; CHECK-LABEL: scvtf_v64i16_v64f16:993; CHECK: // %bb.0:994; CHECK-NEXT: ptrue p0.h, vl64995; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]996; CHECK-NEXT: scvtf z0.h, p0/m, z0.h997; CHECK-NEXT: st1h { z0.h }, p0, [x1]998; CHECK-NEXT: ret999 %op1 = load <64 x i16>, ptr %a1000 %res = sitofp <64 x i16> %op1 to <64 x half>1001 store <64 x half> %res, ptr %b1002 ret void1003}1004 1005define void @scvtf_v128i16_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 {1006; CHECK-LABEL: scvtf_v128i16_v128f16:1007; CHECK: // %bb.0:1008; CHECK-NEXT: ptrue p0.h, vl1281009; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1010; CHECK-NEXT: scvtf z0.h, p0/m, z0.h1011; CHECK-NEXT: st1h { z0.h }, p0, [x1]1012; CHECK-NEXT: ret1013 %op1 = load <128 x i16>, ptr %a1014 %res = sitofp <128 x i16> %op1 to <128 x half>1015 store <128 x half> %res, ptr %b1016 ret void1017}1018 1019;1020; SCVTF H -> S1021;1022 1023; Don't use SVE for 64-bit vectors.1024define <2 x float> @scvtf_v2i16_v2f32(<2 x i16> %op1) vscale_range(2,0) #0 {1025; CHECK-LABEL: scvtf_v2i16_v2f32:1026; CHECK: // %bb.0:1027; CHECK-NEXT: shl v0.2s, v0.2s, #161028; CHECK-NEXT: sshr v0.2s, v0.2s, #161029; CHECK-NEXT: scvtf v0.2s, v0.2s1030; CHECK-NEXT: ret1031 %res = sitofp <2 x i16> %op1 to <2 x float>1032 ret <2 x float> %res1033}1034 1035; Don't use SVE for 128-bit vectors.1036define <4 x float> @scvtf_v4i16_v4f32(<4 x i16> %op1) vscale_range(2,0) #0 {1037; CHECK-LABEL: scvtf_v4i16_v4f32:1038; CHECK: // %bb.0:1039; CHECK-NEXT: sshll v0.4s, v0.4h, #01040; CHECK-NEXT: scvtf v0.4s, v0.4s1041; CHECK-NEXT: ret1042 %res = sitofp <4 x i16> %op1 to <4 x float>1043 ret <4 x float> %res1044}1045 1046define void @scvtf_v8i16_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {1047; CHECK-LABEL: scvtf_v8i16_v8f32:1048; CHECK: // %bb.0:1049; CHECK-NEXT: ldr q0, [x0]1050; CHECK-NEXT: ptrue p0.s, vl81051; CHECK-NEXT: sunpklo z0.s, z0.h1052; CHECK-NEXT: scvtf z0.s, p0/m, z0.s1053; CHECK-NEXT: st1w { z0.s }, p0, [x1]1054; CHECK-NEXT: ret1055 %op1 = load <8 x i16>, ptr %a1056 %res = sitofp <8 x i16> %op1 to <8 x float>1057 store <8 x float> %res, ptr %b1058 ret void1059}1060 1061define void @scvtf_v16i16_v16f32(ptr %a, ptr %b) #0 {1062; VBITS_GE_256-LABEL: scvtf_v16i16_v16f32:1063; VBITS_GE_256: // %bb.0:1064; VBITS_GE_256-NEXT: ptrue p0.h, vl161065; VBITS_GE_256-NEXT: mov x8, #8 // =0x81066; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0]1067; VBITS_GE_256-NEXT: ptrue p0.s, vl81068; VBITS_GE_256-NEXT: movprfx z1, z01069; VBITS_GE_256-NEXT: ext z1.b, z1.b, z0.b, #161070; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h1071; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h1072; VBITS_GE_256-NEXT: scvtf z0.s, p0/m, z0.s1073; VBITS_GE_256-NEXT: scvtf z1.s, p0/m, z1.s1074; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1]1075; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1, x8, lsl #2]1076; VBITS_GE_256-NEXT: ret1077;1078; VBITS_GE_512-LABEL: scvtf_v16i16_v16f32:1079; VBITS_GE_512: // %bb.0:1080; VBITS_GE_512-NEXT: ptrue p0.h, vl161081; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]1082; VBITS_GE_512-NEXT: ptrue p0.s, vl161083; VBITS_GE_512-NEXT: sunpklo z0.s, z0.h1084; VBITS_GE_512-NEXT: scvtf z0.s, p0/m, z0.s1085; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]1086; VBITS_GE_512-NEXT: ret1087 %op1 = load <16 x i16>, ptr %a1088 %res = sitofp <16 x i16> %op1 to <16 x float>1089 store <16 x float> %res, ptr %b1090 ret void1091}1092 1093define void @scvtf_v32i16_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 {1094; CHECK-LABEL: scvtf_v32i16_v32f32:1095; CHECK: // %bb.0:1096; CHECK-NEXT: ptrue p0.h, vl321097; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1098; CHECK-NEXT: ptrue p0.s, vl321099; CHECK-NEXT: sunpklo z0.s, z0.h1100; CHECK-NEXT: scvtf z0.s, p0/m, z0.s1101; CHECK-NEXT: st1w { z0.s }, p0, [x1]1102; CHECK-NEXT: ret1103 %op1 = load <32 x i16>, ptr %a1104 %res = sitofp <32 x i16> %op1 to <32 x float>1105 store <32 x float> %res, ptr %b1106 ret void1107}1108 1109define void @scvtf_v64i16_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 {1110; CHECK-LABEL: scvtf_v64i16_v64f32:1111; CHECK: // %bb.0:1112; CHECK-NEXT: ptrue p0.h, vl641113; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1114; CHECK-NEXT: ptrue p0.s, vl641115; CHECK-NEXT: sunpklo z0.s, z0.h1116; CHECK-NEXT: scvtf z0.s, p0/m, z0.s1117; CHECK-NEXT: st1w { z0.s }, p0, [x1]1118; CHECK-NEXT: ret1119 %op1 = load <64 x i16>, ptr %a1120 %res = sitofp <64 x i16> %op1 to <64 x float>1121 store <64 x float> %res, ptr %b1122 ret void1123}1124 1125;1126; SCVTF H -> D1127;1128 1129; v1i16 is perfered to be widened to v4i16, which pushes the output into SVE types, so use SVE1130define <1 x double> @scvtf_v1i16_v1f64(<1 x i16> %op1) vscale_range(2,0) #0 {1131; CHECK-LABEL: scvtf_v1i16_v1f64:1132; CHECK: // %bb.0:1133; CHECK-NEXT: // kill: def $d0 killed $d0 def $z01134; CHECK-NEXT: ptrue p0.d, vl41135; CHECK-NEXT: sunpklo z0.s, z0.h1136; CHECK-NEXT: sunpklo z0.d, z0.s1137; CHECK-NEXT: scvtf z0.d, p0/m, z0.d1138; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z01139; CHECK-NEXT: ret1140 %res = sitofp <1 x i16> %op1 to <1 x double>1141 ret <1 x double> %res1142}1143 1144; Don't use SVE for 128-bit vectors.1145define <2 x double> @scvtf_v2i16_v2f64(<2 x i16> %op1) vscale_range(2,0) #0 {1146; CHECK-LABEL: scvtf_v2i16_v2f64:1147; CHECK: // %bb.0:1148; CHECK-NEXT: shl v0.2s, v0.2s, #161149; CHECK-NEXT: sshr v0.2s, v0.2s, #161150; CHECK-NEXT: sshll v0.2d, v0.2s, #01151; CHECK-NEXT: scvtf v0.2d, v0.2d1152; CHECK-NEXT: ret1153 %res = sitofp <2 x i16> %op1 to <2 x double>1154 ret <2 x double> %res1155}1156 1157define void @scvtf_v4i16_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {1158; CHECK-LABEL: scvtf_v4i16_v4f64:1159; CHECK: // %bb.0:1160; CHECK-NEXT: ldr d0, [x0]1161; CHECK-NEXT: ptrue p0.d, vl41162; CHECK-NEXT: sunpklo z0.s, z0.h1163; CHECK-NEXT: sunpklo z0.d, z0.s1164; CHECK-NEXT: scvtf z0.d, p0/m, z0.d1165; CHECK-NEXT: st1d { z0.d }, p0, [x1]1166; CHECK-NEXT: ret1167 %op1 = load <4 x i16>, ptr %a1168 %res = sitofp <4 x i16> %op1 to <4 x double>1169 store <4 x double> %res, ptr %b1170 ret void1171}1172 1173define void @scvtf_v8i16_v8f64(ptr %a, ptr %b) #0 {1174; VBITS_GE_256-LABEL: scvtf_v8i16_v8f64:1175; VBITS_GE_256: // %bb.0:1176; VBITS_GE_256-NEXT: ldr q0, [x0]1177; VBITS_GE_256-NEXT: ptrue p0.d, vl41178; VBITS_GE_256-NEXT: mov x8, #4 // =0x41179; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #81180; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h1181; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h1182; VBITS_GE_256-NEXT: sunpklo z0.d, z0.s1183; VBITS_GE_256-NEXT: sunpklo z1.d, z1.s1184; VBITS_GE_256-NEXT: scvtf z0.d, p0/m, z0.d1185; VBITS_GE_256-NEXT: scvtf z1.d, p0/m, z1.d1186; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1]1187; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3]1188; VBITS_GE_256-NEXT: ret1189;1190; VBITS_GE_512-LABEL: scvtf_v8i16_v8f64:1191; VBITS_GE_512: // %bb.0:1192; VBITS_GE_512-NEXT: ldr q0, [x0]1193; VBITS_GE_512-NEXT: ptrue p0.d, vl81194; VBITS_GE_512-NEXT: sunpklo z0.s, z0.h1195; VBITS_GE_512-NEXT: sunpklo z0.d, z0.s1196; VBITS_GE_512-NEXT: scvtf z0.d, p0/m, z0.d1197; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1]1198; VBITS_GE_512-NEXT: ret1199 %op1 = load <8 x i16>, ptr %a1200 %res = sitofp <8 x i16> %op1 to <8 x double>1201 store <8 x double> %res, ptr %b1202 ret void1203}1204 1205define void @scvtf_v16i16_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {1206; CHECK-LABEL: scvtf_v16i16_v16f64:1207; CHECK: // %bb.0:1208; CHECK-NEXT: ptrue p0.h, vl161209; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1210; CHECK-NEXT: ptrue p0.d, vl161211; CHECK-NEXT: sunpklo z0.s, z0.h1212; CHECK-NEXT: sunpklo z0.d, z0.s1213; CHECK-NEXT: scvtf z0.d, p0/m, z0.d1214; CHECK-NEXT: st1d { z0.d }, p0, [x1]1215; CHECK-NEXT: ret1216 %op1 = load <16 x i16>, ptr %a1217 %res = sitofp <16 x i16> %op1 to <16 x double>1218 store <16 x double> %res, ptr %b1219 ret void1220}1221 1222define void @scvtf_v32i16_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {1223; CHECK-LABEL: scvtf_v32i16_v32f64:1224; CHECK: // %bb.0:1225; CHECK-NEXT: ptrue p0.h, vl321226; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1227; CHECK-NEXT: ptrue p0.d, vl321228; CHECK-NEXT: sunpklo z0.s, z0.h1229; CHECK-NEXT: sunpklo z0.d, z0.s1230; CHECK-NEXT: scvtf z0.d, p0/m, z0.d1231; CHECK-NEXT: st1d { z0.d }, p0, [x1]1232; CHECK-NEXT: ret1233 %op1 = load <32 x i16>, ptr %a1234 %res = sitofp <32 x i16> %op1 to <32 x double>1235 store <32 x double> %res, ptr %b1236 ret void1237}1238 1239;1240; SCVTF S -> H1241;1242 1243; Don't use SVE for 64-bit vectors.1244define <2 x half> @scvtf_v2i32_v2f16(<2 x i32> %op1) vscale_range(2,0) #0 {1245; CHECK-LABEL: scvtf_v2i32_v2f16:1246; CHECK: // %bb.0:1247; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01248; CHECK-NEXT: scvtf v0.4s, v0.4s1249; CHECK-NEXT: fcvtn v0.4h, v0.4s1250; CHECK-NEXT: ret1251 %res = sitofp <2 x i32> %op1 to <2 x half>1252 ret <2 x half> %res1253}1254 1255; Don't use SVE for 128-bit vectors.1256define <4 x half> @scvtf_v4i32_v4f16(<4 x i32> %op1) vscale_range(2,0) #0 {1257; CHECK-LABEL: scvtf_v4i32_v4f16:1258; CHECK: // %bb.0:1259; CHECK-NEXT: scvtf v0.4s, v0.4s1260; CHECK-NEXT: fcvtn v0.4h, v0.4s1261; CHECK-NEXT: ret1262 %res = sitofp <4 x i32> %op1 to <4 x half>1263 ret <4 x half> %res1264}1265 1266define <8 x half> @scvtf_v8i32_v8f16(ptr %a) vscale_range(2,0) #0 {1267; CHECK-LABEL: scvtf_v8i32_v8f16:1268; CHECK: // %bb.0:1269; CHECK-NEXT: ptrue p0.s, vl81270; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1271; CHECK-NEXT: scvtf z0.h, p0/m, z0.s1272; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h1273; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z01274; CHECK-NEXT: ret1275 %op1 = load <8 x i32>, ptr %a1276 %res = sitofp <8 x i32> %op1 to <8 x half>1277 ret <8 x half> %res1278}1279 1280define void @scvtf_v16i32_v16f16(ptr %a, ptr %b) #0 {1281; VBITS_GE_256-LABEL: scvtf_v16i32_v16f16:1282; VBITS_GE_256: // %bb.0:1283; VBITS_GE_256-NEXT: ptrue p0.s, vl81284; VBITS_GE_256-NEXT: mov x8, #8 // =0x81285; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]1286; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]1287; VBITS_GE_256-NEXT: scvtf z0.h, p0/m, z0.s1288; VBITS_GE_256-NEXT: scvtf z1.h, p0/m, z1.s1289; VBITS_GE_256-NEXT: ptrue p0.h, vl81290; VBITS_GE_256-NEXT: uzp1 z0.h, z0.h, z0.h1291; VBITS_GE_256-NEXT: uzp1 z1.h, z1.h, z1.h1292; VBITS_GE_256-NEXT: splice z1.h, p0, z1.h, z0.h1293; VBITS_GE_256-NEXT: ptrue p0.h, vl161294; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x1]1295; VBITS_GE_256-NEXT: ret1296;1297; VBITS_GE_512-LABEL: scvtf_v16i32_v16f16:1298; VBITS_GE_512: // %bb.0:1299; VBITS_GE_512-NEXT: ptrue p0.s, vl161300; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]1301; VBITS_GE_512-NEXT: scvtf z0.h, p0/m, z0.s1302; VBITS_GE_512-NEXT: ptrue p0.h, vl161303; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h1304; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1]1305; VBITS_GE_512-NEXT: ret1306 %op1 = load <16 x i32>, ptr %a1307 %res = sitofp <16 x i32> %op1 to <16 x half>1308 store <16 x half> %res, ptr %b1309 ret void1310}1311 1312define void @scvtf_v32i32_v32f16(ptr %a, ptr %b) vscale_range(8,0) #0 {1313; CHECK-LABEL: scvtf_v32i32_v32f16:1314; CHECK: // %bb.0:1315; CHECK-NEXT: ptrue p0.s, vl321316; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1317; CHECK-NEXT: scvtf z0.h, p0/m, z0.s1318; CHECK-NEXT: ptrue p0.h, vl321319; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h1320; CHECK-NEXT: st1h { z0.h }, p0, [x1]1321; CHECK-NEXT: ret1322 %op1 = load <32 x i32>, ptr %a1323 %res = sitofp <32 x i32> %op1 to <32 x half>1324 store <32 x half> %res, ptr %b1325 ret void1326}1327 1328define void @scvtf_v64i32_v64f16(ptr %a, ptr %b) vscale_range(16,0) #0 {1329; CHECK-LABEL: scvtf_v64i32_v64f16:1330; CHECK: // %bb.0:1331; CHECK-NEXT: ptrue p0.s, vl641332; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1333; CHECK-NEXT: scvtf z0.h, p0/m, z0.s1334; CHECK-NEXT: ptrue p0.h, vl641335; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h1336; CHECK-NEXT: st1h { z0.h }, p0, [x1]1337; CHECK-NEXT: ret1338 %op1 = load <64 x i32>, ptr %a1339 %res = sitofp <64 x i32> %op1 to <64 x half>1340 store <64 x half> %res, ptr %b1341 ret void1342}1343 1344;1345; SCVTF S -> S1346;1347 1348; Don't use SVE for 64-bit vectors.1349define <2 x float> @scvtf_v2i32_v2f32(<2 x i32> %op1) vscale_range(2,0) #0 {1350; CHECK-LABEL: scvtf_v2i32_v2f32:1351; CHECK: // %bb.0:1352; CHECK-NEXT: scvtf v0.2s, v0.2s1353; CHECK-NEXT: ret1354 %res = sitofp <2 x i32> %op1 to <2 x float>1355 ret <2 x float> %res1356}1357 1358; Don't use SVE for 128-bit vectors.1359define <4 x float> @scvtf_v4i32_v4f32(<4 x i32> %op1) vscale_range(2,0) #0 {1360; CHECK-LABEL: scvtf_v4i32_v4f32:1361; CHECK: // %bb.0:1362; CHECK-NEXT: scvtf v0.4s, v0.4s1363; CHECK-NEXT: ret1364 %res = sitofp <4 x i32> %op1 to <4 x float>1365 ret <4 x float> %res1366}1367 1368define void @scvtf_v8i32_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {1369; CHECK-LABEL: scvtf_v8i32_v8f32:1370; CHECK: // %bb.0:1371; CHECK-NEXT: ptrue p0.s, vl81372; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1373; CHECK-NEXT: scvtf z0.s, p0/m, z0.s1374; CHECK-NEXT: st1w { z0.s }, p0, [x1]1375; CHECK-NEXT: ret1376 %op1 = load <8 x i32>, ptr %a1377 %res = sitofp <8 x i32> %op1 to <8 x float>1378 store <8 x float> %res, ptr %b1379 ret void1380}1381 1382define void @scvtf_v16i32_v16f32(ptr %a, ptr %b) #0 {1383; VBITS_GE_256-LABEL: scvtf_v16i32_v16f32:1384; VBITS_GE_256: // %bb.0:1385; VBITS_GE_256-NEXT: ptrue p0.s, vl81386; VBITS_GE_256-NEXT: mov x8, #8 // =0x81387; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]1388; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]1389; VBITS_GE_256-NEXT: scvtf z0.s, p0/m, z0.s1390; VBITS_GE_256-NEXT: scvtf z1.s, p0/m, z1.s1391; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]1392; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1]1393; VBITS_GE_256-NEXT: ret1394;1395; VBITS_GE_512-LABEL: scvtf_v16i32_v16f32:1396; VBITS_GE_512: // %bb.0:1397; VBITS_GE_512-NEXT: ptrue p0.s, vl161398; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]1399; VBITS_GE_512-NEXT: scvtf z0.s, p0/m, z0.s1400; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]1401; VBITS_GE_512-NEXT: ret1402 %op1 = load <16 x i32>, ptr %a1403 %res = sitofp <16 x i32> %op1 to <16 x float>1404 store <16 x float> %res, ptr %b1405 ret void1406}1407 1408define void @scvtf_v32i32_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 {1409; CHECK-LABEL: scvtf_v32i32_v32f32:1410; CHECK: // %bb.0:1411; CHECK-NEXT: ptrue p0.s, vl321412; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1413; CHECK-NEXT: scvtf z0.s, p0/m, z0.s1414; CHECK-NEXT: st1w { z0.s }, p0, [x1]1415; CHECK-NEXT: ret1416 %op1 = load <32 x i32>, ptr %a1417 %res = sitofp <32 x i32> %op1 to <32 x float>1418 store <32 x float> %res, ptr %b1419 ret void1420}1421 1422define void @scvtf_v64i32_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 {1423; CHECK-LABEL: scvtf_v64i32_v64f32:1424; CHECK: // %bb.0:1425; CHECK-NEXT: ptrue p0.s, vl641426; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1427; CHECK-NEXT: scvtf z0.s, p0/m, z0.s1428; CHECK-NEXT: st1w { z0.s }, p0, [x1]1429; CHECK-NEXT: ret1430 %op1 = load <64 x i32>, ptr %a1431 %res = sitofp <64 x i32> %op1 to <64 x float>1432 store <64 x float> %res, ptr %b1433 ret void1434}1435 1436;1437; SCVTF S -> D1438;1439 1440; Don't use SVE for 64-bit vectors.1441define <1 x double> @scvtf_v1i32_v1f64(<1 x i32> %op1) vscale_range(2,0) #0 {1442; CHECK-LABEL: scvtf_v1i32_v1f64:1443; CHECK: // %bb.0:1444; CHECK-NEXT: sshll v0.2d, v0.2s, #01445; CHECK-NEXT: scvtf v0.2d, v0.2d1446; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q01447; CHECK-NEXT: ret1448 %res = sitofp <1 x i32> %op1 to <1 x double>1449 ret <1 x double> %res1450}1451 1452; Don't use SVE for 128-bit vectors.1453define <2 x double> @scvtf_v2i32_v2f64(<2 x i32> %op1) vscale_range(2,0) #0 {1454; CHECK-LABEL: scvtf_v2i32_v2f64:1455; CHECK: // %bb.0:1456; CHECK-NEXT: sshll v0.2d, v0.2s, #01457; CHECK-NEXT: scvtf v0.2d, v0.2d1458; CHECK-NEXT: ret1459 %res = sitofp <2 x i32> %op1 to <2 x double>1460 ret <2 x double> %res1461}1462 1463define void @scvtf_v4i32_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {1464; CHECK-LABEL: scvtf_v4i32_v4f64:1465; CHECK: // %bb.0:1466; CHECK-NEXT: ldr q0, [x0]1467; CHECK-NEXT: ptrue p0.d, vl41468; CHECK-NEXT: sunpklo z0.d, z0.s1469; CHECK-NEXT: scvtf z0.d, p0/m, z0.d1470; CHECK-NEXT: st1d { z0.d }, p0, [x1]1471; CHECK-NEXT: ret1472 %op1 = load <4 x i32>, ptr %a1473 %res = sitofp <4 x i32> %op1 to <4 x double>1474 store <4 x double> %res, ptr %b1475 ret void1476}1477 1478define void @scvtf_v8i32_v8f64(ptr %a, ptr %b) #0 {1479; VBITS_GE_256-LABEL: scvtf_v8i32_v8f64:1480; VBITS_GE_256: // %bb.0:1481; VBITS_GE_256-NEXT: ptrue p0.s, vl81482; VBITS_GE_256-NEXT: mov x8, #4 // =0x41483; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0]1484; VBITS_GE_256-NEXT: ptrue p0.d, vl41485; VBITS_GE_256-NEXT: movprfx z1, z01486; VBITS_GE_256-NEXT: ext z1.b, z1.b, z0.b, #161487; VBITS_GE_256-NEXT: sunpklo z0.d, z0.s1488; VBITS_GE_256-NEXT: sunpklo z1.d, z1.s1489; VBITS_GE_256-NEXT: scvtf z0.d, p0/m, z0.d1490; VBITS_GE_256-NEXT: scvtf z1.d, p0/m, z1.d1491; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1]1492; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3]1493; VBITS_GE_256-NEXT: ret1494;1495; VBITS_GE_512-LABEL: scvtf_v8i32_v8f64:1496; VBITS_GE_512: // %bb.0:1497; VBITS_GE_512-NEXT: ptrue p0.s, vl81498; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]1499; VBITS_GE_512-NEXT: ptrue p0.d, vl81500; VBITS_GE_512-NEXT: sunpklo z0.d, z0.s1501; VBITS_GE_512-NEXT: scvtf z0.d, p0/m, z0.d1502; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1]1503; VBITS_GE_512-NEXT: ret1504 %op1 = load <8 x i32>, ptr %a1505 %res = sitofp <8 x i32> %op1 to <8 x double>1506 store <8 x double> %res, ptr %b1507 ret void1508}1509 1510define void @scvtf_v16i32_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {1511; CHECK-LABEL: scvtf_v16i32_v16f64:1512; CHECK: // %bb.0:1513; CHECK-NEXT: ptrue p0.s, vl161514; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1515; CHECK-NEXT: ptrue p0.d, vl161516; CHECK-NEXT: sunpklo z0.d, z0.s1517; CHECK-NEXT: scvtf z0.d, p0/m, z0.d1518; CHECK-NEXT: st1d { z0.d }, p0, [x1]1519; CHECK-NEXT: ret1520 %op1 = load <16 x i32>, ptr %a1521 %res = sitofp <16 x i32> %op1 to <16 x double>1522 store <16 x double> %res, ptr %b1523 ret void1524}1525 1526define void @scvtf_v32i32_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {1527; CHECK-LABEL: scvtf_v32i32_v32f64:1528; CHECK: // %bb.0:1529; CHECK-NEXT: ptrue p0.s, vl321530; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1531; CHECK-NEXT: ptrue p0.d, vl321532; CHECK-NEXT: sunpklo z0.d, z0.s1533; CHECK-NEXT: scvtf z0.d, p0/m, z0.d1534; CHECK-NEXT: st1d { z0.d }, p0, [x1]1535; CHECK-NEXT: ret1536 %op1 = load <32 x i32>, ptr %a1537 %res = sitofp <32 x i32> %op1 to <32 x double>1538 store <32 x double> %res, ptr %b1539 ret void1540}1541 1542;1543; SCVTF D -> H1544;1545 1546; Don't use SVE for 64-bit vectors.1547define <1 x half> @scvtf_v1i64_v1f16(<1 x i64> %op1) vscale_range(2,0) #0 {1548; CHECK-LABEL: scvtf_v1i64_v1f16:1549; CHECK: // %bb.0:1550; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01551; CHECK-NEXT: fmov x8, d01552; CHECK-NEXT: scvtf h0, x81553; CHECK-NEXT: ret1554 %res = sitofp <1 x i64> %op1 to <1 x half>1555 ret <1 x half> %res1556}1557 1558; v2f16 is not legal for NEON, so use SVE1559define <2 x half> @scvtf_v2i64_v2f16(<2 x i64> %op1) vscale_range(2,0) #0 {1560; CHECK-LABEL: scvtf_v2i64_v2f16:1561; CHECK: // %bb.0:1562; CHECK-NEXT: ptrue p0.d, vl41563; CHECK-NEXT: // kill: def $q0 killed $q0 def $z01564; CHECK-NEXT: scvtf z0.h, p0/m, z0.d1565; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s1566; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h1567; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z01568; CHECK-NEXT: ret1569 %res = sitofp <2 x i64> %op1 to <2 x half>1570 ret <2 x half> %res1571}1572 1573define <4 x half> @scvtf_v4i64_v4f16(ptr %a) vscale_range(2,0) #0 {1574; CHECK-LABEL: scvtf_v4i64_v4f16:1575; CHECK: // %bb.0:1576; CHECK-NEXT: ptrue p0.d, vl41577; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1578; CHECK-NEXT: scvtf z0.h, p0/m, z0.d1579; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s1580; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h1581; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z01582; CHECK-NEXT: ret1583 %op1 = load <4 x i64>, ptr %a1584 %res = sitofp <4 x i64> %op1 to <4 x half>1585 ret <4 x half> %res1586}1587 1588define <8 x half> @scvtf_v8i64_v8f16(ptr %a) #0 {1589; VBITS_GE_256-LABEL: scvtf_v8i64_v8f16:1590; VBITS_GE_256: // %bb.0:1591; VBITS_GE_256-NEXT: ptrue p0.d, vl41592; VBITS_GE_256-NEXT: mov x8, #4 // =0x41593; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]1594; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]1595; VBITS_GE_256-NEXT: scvtf z0.h, p0/m, z0.d1596; VBITS_GE_256-NEXT: scvtf z1.h, p0/m, z1.d1597; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s1598; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s1599; VBITS_GE_256-NEXT: uzp1 z2.h, z0.h, z0.h1600; VBITS_GE_256-NEXT: uzp1 z0.h, z1.h, z1.h1601; VBITS_GE_256-NEXT: mov v0.d[1], v2.d[0]1602; VBITS_GE_256-NEXT: // kill: def $q0 killed $q0 killed $z01603; VBITS_GE_256-NEXT: ret1604;1605; VBITS_GE_512-LABEL: scvtf_v8i64_v8f16:1606; VBITS_GE_512: // %bb.0:1607; VBITS_GE_512-NEXT: ptrue p0.d, vl81608; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]1609; VBITS_GE_512-NEXT: scvtf z0.h, p0/m, z0.d1610; VBITS_GE_512-NEXT: uzp1 z0.s, z0.s, z0.s1611; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h1612; VBITS_GE_512-NEXT: // kill: def $q0 killed $q0 killed $z01613; VBITS_GE_512-NEXT: ret1614 %op1 = load <8 x i64>, ptr %a1615 %res = sitofp <8 x i64> %op1 to <8 x half>1616 ret <8 x half> %res1617}1618 1619define void @scvtf_v16i64_v16f16(ptr %a, ptr %b) vscale_range(8,0) #0 {1620; CHECK-LABEL: scvtf_v16i64_v16f16:1621; CHECK: // %bb.0:1622; CHECK-NEXT: ptrue p0.d, vl161623; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1624; CHECK-NEXT: scvtf z0.h, p0/m, z0.d1625; CHECK-NEXT: ptrue p0.s, vl161626; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s1627; CHECK-NEXT: st1h { z0.s }, p0, [x1]1628; CHECK-NEXT: ret1629 %op1 = load <16 x i64>, ptr %a1630 %res = sitofp <16 x i64> %op1 to <16 x half>1631 store <16 x half> %res, ptr %b1632 ret void1633}1634 1635define void @scvtf_v32i64_v32f16(ptr %a, ptr %b) vscale_range(16,0) #0 {1636; CHECK-LABEL: scvtf_v32i64_v32f16:1637; CHECK: // %bb.0:1638; CHECK-NEXT: ptrue p0.d, vl321639; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1640; CHECK-NEXT: scvtf z0.h, p0/m, z0.d1641; CHECK-NEXT: ptrue p0.s, vl321642; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s1643; CHECK-NEXT: st1h { z0.s }, p0, [x1]1644; CHECK-NEXT: ret1645 %op1 = load <32 x i64>, ptr %a1646 %res = sitofp <32 x i64> %op1 to <32 x half>1647 store <32 x half> %res, ptr %b1648 ret void1649}1650 1651;1652; SCVTF D -> S1653;1654 1655; Don't use SVE for 64-bit vectors.1656define <1 x float> @scvtf_v1i64_v1f32(<1 x i64> %op1) vscale_range(2,0) #0 {1657; CHECK-LABEL: scvtf_v1i64_v1f32:1658; CHECK: // %bb.0:1659; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01660; CHECK-NEXT: fmov x8, d01661; CHECK-NEXT: movi d1, #00000000000000001662; CHECK-NEXT: scvtf s0, x81663; CHECK-NEXT: mov v1.s[0], v0.s[0]1664; CHECK-NEXT: fmov d0, d11665; CHECK-NEXT: ret1666 %res = sitofp <1 x i64> %op1 to <1 x float>1667 ret <1 x float> %res1668}1669 1670; Don't use SVE for 128-bit vectors.1671define <2 x float> @scvtf_v2i64_v2f32(<2 x i64> %op1) vscale_range(2,0) #0 {1672; CHECK-LABEL: scvtf_v2i64_v2f32:1673; CHECK: // %bb.0:1674; CHECK-NEXT: mov x8, v0.d[1]1675; CHECK-NEXT: fmov x9, d01676; CHECK-NEXT: scvtf s0, x91677; CHECK-NEXT: scvtf s1, x81678; CHECK-NEXT: mov v0.s[1], v1.s[0]1679; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q01680; CHECK-NEXT: ret1681 %res = sitofp <2 x i64> %op1 to <2 x float>1682 ret <2 x float> %res1683}1684 1685define <4 x float> @scvtf_v4i64_v4f32(ptr %a) vscale_range(2,0) #0 {1686; CHECK-LABEL: scvtf_v4i64_v4f32:1687; CHECK: // %bb.0:1688; CHECK-NEXT: ptrue p0.d, vl41689; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1690; CHECK-NEXT: scvtf z0.s, p0/m, z0.d1691; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s1692; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z01693; CHECK-NEXT: ret1694 %op1 = load <4 x i64>, ptr %a1695 %res = sitofp <4 x i64> %op1 to <4 x float>1696 ret <4 x float> %res1697}1698 1699define void @scvtf_v8i64_v8f32(ptr %a, ptr %b) #0 {1700; VBITS_GE_256-LABEL: scvtf_v8i64_v8f32:1701; VBITS_GE_256: // %bb.0:1702; VBITS_GE_256-NEXT: ptrue p0.d, vl41703; VBITS_GE_256-NEXT: mov x8, #4 // =0x41704; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]1705; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]1706; VBITS_GE_256-NEXT: scvtf z0.s, p0/m, z0.d1707; VBITS_GE_256-NEXT: scvtf z1.s, p0/m, z1.d1708; VBITS_GE_256-NEXT: ptrue p0.s, vl41709; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s1710; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s1711; VBITS_GE_256-NEXT: splice z1.s, p0, z1.s, z0.s1712; VBITS_GE_256-NEXT: ptrue p0.s, vl81713; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1]1714; VBITS_GE_256-NEXT: ret1715;1716; VBITS_GE_512-LABEL: scvtf_v8i64_v8f32:1717; VBITS_GE_512: // %bb.0:1718; VBITS_GE_512-NEXT: ptrue p0.d, vl81719; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]1720; VBITS_GE_512-NEXT: scvtf z0.s, p0/m, z0.d1721; VBITS_GE_512-NEXT: ptrue p0.s, vl81722; VBITS_GE_512-NEXT: uzp1 z0.s, z0.s, z0.s1723; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]1724; VBITS_GE_512-NEXT: ret1725 %op1 = load <8 x i64>, ptr %a1726 %res = sitofp <8 x i64> %op1 to <8 x float>1727 store <8 x float> %res, ptr %b1728 ret void1729}1730 1731define void @scvtf_v16i64_v16f32(ptr %a, ptr %b) vscale_range(8,0) #0 {1732; CHECK-LABEL: scvtf_v16i64_v16f32:1733; CHECK: // %bb.0:1734; CHECK-NEXT: ptrue p0.d, vl161735; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1736; CHECK-NEXT: scvtf z0.s, p0/m, z0.d1737; CHECK-NEXT: ptrue p0.s, vl161738; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s1739; CHECK-NEXT: st1w { z0.s }, p0, [x1]1740; CHECK-NEXT: ret1741 %op1 = load <16 x i64>, ptr %a1742 %res = sitofp <16 x i64> %op1 to <16 x float>1743 store <16 x float> %res, ptr %b1744 ret void1745}1746 1747define void @scvtf_v32i64_v32f32(ptr %a, ptr %b) vscale_range(16,0) #0 {1748; CHECK-LABEL: scvtf_v32i64_v32f32:1749; CHECK: // %bb.0:1750; CHECK-NEXT: ptrue p0.d, vl321751; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1752; CHECK-NEXT: scvtf z0.s, p0/m, z0.d1753; CHECK-NEXT: ptrue p0.s, vl321754; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s1755; CHECK-NEXT: st1w { z0.s }, p0, [x1]1756; CHECK-NEXT: ret1757 %op1 = load <32 x i64>, ptr %a1758 %res = sitofp <32 x i64> %op1 to <32 x float>1759 store <32 x float> %res, ptr %b1760 ret void1761}1762 1763;1764; SCVTF D -> D1765;1766 1767; Don't use SVE for 64-bit vectors.1768define <1 x double> @scvtf_v1i64_v1f64(<1 x i64> %op1) vscale_range(2,0) #0 {1769; CHECK-LABEL: scvtf_v1i64_v1f64:1770; CHECK: // %bb.0:1771; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01772; CHECK-NEXT: scvtf d0, d01773; CHECK-NEXT: ret1774 %res = sitofp <1 x i64> %op1 to <1 x double>1775 ret <1 x double> %res1776}1777 1778; Don't use SVE for 128-bit vectors.1779define <2 x double> @scvtf_v2i64_v2f64(<2 x i64> %op1) vscale_range(2,0) #0 {1780; CHECK-LABEL: scvtf_v2i64_v2f64:1781; CHECK: // %bb.0:1782; CHECK-NEXT: scvtf v0.2d, v0.2d1783; CHECK-NEXT: ret1784 %res = sitofp <2 x i64> %op1 to <2 x double>1785 ret <2 x double> %res1786}1787 1788define void @scvtf_v4i64_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {1789; CHECK-LABEL: scvtf_v4i64_v4f64:1790; CHECK: // %bb.0:1791; CHECK-NEXT: ptrue p0.d, vl41792; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1793; CHECK-NEXT: scvtf z0.d, p0/m, z0.d1794; CHECK-NEXT: st1d { z0.d }, p0, [x1]1795; CHECK-NEXT: ret1796 %op1 = load <4 x i64>, ptr %a1797 %res = sitofp <4 x i64> %op1 to <4 x double>1798 store <4 x double> %res, ptr %b1799 ret void1800}1801 1802define void @scvtf_v8i64_v8f64(ptr %a, ptr %b) #0 {1803; VBITS_GE_256-LABEL: scvtf_v8i64_v8f64:1804; VBITS_GE_256: // %bb.0:1805; VBITS_GE_256-NEXT: ptrue p0.d, vl41806; VBITS_GE_256-NEXT: mov x8, #4 // =0x41807; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]1808; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]1809; VBITS_GE_256-NEXT: scvtf z0.d, p0/m, z0.d1810; VBITS_GE_256-NEXT: scvtf z1.d, p0/m, z1.d1811; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]1812; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1]1813; VBITS_GE_256-NEXT: ret1814;1815; VBITS_GE_512-LABEL: scvtf_v8i64_v8f64:1816; VBITS_GE_512: // %bb.0:1817; VBITS_GE_512-NEXT: ptrue p0.d, vl81818; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]1819; VBITS_GE_512-NEXT: scvtf z0.d, p0/m, z0.d1820; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1]1821; VBITS_GE_512-NEXT: ret1822 %op1 = load <8 x i64>, ptr %a1823 %res = sitofp <8 x i64> %op1 to <8 x double>1824 store <8 x double> %res, ptr %b1825 ret void1826}1827 1828define void @scvtf_v16i64_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {1829; CHECK-LABEL: scvtf_v16i64_v16f64:1830; CHECK: // %bb.0:1831; CHECK-NEXT: ptrue p0.d, vl161832; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1833; CHECK-NEXT: scvtf z0.d, p0/m, z0.d1834; CHECK-NEXT: st1d { z0.d }, p0, [x1]1835; CHECK-NEXT: ret1836 %op1 = load <16 x i64>, ptr %a1837 %res = sitofp <16 x i64> %op1 to <16 x double>1838 store <16 x double> %res, ptr %b1839 ret void1840}1841 1842define void @scvtf_v32i64_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {1843; CHECK-LABEL: scvtf_v32i64_v32f64:1844; CHECK: // %bb.0:1845; CHECK-NEXT: ptrue p0.d, vl321846; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1847; CHECK-NEXT: scvtf z0.d, p0/m, z0.d1848; CHECK-NEXT: st1d { z0.d }, p0, [x1]1849; CHECK-NEXT: ret1850 %op1 = load <32 x i64>, ptr %a1851 %res = sitofp <32 x i64> %op1 to <32 x double>1852 store <32 x double> %res, ptr %b1853 ret void1854}1855 1856attributes #0 = { "target-features"="+sve" }1857