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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8; Don't use SVE for 64-bit vectors.9define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) vscale_range(2,0) #0 {10; CHECK-LABEL: select_v8i8:11; CHECK: // %bb.0:12; CHECK-NEXT: shl v2.8b, v2.8b, #713; CHECK-NEXT: cmlt v2.8b, v2.8b, #014; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b15; CHECK-NEXT: ret16 %sel = select <8 x i1> %mask, <8 x i8> %op1, <8 x i8> %op217 ret <8 x i8> %sel18}19 20; Don't use SVE for 128-bit vectors.21define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) vscale_range(2,0) #0 {22; CHECK-LABEL: select_v16i8:23; CHECK: // %bb.0:24; CHECK-NEXT: shl v2.16b, v2.16b, #725; CHECK-NEXT: cmlt v2.16b, v2.16b, #026; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b27; CHECK-NEXT: ret28 %sel = select <16 x i1> %mask, <16 x i8> %op1, <16 x i8> %op229 ret <16 x i8> %sel30}31 32define void @select_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {33; CHECK-LABEL: select_v32i8:34; CHECK: // %bb.0:35; CHECK-NEXT: ptrue p0.b, vl3236; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]37; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]38; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, z1.b39; CHECK-NEXT: st1b { z1.b }, p0, [x0]40; CHECK-NEXT: ret41 %op1 = load <32 x i8>, ptr %a42 %op2 = load <32 x i8>, ptr %b43 %mask = icmp eq <32 x i8> %op1, %op244 %sel = select <32 x i1> %mask, <32 x i8> %op1, <32 x i8> %op245 store <32 x i8> %sel, ptr %a46 ret void47}48 49define void @select_v64i8(ptr %a, ptr %b) #0 {50; VBITS_GE_256-LABEL: select_v64i8:51; VBITS_GE_256: // %bb.0:52; VBITS_GE_256-NEXT: ptrue p0.b, vl3253; VBITS_GE_256-NEXT: mov w8, #32 // =0x2054; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]55; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]56; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]57; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]58; VBITS_GE_256-NEXT: cmpne p1.b, p0/z, z0.b, z1.b59; VBITS_GE_256-NEXT: cmpne p0.b, p0/z, z2.b, z3.b60; VBITS_GE_256-NEXT: st1b { z1.b }, p1, [x0, x8]61; VBITS_GE_256-NEXT: st1b { z3.b }, p0, [x0]62; VBITS_GE_256-NEXT: ret63;64; VBITS_GE_512-LABEL: select_v64i8:65; VBITS_GE_512: // %bb.0:66; VBITS_GE_512-NEXT: ptrue p0.b, vl6467; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]68; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]69; VBITS_GE_512-NEXT: cmpne p0.b, p0/z, z0.b, z1.b70; VBITS_GE_512-NEXT: st1b { z1.b }, p0, [x0]71; VBITS_GE_512-NEXT: ret72 %op1 = load <64 x i8>, ptr %a73 %op2 = load <64 x i8>, ptr %b74 %mask = icmp eq <64 x i8> %op1, %op275 %sel = select <64 x i1> %mask, <64 x i8> %op1, <64 x i8> %op276 store <64 x i8> %sel, ptr %a77 ret void78}79 80define void @select_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {81; CHECK-LABEL: select_v128i8:82; CHECK: // %bb.0:83; CHECK-NEXT: ptrue p0.b, vl12884; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]85; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]86; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, z1.b87; CHECK-NEXT: st1b { z1.b }, p0, [x0]88; CHECK-NEXT: ret89 %op1 = load <128 x i8>, ptr %a90 %op2 = load <128 x i8>, ptr %b91 %mask = icmp eq <128 x i8> %op1, %op292 %sel = select <128 x i1> %mask, <128 x i8> %op1, <128 x i8> %op293 store <128 x i8> %sel, ptr %a94 ret void95}96 97define void @select_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {98; CHECK-LABEL: select_v256i8:99; CHECK: // %bb.0:100; CHECK-NEXT: ptrue p0.b, vl256101; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]102; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]103; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, z1.b104; CHECK-NEXT: st1b { z1.b }, p0, [x0]105; CHECK-NEXT: ret106 %op1 = load <256 x i8>, ptr %a107 %op2 = load <256 x i8>, ptr %b108 %mask = icmp eq <256 x i8> %op1, %op2109 %sel = select <256 x i1> %mask, <256 x i8> %op1, <256 x i8> %op2110 store <256 x i8> %sel, ptr %a111 ret void112}113 114; Don't use SVE for 64-bit vectors.115define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) vscale_range(2,0) #0 {116; CHECK-LABEL: select_v4i16:117; CHECK: // %bb.0:118; CHECK-NEXT: shl v2.4h, v2.4h, #15119; CHECK-NEXT: cmlt v2.4h, v2.4h, #0120; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b121; CHECK-NEXT: ret122 %sel = select <4 x i1> %mask, <4 x i16> %op1, <4 x i16> %op2123 ret <4 x i16> %sel124}125 126; Don't use SVE for 128-bit vectors.127define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) vscale_range(2,0) #0 {128; CHECK-LABEL: select_v8i16:129; CHECK: // %bb.0:130; CHECK-NEXT: ushll v2.8h, v2.8b, #0131; CHECK-NEXT: shl v2.8h, v2.8h, #15132; CHECK-NEXT: cmlt v2.8h, v2.8h, #0133; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b134; CHECK-NEXT: ret135 %sel = select <8 x i1> %mask, <8 x i16> %op1, <8 x i16> %op2136 ret <8 x i16> %sel137}138 139define void @select_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {140; CHECK-LABEL: select_v16i16:141; CHECK: // %bb.0:142; CHECK-NEXT: ptrue p0.h, vl16143; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]144; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]145; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z1.h146; CHECK-NEXT: st1h { z1.h }, p0, [x0]147; CHECK-NEXT: ret148 %op1 = load <16 x i16>, ptr %a149 %op2 = load <16 x i16>, ptr %b150 %mask = icmp eq <16 x i16> %op1, %op2151 %sel = select <16 x i1> %mask, <16 x i16> %op1, <16 x i16> %op2152 store <16 x i16> %sel, ptr %a153 ret void154}155 156define void @select_v32i16(ptr %a, ptr %b) #0 {157; VBITS_GE_256-LABEL: select_v32i16:158; VBITS_GE_256: // %bb.0:159; VBITS_GE_256-NEXT: ptrue p0.h, vl16160; VBITS_GE_256-NEXT: mov x8, #16 // =0x10161; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]162; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]163; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]164; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]165; VBITS_GE_256-NEXT: cmpne p1.h, p0/z, z0.h, z1.h166; VBITS_GE_256-NEXT: cmpne p0.h, p0/z, z2.h, z3.h167; VBITS_GE_256-NEXT: st1h { z1.h }, p1, [x0, x8, lsl #1]168; VBITS_GE_256-NEXT: st1h { z3.h }, p0, [x0]169; VBITS_GE_256-NEXT: ret170;171; VBITS_GE_512-LABEL: select_v32i16:172; VBITS_GE_512: // %bb.0:173; VBITS_GE_512-NEXT: ptrue p0.h, vl32174; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]175; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]176; VBITS_GE_512-NEXT: cmpne p0.h, p0/z, z0.h, z1.h177; VBITS_GE_512-NEXT: st1h { z1.h }, p0, [x0]178; VBITS_GE_512-NEXT: ret179 %op1 = load <32 x i16>, ptr %a180 %op2 = load <32 x i16>, ptr %b181 %mask = icmp eq <32 x i16> %op1, %op2182 %sel = select <32 x i1> %mask, <32 x i16> %op1, <32 x i16> %op2183 store <32 x i16> %sel, ptr %a184 ret void185}186 187define void @select_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {188; CHECK-LABEL: select_v64i16:189; CHECK: // %bb.0:190; CHECK-NEXT: ptrue p0.h, vl64191; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]192; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]193; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z1.h194; CHECK-NEXT: st1h { z1.h }, p0, [x0]195; CHECK-NEXT: ret196 %op1 = load <64 x i16>, ptr %a197 %op2 = load <64 x i16>, ptr %b198 %mask = icmp eq <64 x i16> %op1, %op2199 %sel = select <64 x i1> %mask, <64 x i16> %op1, <64 x i16> %op2200 store <64 x i16> %sel, ptr %a201 ret void202}203 204define void @select_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {205; CHECK-LABEL: select_v128i16:206; CHECK: // %bb.0:207; CHECK-NEXT: ptrue p0.h, vl128208; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]209; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]210; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z1.h211; CHECK-NEXT: st1h { z1.h }, p0, [x0]212; CHECK-NEXT: ret213 %op1 = load <128 x i16>, ptr %a214 %op2 = load <128 x i16>, ptr %b215 %mask = icmp eq <128 x i16> %op1, %op2216 %sel = select <128 x i1> %mask, <128 x i16> %op1, <128 x i16> %op2217 store <128 x i16> %sel, ptr %a218 ret void219}220 221; Don't use SVE for 64-bit vectors.222define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) vscale_range(2,0) #0 {223; CHECK-LABEL: select_v2i32:224; CHECK: // %bb.0:225; CHECK-NEXT: shl v2.2s, v2.2s, #31226; CHECK-NEXT: cmlt v2.2s, v2.2s, #0227; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b228; CHECK-NEXT: ret229 %sel = select <2 x i1> %mask, <2 x i32> %op1, <2 x i32> %op2230 ret <2 x i32> %sel231}232 233; Don't use SVE for 128-bit vectors.234define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) vscale_range(2,0) #0 {235; CHECK-LABEL: select_v4i32:236; CHECK: // %bb.0:237; CHECK-NEXT: ushll v2.4s, v2.4h, #0238; CHECK-NEXT: shl v2.4s, v2.4s, #31239; CHECK-NEXT: cmlt v2.4s, v2.4s, #0240; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b241; CHECK-NEXT: ret242 %sel = select <4 x i1> %mask, <4 x i32> %op1, <4 x i32> %op2243 ret <4 x i32> %sel244}245 246define void @select_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {247; CHECK-LABEL: select_v8i32:248; CHECK: // %bb.0:249; CHECK-NEXT: ptrue p0.s, vl8250; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]251; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]252; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z1.s253; CHECK-NEXT: st1w { z1.s }, p0, [x0]254; CHECK-NEXT: ret255 %op1 = load <8 x i32>, ptr %a256 %op2 = load <8 x i32>, ptr %b257 %mask = icmp eq <8 x i32> %op1, %op2258 %sel = select <8 x i1> %mask, <8 x i32> %op1, <8 x i32> %op2259 store <8 x i32> %sel, ptr %a260 ret void261}262 263define void @select_v16i32(ptr %a, ptr %b) #0 {264; VBITS_GE_256-LABEL: select_v16i32:265; VBITS_GE_256: // %bb.0:266; VBITS_GE_256-NEXT: ptrue p0.s, vl8267; VBITS_GE_256-NEXT: mov x8, #8 // =0x8268; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]269; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]270; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]271; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]272; VBITS_GE_256-NEXT: cmpne p1.s, p0/z, z0.s, z1.s273; VBITS_GE_256-NEXT: cmpne p0.s, p0/z, z2.s, z3.s274; VBITS_GE_256-NEXT: st1w { z1.s }, p1, [x0, x8, lsl #2]275; VBITS_GE_256-NEXT: st1w { z3.s }, p0, [x0]276; VBITS_GE_256-NEXT: ret277;278; VBITS_GE_512-LABEL: select_v16i32:279; VBITS_GE_512: // %bb.0:280; VBITS_GE_512-NEXT: ptrue p0.s, vl16281; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]282; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]283; VBITS_GE_512-NEXT: cmpne p0.s, p0/z, z0.s, z1.s284; VBITS_GE_512-NEXT: st1w { z1.s }, p0, [x0]285; VBITS_GE_512-NEXT: ret286 %op1 = load <16 x i32>, ptr %a287 %op2 = load <16 x i32>, ptr %b288 %mask = icmp eq <16 x i32> %op1, %op2289 %sel = select <16 x i1> %mask, <16 x i32> %op1, <16 x i32> %op2290 store <16 x i32> %sel, ptr %a291 ret void292}293 294define void @select_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {295; CHECK-LABEL: select_v32i32:296; CHECK: // %bb.0:297; CHECK-NEXT: ptrue p0.s, vl32298; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]299; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]300; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z1.s301; CHECK-NEXT: st1w { z1.s }, p0, [x0]302; CHECK-NEXT: ret303 %op1 = load <32 x i32>, ptr %a304 %op2 = load <32 x i32>, ptr %b305 %mask = icmp eq <32 x i32> %op1, %op2306 %sel = select <32 x i1> %mask, <32 x i32> %op1, <32 x i32> %op2307 store <32 x i32> %sel, ptr %a308 ret void309}310 311define void @select_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {312; CHECK-LABEL: select_v64i32:313; CHECK: // %bb.0:314; CHECK-NEXT: ptrue p0.s, vl64315; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]316; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]317; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z1.s318; CHECK-NEXT: st1w { z1.s }, p0, [x0]319; CHECK-NEXT: ret320 %op1 = load <64 x i32>, ptr %a321 %op2 = load <64 x i32>, ptr %b322 %mask = icmp eq <64 x i32> %op1, %op2323 %sel = select <64 x i1> %mask, <64 x i32> %op1, <64 x i32> %op2324 store <64 x i32> %sel, ptr %a325 ret void326}327 328; Don't use SVE for 64-bit vectors.329define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) vscale_range(2,0) #0 {330; CHECK-LABEL: select_v1i64:331; CHECK: // %bb.0:332; CHECK-NEXT: tst w0, #0x1333; CHECK-NEXT: csetm x8, ne334; CHECK-NEXT: fmov d2, x8335; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b336; CHECK-NEXT: ret337 %sel = select <1 x i1> %mask, <1 x i64> %op1, <1 x i64> %op2338 ret <1 x i64> %sel339}340 341; Don't use SVE for 128-bit vectors.342define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) vscale_range(2,0) #0 {343; CHECK-LABEL: select_v2i64:344; CHECK: // %bb.0:345; CHECK-NEXT: ushll v2.2d, v2.2s, #0346; CHECK-NEXT: shl v2.2d, v2.2d, #63347; CHECK-NEXT: cmlt v2.2d, v2.2d, #0348; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b349; CHECK-NEXT: ret350 %sel = select <2 x i1> %mask, <2 x i64> %op1, <2 x i64> %op2351 ret <2 x i64> %sel352}353 354define void @select_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {355; CHECK-LABEL: select_v4i64:356; CHECK: // %bb.0:357; CHECK-NEXT: ptrue p0.d, vl4358; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]359; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]360; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, z1.d361; CHECK-NEXT: st1d { z1.d }, p0, [x0]362; CHECK-NEXT: ret363 %op1 = load <4 x i64>, ptr %a364 %op2 = load <4 x i64>, ptr %b365 %mask = icmp eq <4 x i64> %op1, %op2366 %sel = select <4 x i1> %mask, <4 x i64> %op1, <4 x i64> %op2367 store <4 x i64> %sel, ptr %a368 ret void369}370 371define void @select_v8i64(ptr %a, ptr %b) #0 {372; VBITS_GE_256-LABEL: select_v8i64:373; VBITS_GE_256: // %bb.0:374; VBITS_GE_256-NEXT: ptrue p0.d, vl4375; VBITS_GE_256-NEXT: mov x8, #4 // =0x4376; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]377; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]378; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]379; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]380; VBITS_GE_256-NEXT: cmpne p1.d, p0/z, z0.d, z1.d381; VBITS_GE_256-NEXT: cmpne p0.d, p0/z, z2.d, z3.d382; VBITS_GE_256-NEXT: st1d { z1.d }, p1, [x0, x8, lsl #3]383; VBITS_GE_256-NEXT: st1d { z3.d }, p0, [x0]384; VBITS_GE_256-NEXT: ret385;386; VBITS_GE_512-LABEL: select_v8i64:387; VBITS_GE_512: // %bb.0:388; VBITS_GE_512-NEXT: ptrue p0.d, vl8389; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]390; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]391; VBITS_GE_512-NEXT: cmpne p0.d, p0/z, z0.d, z1.d392; VBITS_GE_512-NEXT: st1d { z1.d }, p0, [x0]393; VBITS_GE_512-NEXT: ret394 %op1 = load <8 x i64>, ptr %a395 %op2 = load <8 x i64>, ptr %b396 %mask = icmp eq <8 x i64> %op1, %op2397 %sel = select <8 x i1> %mask, <8 x i64> %op1, <8 x i64> %op2398 store <8 x i64> %sel, ptr %a399 ret void400}401 402define void @select_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {403; CHECK-LABEL: select_v16i64:404; CHECK: // %bb.0:405; CHECK-NEXT: ptrue p0.d, vl16406; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]407; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]408; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, z1.d409; CHECK-NEXT: st1d { z1.d }, p0, [x0]410; CHECK-NEXT: ret411 %op1 = load <16 x i64>, ptr %a412 %op2 = load <16 x i64>, ptr %b413 %mask = icmp eq <16 x i64> %op1, %op2414 %sel = select <16 x i1> %mask, <16 x i64> %op1, <16 x i64> %op2415 store <16 x i64> %sel, ptr %a416 ret void417}418 419define void @select_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {420; CHECK-LABEL: select_v32i64:421; CHECK: // %bb.0:422; CHECK-NEXT: ptrue p0.d, vl32423; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]424; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]425; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, z1.d426; CHECK-NEXT: st1d { z1.d }, p0, [x0]427; CHECK-NEXT: ret428 %op1 = load <32 x i64>, ptr %a429 %op2 = load <32 x i64>, ptr %b430 %mask = icmp eq <32 x i64> %op1, %op2431 %sel = select <32 x i1> %mask, <32 x i64> %op1, <32 x i64> %op2432 store <32 x i64> %sel, ptr %a433 ret void434}435 436attributes #0 = { "target-features"="+sve" uwtable }437