53 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mattr=+sve -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s3target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"4target triple = "aarch64-unknown-linux-gnu"5 6define <4 x i32> @test(ptr %arg1, ptr %arg2) {7; CHECK-LABEL: test:8; CHECK: // %bb.0: // %entry9; CHECK-NEXT: ptrue p0.s, vl810; CHECK-NEXT: mov x8, #8 // =0x811; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]12; CHECK-NEXT: ld1w { z2.s }, p0/z, [x0]13; CHECK-NEXT: movprfx z0, z114; CHECK-NEXT: ext z0.b, z0.b, z1.b, #1615; CHECK-NEXT: add z1.s, z1.s, z1.s16; CHECK-NEXT: add z2.s, z2.s, z2.s17; CHECK-NEXT: dup v0.4s, v0.s[2]18; CHECK-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]19; CHECK-NEXT: st1w { z2.s }, p0, [x0]20; CHECK-NEXT: ret21entry:22 %0 = load <16 x i32>, ptr %arg1, align 25623 %1 = load <16 x i32>, ptr %arg2, align 25624 %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <4 x i32> <i32 14, i32 14, i32 14, i32 14>25 %2 = add <16 x i32> %0, %026 store <16 x i32> %2, ptr %arg1, align 25627 ret <4 x i32> %shvec28}29 30define <2 x i32> @test2(ptr %arg1, ptr %arg2) {31; CHECK-LABEL: test2:32; CHECK: // %bb.0: // %entry33; CHECK-NEXT: ptrue p0.s, vl834; CHECK-NEXT: mov x8, #8 // =0x835; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]36; CHECK-NEXT: ld1w { z2.s }, p0/z, [x0]37; CHECK-NEXT: movprfx z0, z138; CHECK-NEXT: ext z0.b, z0.b, z1.b, #2439; CHECK-NEXT: add z1.s, z1.s, z1.s40; CHECK-NEXT: add z2.s, z2.s, z2.s41; CHECK-NEXT: dup v0.2s, v0.s[0]42; CHECK-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]43; CHECK-NEXT: st1w { z2.s }, p0, [x0]44; CHECK-NEXT: ret45entry:46 %0 = load <16 x i32>, ptr %arg1, align 25647 %1 = load <16 x i32>, ptr %arg2, align 25648 %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <2 x i32> <i32 14, i32 14>49 %2 = add <16 x i32> %0, %050 store <16 x i32> %2, ptr %arg1, align 25651 ret <2 x i32> %shvec52}53