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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=128 < %s | not grep ptrue3; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2564; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125; RUN: llc -aarch64-sve-vector-bits-min=1024 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_10246; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_20487 8target triple = "aarch64-unknown-linux-gnu"9 10; Don't use SVE for 64-bit vectors.11define void @load_v2f32(ptr %a, ptr %b) #0 {12; CHECK-LABEL: load_v2f32:13; CHECK: // %bb.0:14; CHECK-NEXT: ldr d0, [x0]15; CHECK-NEXT: str d0, [x1]16; CHECK-NEXT: ret17 %load = load <2 x float>, ptr %a18 store <2 x float> %load, ptr %b19 ret void20}21 22; Don't use SVE for 128-bit vectors.23define void @load_v4f32(ptr %a, ptr %b) #0 {24; CHECK-LABEL: load_v4f32:25; CHECK: // %bb.0:26; CHECK-NEXT: ldr q0, [x0]27; CHECK-NEXT: str q0, [x1]28; CHECK-NEXT: ret29 %load = load <4 x float>, ptr %a30 store <4 x float> %load, ptr %b31 ret void32}33 34define void @load_v8f32(ptr %a, ptr %b) #0 {35; CHECK-LABEL: load_v8f32:36; CHECK: // %bb.0:37; CHECK-NEXT: ptrue p0.s, vl838; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]39; CHECK-NEXT: st1w { z0.s }, p0, [x1]40; CHECK-NEXT: ret41 %load = load <8 x float>, ptr %a42 store <8 x float> %load, ptr %b43 ret void44}45 46define void @load_v16f32(ptr %a, ptr %b) #0 {47; VBITS_GE_256-LABEL: load_v16f32:48; VBITS_GE_256: // %bb.0:49; VBITS_GE_256-NEXT: ptrue p0.s, vl850; VBITS_GE_256-NEXT: mov x8, #8 // =0x851; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]52; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]53; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]54; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1]55; VBITS_GE_256-NEXT: ret56;57; VBITS_GE_512-LABEL: load_v16f32:58; VBITS_GE_512: // %bb.0:59; VBITS_GE_512-NEXT: ptrue p0.s, vl1660; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]61; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]62; VBITS_GE_512-NEXT: ret63;64; VBITS_GE_1024-LABEL: load_v16f32:65; VBITS_GE_1024: // %bb.0:66; VBITS_GE_1024-NEXT: ptrue p0.s, vl1667; VBITS_GE_1024-NEXT: ld1w { z0.s }, p0/z, [x0]68; VBITS_GE_1024-NEXT: st1w { z0.s }, p0, [x1]69; VBITS_GE_1024-NEXT: ret70;71; VBITS_GE_2048-LABEL: load_v16f32:72; VBITS_GE_2048: // %bb.0:73; VBITS_GE_2048-NEXT: ptrue p0.s, vl1674; VBITS_GE_2048-NEXT: ld1w { z0.s }, p0/z, [x0]75; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x1]76; VBITS_GE_2048-NEXT: ret77 %load = load <16 x float>, ptr %a78 store <16 x float> %load, ptr %b79 ret void80}81 82define void @load_v32f32(ptr %a, ptr %b) #0 {83; VBITS_GE_256-LABEL: load_v32f32:84; VBITS_GE_256: // %bb.0:85; VBITS_GE_256-NEXT: ptrue p0.s, vl886; VBITS_GE_256-NEXT: mov x8, #16 // =0x1087; VBITS_GE_256-NEXT: mov x9, #24 // =0x1888; VBITS_GE_256-NEXT: mov x10, #8 // =0x889; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]90; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0, x9, lsl #2]91; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0, x10, lsl #2]92; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x0]93; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]94; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1, x9, lsl #2]95; VBITS_GE_256-NEXT: st1w { z2.s }, p0, [x1, x10, lsl #2]96; VBITS_GE_256-NEXT: st1w { z3.s }, p0, [x1]97; VBITS_GE_256-NEXT: ret98;99; VBITS_GE_512-LABEL: load_v32f32:100; VBITS_GE_512: // %bb.0:101; VBITS_GE_512-NEXT: ptrue p0.s, vl16102; VBITS_GE_512-NEXT: mov x8, #16 // =0x10103; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]104; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x0]105; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]106; VBITS_GE_512-NEXT: st1w { z1.s }, p0, [x1]107; VBITS_GE_512-NEXT: ret108;109; VBITS_GE_1024-LABEL: load_v32f32:110; VBITS_GE_1024: // %bb.0:111; VBITS_GE_1024-NEXT: ptrue p0.s, vl32112; VBITS_GE_1024-NEXT: ld1w { z0.s }, p0/z, [x0]113; VBITS_GE_1024-NEXT: st1w { z0.s }, p0, [x1]114; VBITS_GE_1024-NEXT: ret115;116; VBITS_GE_2048-LABEL: load_v32f32:117; VBITS_GE_2048: // %bb.0:118; VBITS_GE_2048-NEXT: ptrue p0.s, vl32119; VBITS_GE_2048-NEXT: ld1w { z0.s }, p0/z, [x0]120; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x1]121; VBITS_GE_2048-NEXT: ret122 %load = load <32 x float>, ptr %a123 store <32 x float> %load, ptr %b124 ret void125}126 127define void @load_v64f32(ptr %a, ptr %b) #0 {128; VBITS_GE_256-LABEL: load_v64f32:129; VBITS_GE_256: // %bb.0:130; VBITS_GE_256-NEXT: ptrue p0.s, vl8131; VBITS_GE_256-NEXT: mov x8, #8 // =0x8132; VBITS_GE_256-NEXT: mov x9, #24 // =0x18133; VBITS_GE_256-NEXT: mov x10, #16 // =0x10134; VBITS_GE_256-NEXT: mov x11, #48 // =0x30135; VBITS_GE_256-NEXT: mov x12, #40 // =0x28136; VBITS_GE_256-NEXT: mov x13, #56 // =0x38137; VBITS_GE_256-NEXT: mov x14, #32 // =0x20138; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x11, lsl #2]139; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]140; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0, x13, lsl #2]141; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x0, x9, lsl #2]142; VBITS_GE_256-NEXT: ld1w { z4.s }, p0/z, [x0, x10, lsl #2]143; VBITS_GE_256-NEXT: ld1w { z5.s }, p0/z, [x0, x14, lsl #2]144; VBITS_GE_256-NEXT: ld1w { z6.s }, p0/z, [x0, x12, lsl #2]145; VBITS_GE_256-NEXT: ld1w { z7.s }, p0/z, [x0]146; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1, x11, lsl #2]147; VBITS_GE_256-NEXT: st1w { z2.s }, p0, [x1, x13, lsl #2]148; VBITS_GE_256-NEXT: st1w { z5.s }, p0, [x1, x14, lsl #2]149; VBITS_GE_256-NEXT: st1w { z6.s }, p0, [x1, x12, lsl #2]150; VBITS_GE_256-NEXT: st1w { z4.s }, p0, [x1, x10, lsl #2]151; VBITS_GE_256-NEXT: st1w { z3.s }, p0, [x1, x9, lsl #2]152; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1, x8, lsl #2]153; VBITS_GE_256-NEXT: st1w { z7.s }, p0, [x1]154; VBITS_GE_256-NEXT: ret155;156; VBITS_GE_512-LABEL: load_v64f32:157; VBITS_GE_512: // %bb.0:158; VBITS_GE_512-NEXT: ptrue p0.s, vl16159; VBITS_GE_512-NEXT: mov x8, #32 // =0x20160; VBITS_GE_512-NEXT: mov x9, #48 // =0x30161; VBITS_GE_512-NEXT: mov x10, #16 // =0x10162; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]163; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x0, x9, lsl #2]164; VBITS_GE_512-NEXT: ld1w { z2.s }, p0/z, [x0, x10, lsl #2]165; VBITS_GE_512-NEXT: ld1w { z3.s }, p0/z, [x0]166; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]167; VBITS_GE_512-NEXT: st1w { z1.s }, p0, [x1, x9, lsl #2]168; VBITS_GE_512-NEXT: st1w { z2.s }, p0, [x1, x10, lsl #2]169; VBITS_GE_512-NEXT: st1w { z3.s }, p0, [x1]170; VBITS_GE_512-NEXT: ret171;172; VBITS_GE_1024-LABEL: load_v64f32:173; VBITS_GE_1024: // %bb.0:174; VBITS_GE_1024-NEXT: ptrue p0.s, vl32175; VBITS_GE_1024-NEXT: mov x8, #32 // =0x20176; VBITS_GE_1024-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]177; VBITS_GE_1024-NEXT: ld1w { z1.s }, p0/z, [x0]178; VBITS_GE_1024-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]179; VBITS_GE_1024-NEXT: st1w { z1.s }, p0, [x1]180; VBITS_GE_1024-NEXT: ret181;182; VBITS_GE_2048-LABEL: load_v64f32:183; VBITS_GE_2048: // %bb.0:184; VBITS_GE_2048-NEXT: ptrue p0.s, vl64185; VBITS_GE_2048-NEXT: ld1w { z0.s }, p0/z, [x0]186; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x1]187; VBITS_GE_2048-NEXT: ret188 %load = load <64 x float>, ptr %a189 store <64 x float> %load, ptr %b190 ret void191}192 193attributes #0 = { "target-features"="+sve" }194