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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; ANDV10;11 12; No single instruction NEON ANDV support. Use SVE.13define i8 @andv_v8i8(<8 x i8> %a) vscale_range(2,0) #0 {14; CHECK-LABEL: andv_v8i8:15; CHECK: // %bb.0:16; CHECK-NEXT: ptrue p0.b, vl817; CHECK-NEXT: // kill: def $d0 killed $d0 def $z018; CHECK-NEXT: andv b0, p0, z0.b19; CHECK-NEXT: fmov w0, s020; CHECK-NEXT: ret21 %res = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %a)22 ret i8 %res23}24 25; No single instruction NEON ANDV support. Use SVE.26define i8 @andv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 {27; CHECK-LABEL: andv_v16i8:28; CHECK: // %bb.0:29; CHECK-NEXT: ptrue p0.b, vl1630; CHECK-NEXT: // kill: def $q0 killed $q0 def $z031; CHECK-NEXT: andv b0, p0, z0.b32; CHECK-NEXT: fmov w0, s033; CHECK-NEXT: ret34 %res = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %a)35 ret i8 %res36}37 38define i8 @andv_v32i8(ptr %a) vscale_range(2,0) #0 {39; CHECK-LABEL: andv_v32i8:40; CHECK: // %bb.0:41; CHECK-NEXT: ptrue p0.b, vl3242; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]43; CHECK-NEXT: andv b0, p0, z0.b44; CHECK-NEXT: fmov w0, s045; CHECK-NEXT: ret46 %op = load <32 x i8>, ptr %a47 %res = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %op)48 ret i8 %res49}50 51define i8 @andv_v64i8(ptr %a) #0 {52; VBITS_GE_256-LABEL: andv_v64i8:53; VBITS_GE_256: // %bb.0:54; VBITS_GE_256-NEXT: ptrue p0.b, vl3255; VBITS_GE_256-NEXT: mov w8, #32 // =0x2056; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]57; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0]58; VBITS_GE_256-NEXT: and z0.d, z1.d, z0.d59; VBITS_GE_256-NEXT: andv b0, p0, z0.b60; VBITS_GE_256-NEXT: fmov w0, s061; VBITS_GE_256-NEXT: ret62;63; VBITS_GE_512-LABEL: andv_v64i8:64; VBITS_GE_512: // %bb.0:65; VBITS_GE_512-NEXT: ptrue p0.b, vl6466; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]67; VBITS_GE_512-NEXT: andv b0, p0, z0.b68; VBITS_GE_512-NEXT: fmov w0, s069; VBITS_GE_512-NEXT: ret70 %op = load <64 x i8>, ptr %a71 %res = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> %op)72 ret i8 %res73}74 75define i8 @andv_v128i8(ptr %a) vscale_range(8,0) #0 {76; CHECK-LABEL: andv_v128i8:77; CHECK: // %bb.0:78; CHECK-NEXT: ptrue p0.b, vl12879; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]80; CHECK-NEXT: andv b0, p0, z0.b81; CHECK-NEXT: fmov w0, s082; CHECK-NEXT: ret83 %op = load <128 x i8>, ptr %a84 %res = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> %op)85 ret i8 %res86}87 88define i8 @andv_v256i8(ptr %a) vscale_range(16,0) #0 {89; CHECK-LABEL: andv_v256i8:90; CHECK: // %bb.0:91; CHECK-NEXT: ptrue p0.b, vl25692; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]93; CHECK-NEXT: andv b0, p0, z0.b94; CHECK-NEXT: fmov w0, s095; CHECK-NEXT: ret96 %op = load <256 x i8>, ptr %a97 %res = call i8 @llvm.vector.reduce.and.v256i8(<256 x i8> %op)98 ret i8 %res99}100 101; No single instruction NEON ANDV support. Use SVE.102define i16 @andv_v4i16(<4 x i16> %a) vscale_range(2,0) #0 {103; CHECK-LABEL: andv_v4i16:104; CHECK: // %bb.0:105; CHECK-NEXT: ptrue p0.h, vl4106; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0107; CHECK-NEXT: andv h0, p0, z0.h108; CHECK-NEXT: fmov w0, s0109; CHECK-NEXT: ret110 %res = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %a)111 ret i16 %res112}113 114; No single instruction NEON ANDV support. Use SVE.115define i16 @andv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 {116; CHECK-LABEL: andv_v8i16:117; CHECK: // %bb.0:118; CHECK-NEXT: ptrue p0.h, vl8119; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0120; CHECK-NEXT: andv h0, p0, z0.h121; CHECK-NEXT: fmov w0, s0122; CHECK-NEXT: ret123 %res = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %a)124 ret i16 %res125}126 127define i16 @andv_v16i16(ptr %a) vscale_range(2,0) #0 {128; CHECK-LABEL: andv_v16i16:129; CHECK: // %bb.0:130; CHECK-NEXT: ptrue p0.h, vl16131; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]132; CHECK-NEXT: andv h0, p0, z0.h133; CHECK-NEXT: fmov w0, s0134; CHECK-NEXT: ret135 %op = load <16 x i16>, ptr %a136 %res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %op)137 ret i16 %res138}139 140define i16 @andv_v32i16(ptr %a) #0 {141; VBITS_GE_256-LABEL: andv_v32i16:142; VBITS_GE_256: // %bb.0:143; VBITS_GE_256-NEXT: ptrue p0.h, vl16144; VBITS_GE_256-NEXT: mov x8, #16 // =0x10145; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]146; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]147; VBITS_GE_256-NEXT: and z0.d, z1.d, z0.d148; VBITS_GE_256-NEXT: andv h0, p0, z0.h149; VBITS_GE_256-NEXT: fmov w0, s0150; VBITS_GE_256-NEXT: ret151;152; VBITS_GE_512-LABEL: andv_v32i16:153; VBITS_GE_512: // %bb.0:154; VBITS_GE_512-NEXT: ptrue p0.h, vl32155; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]156; VBITS_GE_512-NEXT: andv h0, p0, z0.h157; VBITS_GE_512-NEXT: fmov w0, s0158; VBITS_GE_512-NEXT: ret159 %op = load <32 x i16>, ptr %a160 %res = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> %op)161 ret i16 %res162}163 164define i16 @andv_v64i16(ptr %a) vscale_range(8,0) #0 {165; CHECK-LABEL: andv_v64i16:166; CHECK: // %bb.0:167; CHECK-NEXT: ptrue p0.h, vl64168; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]169; CHECK-NEXT: andv h0, p0, z0.h170; CHECK-NEXT: fmov w0, s0171; CHECK-NEXT: ret172 %op = load <64 x i16>, ptr %a173 %res = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> %op)174 ret i16 %res175}176 177define i16 @andv_v128i16(ptr %a) vscale_range(16,0) #0 {178; CHECK-LABEL: andv_v128i16:179; CHECK: // %bb.0:180; CHECK-NEXT: ptrue p0.h, vl128181; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]182; CHECK-NEXT: andv h0, p0, z0.h183; CHECK-NEXT: fmov w0, s0184; CHECK-NEXT: ret185 %op = load <128 x i16>, ptr %a186 %res = call i16 @llvm.vector.reduce.and.v128i16(<128 x i16> %op)187 ret i16 %res188}189 190; No single instruction NEON ANDV support. Use SVE.191define i32 @andv_v2i32(<2 x i32> %a) vscale_range(2,0) #0 {192; CHECK-LABEL: andv_v2i32:193; CHECK: // %bb.0:194; CHECK-NEXT: ptrue p0.s, vl2195; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0196; CHECK-NEXT: andv s0, p0, z0.s197; CHECK-NEXT: fmov w0, s0198; CHECK-NEXT: ret199 %res = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %a)200 ret i32 %res201}202 203; No single instruction NEON ANDV support. Use SVE.204define i32 @andv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 {205; CHECK-LABEL: andv_v4i32:206; CHECK: // %bb.0:207; CHECK-NEXT: ptrue p0.s, vl4208; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0209; CHECK-NEXT: andv s0, p0, z0.s210; CHECK-NEXT: fmov w0, s0211; CHECK-NEXT: ret212 %res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)213 ret i32 %res214}215 216define i32 @andv_v8i32(ptr %a) vscale_range(2,0) #0 {217; CHECK-LABEL: andv_v8i32:218; CHECK: // %bb.0:219; CHECK-NEXT: ptrue p0.s, vl8220; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]221; CHECK-NEXT: andv s0, p0, z0.s222; CHECK-NEXT: fmov w0, s0223; CHECK-NEXT: ret224 %op = load <8 x i32>, ptr %a225 %res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %op)226 ret i32 %res227}228 229define i32 @andv_v16i32(ptr %a) #0 {230; VBITS_GE_256-LABEL: andv_v16i32:231; VBITS_GE_256: // %bb.0:232; VBITS_GE_256-NEXT: ptrue p0.s, vl8233; VBITS_GE_256-NEXT: mov x8, #8 // =0x8234; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]235; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]236; VBITS_GE_256-NEXT: and z0.d, z1.d, z0.d237; VBITS_GE_256-NEXT: andv s0, p0, z0.s238; VBITS_GE_256-NEXT: fmov w0, s0239; VBITS_GE_256-NEXT: ret240;241; VBITS_GE_512-LABEL: andv_v16i32:242; VBITS_GE_512: // %bb.0:243; VBITS_GE_512-NEXT: ptrue p0.s, vl16244; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]245; VBITS_GE_512-NEXT: andv s0, p0, z0.s246; VBITS_GE_512-NEXT: fmov w0, s0247; VBITS_GE_512-NEXT: ret248 %op = load <16 x i32>, ptr %a249 %res = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %op)250 ret i32 %res251}252 253define i32 @andv_v32i32(ptr %a) vscale_range(8,0) #0 {254; CHECK-LABEL: andv_v32i32:255; CHECK: // %bb.0:256; CHECK-NEXT: ptrue p0.s, vl32257; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]258; CHECK-NEXT: andv s0, p0, z0.s259; CHECK-NEXT: fmov w0, s0260; CHECK-NEXT: ret261 %op = load <32 x i32>, ptr %a262 %res = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> %op)263 ret i32 %res264}265 266define i32 @andv_v64i32(ptr %a) vscale_range(16,0) #0 {267; CHECK-LABEL: andv_v64i32:268; CHECK: // %bb.0:269; CHECK-NEXT: ptrue p0.s, vl64270; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]271; CHECK-NEXT: andv s0, p0, z0.s272; CHECK-NEXT: fmov w0, s0273; CHECK-NEXT: ret274 %op = load <64 x i32>, ptr %a275 %res = call i32 @llvm.vector.reduce.and.v64i32(<64 x i32> %op)276 ret i32 %res277}278 279; Nothing to do for single element vectors.280define i64 @andv_v1i64(<1 x i64> %a) vscale_range(2,0) #0 {281; CHECK-LABEL: andv_v1i64:282; CHECK: // %bb.0:283; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0284; CHECK-NEXT: fmov x0, d0285; CHECK-NEXT: ret286 %res = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %a)287 ret i64 %res288}289 290; Use SVE for 128-bit vectors291define i64 @andv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 {292; CHECK-LABEL: andv_v2i64:293; CHECK: // %bb.0:294; CHECK-NEXT: ptrue p0.d, vl2295; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0296; CHECK-NEXT: andv d0, p0, z0.d297; CHECK-NEXT: fmov x0, d0298; CHECK-NEXT: ret299 %res = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %a)300 ret i64 %res301}302 303define i64 @andv_v4i64(ptr %a) vscale_range(2,0) #0 {304; CHECK-LABEL: andv_v4i64:305; CHECK: // %bb.0:306; CHECK-NEXT: ptrue p0.d, vl4307; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]308; CHECK-NEXT: andv d0, p0, z0.d309; CHECK-NEXT: fmov x0, d0310; CHECK-NEXT: ret311 %op = load <4 x i64>, ptr %a312 %res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %op)313 ret i64 %res314}315 316define i64 @andv_v8i64(ptr %a) #0 {317; VBITS_GE_256-LABEL: andv_v8i64:318; VBITS_GE_256: // %bb.0:319; VBITS_GE_256-NEXT: ptrue p0.d, vl4320; VBITS_GE_256-NEXT: mov x8, #4 // =0x4321; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]322; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]323; VBITS_GE_256-NEXT: and z0.d, z1.d, z0.d324; VBITS_GE_256-NEXT: andv d0, p0, z0.d325; VBITS_GE_256-NEXT: fmov x0, d0326; VBITS_GE_256-NEXT: ret327;328; VBITS_GE_512-LABEL: andv_v8i64:329; VBITS_GE_512: // %bb.0:330; VBITS_GE_512-NEXT: ptrue p0.d, vl8331; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]332; VBITS_GE_512-NEXT: andv d0, p0, z0.d333; VBITS_GE_512-NEXT: fmov x0, d0334; VBITS_GE_512-NEXT: ret335 %op = load <8 x i64>, ptr %a336 %res = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %op)337 ret i64 %res338}339 340define i64 @andv_v16i64(ptr %a) vscale_range(8,0) #0 {341; CHECK-LABEL: andv_v16i64:342; CHECK: // %bb.0:343; CHECK-NEXT: ptrue p0.d, vl16344; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]345; CHECK-NEXT: andv d0, p0, z0.d346; CHECK-NEXT: fmov x0, d0347; CHECK-NEXT: ret348 %op = load <16 x i64>, ptr %a349 %res = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> %op)350 ret i64 %res351}352 353define i64 @andv_v32i64(ptr %a) vscale_range(16,0) #0 {354; CHECK-LABEL: andv_v32i64:355; CHECK: // %bb.0:356; CHECK-NEXT: ptrue p0.d, vl32357; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]358; CHECK-NEXT: andv d0, p0, z0.d359; CHECK-NEXT: fmov x0, d0360; CHECK-NEXT: ret361 %op = load <32 x i64>, ptr %a362 %res = call i64 @llvm.vector.reduce.and.v32i64(<32 x i64> %op)363 ret i64 %res364}365 366;367; EORV368;369 370; No single instruction NEON EORV support. Use SVE.371define i8 @eorv_v8i8(<8 x i8> %a) vscale_range(2,0) #0 {372; CHECK-LABEL: eorv_v8i8:373; CHECK: // %bb.0:374; CHECK-NEXT: ptrue p0.b, vl8375; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0376; CHECK-NEXT: eorv b0, p0, z0.b377; CHECK-NEXT: fmov w0, s0378; CHECK-NEXT: ret379 %res = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %a)380 ret i8 %res381}382 383; No single instruction NEON EORV support. Use SVE.384define i8 @eorv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 {385; CHECK-LABEL: eorv_v16i8:386; CHECK: // %bb.0:387; CHECK-NEXT: ptrue p0.b, vl16388; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0389; CHECK-NEXT: eorv b0, p0, z0.b390; CHECK-NEXT: fmov w0, s0391; CHECK-NEXT: ret392 %res = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %a)393 ret i8 %res394}395 396define i8 @eorv_v32i8(ptr %a) vscale_range(2,0) #0 {397; CHECK-LABEL: eorv_v32i8:398; CHECK: // %bb.0:399; CHECK-NEXT: ptrue p0.b, vl32400; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]401; CHECK-NEXT: eorv b0, p0, z0.b402; CHECK-NEXT: fmov w0, s0403; CHECK-NEXT: ret404 %op = load <32 x i8>, ptr %a405 %res = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %op)406 ret i8 %res407}408 409define i8 @eorv_v64i8(ptr %a) #0 {410; VBITS_GE_256-LABEL: eorv_v64i8:411; VBITS_GE_256: // %bb.0:412; VBITS_GE_256-NEXT: ptrue p0.b, vl32413; VBITS_GE_256-NEXT: mov w8, #32 // =0x20414; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]415; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0]416; VBITS_GE_256-NEXT: eor z0.d, z1.d, z0.d417; VBITS_GE_256-NEXT: eorv b0, p0, z0.b418; VBITS_GE_256-NEXT: fmov w0, s0419; VBITS_GE_256-NEXT: ret420;421; VBITS_GE_512-LABEL: eorv_v64i8:422; VBITS_GE_512: // %bb.0:423; VBITS_GE_512-NEXT: ptrue p0.b, vl64424; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]425; VBITS_GE_512-NEXT: eorv b0, p0, z0.b426; VBITS_GE_512-NEXT: fmov w0, s0427; VBITS_GE_512-NEXT: ret428 %op = load <64 x i8>, ptr %a429 %res = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> %op)430 ret i8 %res431}432 433define i8 @eorv_v128i8(ptr %a) vscale_range(8,0) #0 {434; CHECK-LABEL: eorv_v128i8:435; CHECK: // %bb.0:436; CHECK-NEXT: ptrue p0.b, vl128437; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]438; CHECK-NEXT: eorv b0, p0, z0.b439; CHECK-NEXT: fmov w0, s0440; CHECK-NEXT: ret441 %op = load <128 x i8>, ptr %a442 %res = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %op)443 ret i8 %res444}445 446define i8 @eorv_v256i8(ptr %a) vscale_range(16,0) #0 {447; CHECK-LABEL: eorv_v256i8:448; CHECK: // %bb.0:449; CHECK-NEXT: ptrue p0.b, vl256450; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]451; CHECK-NEXT: eorv b0, p0, z0.b452; CHECK-NEXT: fmov w0, s0453; CHECK-NEXT: ret454 %op = load <256 x i8>, ptr %a455 %res = call i8 @llvm.vector.reduce.xor.v256i8(<256 x i8> %op)456 ret i8 %res457}458 459; No single instruction NEON EORV support. Use SVE.460define i16 @eorv_v4i16(<4 x i16> %a) vscale_range(2,0) #0 {461; CHECK-LABEL: eorv_v4i16:462; CHECK: // %bb.0:463; CHECK-NEXT: ptrue p0.h, vl4464; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0465; CHECK-NEXT: eorv h0, p0, z0.h466; CHECK-NEXT: fmov w0, s0467; CHECK-NEXT: ret468 %res = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %a)469 ret i16 %res470}471 472; No single instruction NEON EORV support. Use SVE.473define i16 @eorv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 {474; CHECK-LABEL: eorv_v8i16:475; CHECK: // %bb.0:476; CHECK-NEXT: ptrue p0.h, vl8477; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0478; CHECK-NEXT: eorv h0, p0, z0.h479; CHECK-NEXT: fmov w0, s0480; CHECK-NEXT: ret481 %res = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %a)482 ret i16 %res483}484 485define i16 @eorv_v16i16(ptr %a) vscale_range(2,0) #0 {486; CHECK-LABEL: eorv_v16i16:487; CHECK: // %bb.0:488; CHECK-NEXT: ptrue p0.h, vl16489; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]490; CHECK-NEXT: eorv h0, p0, z0.h491; CHECK-NEXT: fmov w0, s0492; CHECK-NEXT: ret493 %op = load <16 x i16>, ptr %a494 %res = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %op)495 ret i16 %res496}497 498define i16 @eorv_v32i16(ptr %a) #0 {499; VBITS_GE_256-LABEL: eorv_v32i16:500; VBITS_GE_256: // %bb.0:501; VBITS_GE_256-NEXT: ptrue p0.h, vl16502; VBITS_GE_256-NEXT: mov x8, #16 // =0x10503; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]504; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]505; VBITS_GE_256-NEXT: eor z0.d, z1.d, z0.d506; VBITS_GE_256-NEXT: eorv h0, p0, z0.h507; VBITS_GE_256-NEXT: fmov w0, s0508; VBITS_GE_256-NEXT: ret509;510; VBITS_GE_512-LABEL: eorv_v32i16:511; VBITS_GE_512: // %bb.0:512; VBITS_GE_512-NEXT: ptrue p0.h, vl32513; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]514; VBITS_GE_512-NEXT: eorv h0, p0, z0.h515; VBITS_GE_512-NEXT: fmov w0, s0516; VBITS_GE_512-NEXT: ret517 %op = load <32 x i16>, ptr %a518 %res = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> %op)519 ret i16 %res520}521 522define i16 @eorv_v64i16(ptr %a) vscale_range(8,0) #0 {523; CHECK-LABEL: eorv_v64i16:524; CHECK: // %bb.0:525; CHECK-NEXT: ptrue p0.h, vl64526; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]527; CHECK-NEXT: eorv h0, p0, z0.h528; CHECK-NEXT: fmov w0, s0529; CHECK-NEXT: ret530 %op = load <64 x i16>, ptr %a531 %res = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> %op)532 ret i16 %res533}534 535define i16 @eorv_v128i16(ptr %a) vscale_range(16,0) #0 {536; CHECK-LABEL: eorv_v128i16:537; CHECK: // %bb.0:538; CHECK-NEXT: ptrue p0.h, vl128539; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]540; CHECK-NEXT: eorv h0, p0, z0.h541; CHECK-NEXT: fmov w0, s0542; CHECK-NEXT: ret543 %op = load <128 x i16>, ptr %a544 %res = call i16 @llvm.vector.reduce.xor.v128i16(<128 x i16> %op)545 ret i16 %res546}547 548; No single instruction NEON EORV support. Use SVE.549define i32 @eorv_v2i32(<2 x i32> %a) vscale_range(2,0) #0 {550; CHECK-LABEL: eorv_v2i32:551; CHECK: // %bb.0:552; CHECK-NEXT: ptrue p0.s, vl2553; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0554; CHECK-NEXT: eorv s0, p0, z0.s555; CHECK-NEXT: fmov w0, s0556; CHECK-NEXT: ret557 %res = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %a)558 ret i32 %res559}560 561; No single instruction NEON EORV support. Use SVE.562define i32 @eorv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 {563; CHECK-LABEL: eorv_v4i32:564; CHECK: // %bb.0:565; CHECK-NEXT: ptrue p0.s, vl4566; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0567; CHECK-NEXT: eorv s0, p0, z0.s568; CHECK-NEXT: fmov w0, s0569; CHECK-NEXT: ret570 %res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)571 ret i32 %res572}573 574define i32 @eorv_v8i32(ptr %a) vscale_range(2,0) #0 {575; CHECK-LABEL: eorv_v8i32:576; CHECK: // %bb.0:577; CHECK-NEXT: ptrue p0.s, vl8578; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]579; CHECK-NEXT: eorv s0, p0, z0.s580; CHECK-NEXT: fmov w0, s0581; CHECK-NEXT: ret582 %op = load <8 x i32>, ptr %a583 %res = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %op)584 ret i32 %res585}586 587define i32 @eorv_v16i32(ptr %a) #0 {588; VBITS_GE_256-LABEL: eorv_v16i32:589; VBITS_GE_256: // %bb.0:590; VBITS_GE_256-NEXT: ptrue p0.s, vl8591; VBITS_GE_256-NEXT: mov x8, #8 // =0x8592; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]593; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]594; VBITS_GE_256-NEXT: eor z0.d, z1.d, z0.d595; VBITS_GE_256-NEXT: eorv s0, p0, z0.s596; VBITS_GE_256-NEXT: fmov w0, s0597; VBITS_GE_256-NEXT: ret598;599; VBITS_GE_512-LABEL: eorv_v16i32:600; VBITS_GE_512: // %bb.0:601; VBITS_GE_512-NEXT: ptrue p0.s, vl16602; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]603; VBITS_GE_512-NEXT: eorv s0, p0, z0.s604; VBITS_GE_512-NEXT: fmov w0, s0605; VBITS_GE_512-NEXT: ret606 %op = load <16 x i32>, ptr %a607 %res = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %op)608 ret i32 %res609}610 611define i32 @eorv_v32i32(ptr %a) vscale_range(8,0) #0 {612; CHECK-LABEL: eorv_v32i32:613; CHECK: // %bb.0:614; CHECK-NEXT: ptrue p0.s, vl32615; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]616; CHECK-NEXT: eorv s0, p0, z0.s617; CHECK-NEXT: fmov w0, s0618; CHECK-NEXT: ret619 %op = load <32 x i32>, ptr %a620 %res = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> %op)621 ret i32 %res622}623 624define i32 @eorv_v64i32(ptr %a) vscale_range(16,0) #0 {625; CHECK-LABEL: eorv_v64i32:626; CHECK: // %bb.0:627; CHECK-NEXT: ptrue p0.s, vl64628; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]629; CHECK-NEXT: eorv s0, p0, z0.s630; CHECK-NEXT: fmov w0, s0631; CHECK-NEXT: ret632 %op = load <64 x i32>, ptr %a633 %res = call i32 @llvm.vector.reduce.xor.v64i32(<64 x i32> %op)634 ret i32 %res635}636 637; Nothing to do for single element vectors.638define i64 @eorv_v1i64(<1 x i64> %a) vscale_range(2,0) #0 {639; CHECK-LABEL: eorv_v1i64:640; CHECK: // %bb.0:641; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0642; CHECK-NEXT: fmov x0, d0643; CHECK-NEXT: ret644 %res = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> %a)645 ret i64 %res646}647 648; Use SVE for 128-bit vectors649define i64 @eorv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 {650; CHECK-LABEL: eorv_v2i64:651; CHECK: // %bb.0:652; CHECK-NEXT: ptrue p0.d, vl2653; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0654; CHECK-NEXT: eorv d0, p0, z0.d655; CHECK-NEXT: fmov x0, d0656; CHECK-NEXT: ret657 %res = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %a)658 ret i64 %res659}660 661define i64 @eorv_v4i64(ptr %a) vscale_range(2,0) #0 {662; CHECK-LABEL: eorv_v4i64:663; CHECK: // %bb.0:664; CHECK-NEXT: ptrue p0.d, vl4665; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]666; CHECK-NEXT: eorv d0, p0, z0.d667; CHECK-NEXT: fmov x0, d0668; CHECK-NEXT: ret669 %op = load <4 x i64>, ptr %a670 %res = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %op)671 ret i64 %res672}673 674define i64 @eorv_v8i64(ptr %a) #0 {675; VBITS_GE_256-LABEL: eorv_v8i64:676; VBITS_GE_256: // %bb.0:677; VBITS_GE_256-NEXT: ptrue p0.d, vl4678; VBITS_GE_256-NEXT: mov x8, #4 // =0x4679; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]680; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]681; VBITS_GE_256-NEXT: eor z0.d, z1.d, z0.d682; VBITS_GE_256-NEXT: eorv d0, p0, z0.d683; VBITS_GE_256-NEXT: fmov x0, d0684; VBITS_GE_256-NEXT: ret685;686; VBITS_GE_512-LABEL: eorv_v8i64:687; VBITS_GE_512: // %bb.0:688; VBITS_GE_512-NEXT: ptrue p0.d, vl8689; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]690; VBITS_GE_512-NEXT: eorv d0, p0, z0.d691; VBITS_GE_512-NEXT: fmov x0, d0692; VBITS_GE_512-NEXT: ret693 %op = load <8 x i64>, ptr %a694 %res = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %op)695 ret i64 %res696}697 698define i64 @eorv_v16i64(ptr %a) vscale_range(8,0) #0 {699; CHECK-LABEL: eorv_v16i64:700; CHECK: // %bb.0:701; CHECK-NEXT: ptrue p0.d, vl16702; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]703; CHECK-NEXT: eorv d0, p0, z0.d704; CHECK-NEXT: fmov x0, d0705; CHECK-NEXT: ret706 %op = load <16 x i64>, ptr %a707 %res = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> %op)708 ret i64 %res709}710 711define i64 @eorv_v32i64(ptr %a) vscale_range(16,0) #0 {712; CHECK-LABEL: eorv_v32i64:713; CHECK: // %bb.0:714; CHECK-NEXT: ptrue p0.d, vl32715; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]716; CHECK-NEXT: eorv d0, p0, z0.d717; CHECK-NEXT: fmov x0, d0718; CHECK-NEXT: ret719 %op = load <32 x i64>, ptr %a720 %res = call i64 @llvm.vector.reduce.xor.v32i64(<32 x i64> %op)721 ret i64 %res722}723 724;725; ORV726;727 728; No single instruction NEON ORV support. Use SVE.729define i8 @orv_v8i8(<8 x i8> %a) vscale_range(2,0) #0 {730; CHECK-LABEL: orv_v8i8:731; CHECK: // %bb.0:732; CHECK-NEXT: ptrue p0.b, vl8733; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0734; CHECK-NEXT: orv b0, p0, z0.b735; CHECK-NEXT: fmov w0, s0736; CHECK-NEXT: ret737 %res = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %a)738 ret i8 %res739}740 741; No single instruction NEON ORV support. Use SVE.742define i8 @orv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 {743; CHECK-LABEL: orv_v16i8:744; CHECK: // %bb.0:745; CHECK-NEXT: ptrue p0.b, vl16746; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0747; CHECK-NEXT: orv b0, p0, z0.b748; CHECK-NEXT: fmov w0, s0749; CHECK-NEXT: ret750 %res = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %a)751 ret i8 %res752}753 754define i8 @orv_v32i8(ptr %a) vscale_range(2,0) #0 {755; CHECK-LABEL: orv_v32i8:756; CHECK: // %bb.0:757; CHECK-NEXT: ptrue p0.b, vl32758; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]759; CHECK-NEXT: orv b0, p0, z0.b760; CHECK-NEXT: fmov w0, s0761; CHECK-NEXT: ret762 %op = load <32 x i8>, ptr %a763 %res = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %op)764 ret i8 %res765}766 767define i8 @orv_v64i8(ptr %a) #0 {768; VBITS_GE_256-LABEL: orv_v64i8:769; VBITS_GE_256: // %bb.0:770; VBITS_GE_256-NEXT: ptrue p0.b, vl32771; VBITS_GE_256-NEXT: mov w8, #32 // =0x20772; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]773; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0]774; VBITS_GE_256-NEXT: orr z0.d, z1.d, z0.d775; VBITS_GE_256-NEXT: orv b0, p0, z0.b776; VBITS_GE_256-NEXT: fmov w0, s0777; VBITS_GE_256-NEXT: ret778;779; VBITS_GE_512-LABEL: orv_v64i8:780; VBITS_GE_512: // %bb.0:781; VBITS_GE_512-NEXT: ptrue p0.b, vl64782; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]783; VBITS_GE_512-NEXT: orv b0, p0, z0.b784; VBITS_GE_512-NEXT: fmov w0, s0785; VBITS_GE_512-NEXT: ret786 %op = load <64 x i8>, ptr %a787 %res = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> %op)788 ret i8 %res789}790 791define i8 @orv_v128i8(ptr %a) vscale_range(8,0) #0 {792; CHECK-LABEL: orv_v128i8:793; CHECK: // %bb.0:794; CHECK-NEXT: ptrue p0.b, vl128795; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]796; CHECK-NEXT: orv b0, p0, z0.b797; CHECK-NEXT: fmov w0, s0798; CHECK-NEXT: ret799 %op = load <128 x i8>, ptr %a800 %res = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> %op)801 ret i8 %res802}803 804define i8 @orv_v256i8(ptr %a) vscale_range(16,0) #0 {805; CHECK-LABEL: orv_v256i8:806; CHECK: // %bb.0:807; CHECK-NEXT: ptrue p0.b, vl256808; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]809; CHECK-NEXT: orv b0, p0, z0.b810; CHECK-NEXT: fmov w0, s0811; CHECK-NEXT: ret812 %op = load <256 x i8>, ptr %a813 %res = call i8 @llvm.vector.reduce.or.v256i8(<256 x i8> %op)814 ret i8 %res815}816 817; No single instruction NEON ORV support. Use SVE.818define i16 @orv_v4i16(<4 x i16> %a) vscale_range(2,0) #0 {819; CHECK-LABEL: orv_v4i16:820; CHECK: // %bb.0:821; CHECK-NEXT: ptrue p0.h, vl4822; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0823; CHECK-NEXT: orv h0, p0, z0.h824; CHECK-NEXT: fmov w0, s0825; CHECK-NEXT: ret826 %res = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %a)827 ret i16 %res828}829 830; No single instruction NEON ORV support. Use SVE.831define i16 @orv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 {832; CHECK-LABEL: orv_v8i16:833; CHECK: // %bb.0:834; CHECK-NEXT: ptrue p0.h, vl8835; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0836; CHECK-NEXT: orv h0, p0, z0.h837; CHECK-NEXT: fmov w0, s0838; CHECK-NEXT: ret839 %res = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %a)840 ret i16 %res841}842 843define i16 @orv_v16i16(ptr %a) vscale_range(2,0) #0 {844; CHECK-LABEL: orv_v16i16:845; CHECK: // %bb.0:846; CHECK-NEXT: ptrue p0.h, vl16847; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]848; CHECK-NEXT: orv h0, p0, z0.h849; CHECK-NEXT: fmov w0, s0850; CHECK-NEXT: ret851 %op = load <16 x i16>, ptr %a852 %res = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %op)853 ret i16 %res854}855 856define i16 @orv_v32i16(ptr %a) #0 {857; VBITS_GE_256-LABEL: orv_v32i16:858; VBITS_GE_256: // %bb.0:859; VBITS_GE_256-NEXT: ptrue p0.h, vl16860; VBITS_GE_256-NEXT: mov x8, #16 // =0x10861; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]862; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]863; VBITS_GE_256-NEXT: orr z0.d, z1.d, z0.d864; VBITS_GE_256-NEXT: orv h0, p0, z0.h865; VBITS_GE_256-NEXT: fmov w0, s0866; VBITS_GE_256-NEXT: ret867;868; VBITS_GE_512-LABEL: orv_v32i16:869; VBITS_GE_512: // %bb.0:870; VBITS_GE_512-NEXT: ptrue p0.h, vl32871; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]872; VBITS_GE_512-NEXT: orv h0, p0, z0.h873; VBITS_GE_512-NEXT: fmov w0, s0874; VBITS_GE_512-NEXT: ret875 %op = load <32 x i16>, ptr %a876 %res = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> %op)877 ret i16 %res878}879 880define i16 @orv_v64i16(ptr %a) vscale_range(8,0) #0 {881; CHECK-LABEL: orv_v64i16:882; CHECK: // %bb.0:883; CHECK-NEXT: ptrue p0.h, vl64884; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]885; CHECK-NEXT: orv h0, p0, z0.h886; CHECK-NEXT: fmov w0, s0887; CHECK-NEXT: ret888 %op = load <64 x i16>, ptr %a889 %res = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> %op)890 ret i16 %res891}892 893define i16 @orv_v128i16(ptr %a) vscale_range(16,0) #0 {894; CHECK-LABEL: orv_v128i16:895; CHECK: // %bb.0:896; CHECK-NEXT: ptrue p0.h, vl128897; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]898; CHECK-NEXT: orv h0, p0, z0.h899; CHECK-NEXT: fmov w0, s0900; CHECK-NEXT: ret901 %op = load <128 x i16>, ptr %a902 %res = call i16 @llvm.vector.reduce.or.v128i16(<128 x i16> %op)903 ret i16 %res904}905 906; No single instruction NEON ORV support. Use SVE.907define i32 @orv_v2i32(<2 x i32> %a) vscale_range(2,0) #0 {908; CHECK-LABEL: orv_v2i32:909; CHECK: // %bb.0:910; CHECK-NEXT: ptrue p0.s, vl2911; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0912; CHECK-NEXT: orv s0, p0, z0.s913; CHECK-NEXT: fmov w0, s0914; CHECK-NEXT: ret915 %res = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %a)916 ret i32 %res917}918 919; No single instruction NEON ORV support. Use SVE.920define i32 @orv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 {921; CHECK-LABEL: orv_v4i32:922; CHECK: // %bb.0:923; CHECK-NEXT: ptrue p0.s, vl4924; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0925; CHECK-NEXT: orv s0, p0, z0.s926; CHECK-NEXT: fmov w0, s0927; CHECK-NEXT: ret928 %res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)929 ret i32 %res930}931 932define i32 @orv_v8i32(ptr %a) vscale_range(2,0) #0 {933; CHECK-LABEL: orv_v8i32:934; CHECK: // %bb.0:935; CHECK-NEXT: ptrue p0.s, vl8936; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]937; CHECK-NEXT: orv s0, p0, z0.s938; CHECK-NEXT: fmov w0, s0939; CHECK-NEXT: ret940 %op = load <8 x i32>, ptr %a941 %res = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %op)942 ret i32 %res943}944 945define i32 @orv_v16i32(ptr %a) #0 {946; VBITS_GE_256-LABEL: orv_v16i32:947; VBITS_GE_256: // %bb.0:948; VBITS_GE_256-NEXT: ptrue p0.s, vl8949; VBITS_GE_256-NEXT: mov x8, #8 // =0x8950; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]951; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]952; VBITS_GE_256-NEXT: orr z0.d, z1.d, z0.d953; VBITS_GE_256-NEXT: orv s0, p0, z0.s954; VBITS_GE_256-NEXT: fmov w0, s0955; VBITS_GE_256-NEXT: ret956;957; VBITS_GE_512-LABEL: orv_v16i32:958; VBITS_GE_512: // %bb.0:959; VBITS_GE_512-NEXT: ptrue p0.s, vl16960; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]961; VBITS_GE_512-NEXT: orv s0, p0, z0.s962; VBITS_GE_512-NEXT: fmov w0, s0963; VBITS_GE_512-NEXT: ret964 %op = load <16 x i32>, ptr %a965 %res = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %op)966 ret i32 %res967}968 969define i32 @orv_v32i32(ptr %a) vscale_range(8,0) #0 {970; CHECK-LABEL: orv_v32i32:971; CHECK: // %bb.0:972; CHECK-NEXT: ptrue p0.s, vl32973; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]974; CHECK-NEXT: orv s0, p0, z0.s975; CHECK-NEXT: fmov w0, s0976; CHECK-NEXT: ret977 %op = load <32 x i32>, ptr %a978 %res = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> %op)979 ret i32 %res980}981 982define i32 @orv_v64i32(ptr %a) vscale_range(16,0) #0 {983; CHECK-LABEL: orv_v64i32:984; CHECK: // %bb.0:985; CHECK-NEXT: ptrue p0.s, vl64986; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]987; CHECK-NEXT: orv s0, p0, z0.s988; CHECK-NEXT: fmov w0, s0989; CHECK-NEXT: ret990 %op = load <64 x i32>, ptr %a991 %res = call i32 @llvm.vector.reduce.or.v64i32(<64 x i32> %op)992 ret i32 %res993}994 995; Nothing to do for single element vectors.996define i64 @orv_v1i64(<1 x i64> %a) vscale_range(2,0) #0 {997; CHECK-LABEL: orv_v1i64:998; CHECK: // %bb.0:999; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01000; CHECK-NEXT: fmov x0, d01001; CHECK-NEXT: ret1002 %res = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %a)1003 ret i64 %res1004}1005 1006; Use SVE for 128-bit vectors1007define i64 @orv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 {1008; CHECK-LABEL: orv_v2i64:1009; CHECK: // %bb.0:1010; CHECK-NEXT: ptrue p0.d, vl21011; CHECK-NEXT: // kill: def $q0 killed $q0 def $z01012; CHECK-NEXT: orv d0, p0, z0.d1013; CHECK-NEXT: fmov x0, d01014; CHECK-NEXT: ret1015 %res = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a)1016 ret i64 %res1017}1018 1019define i64 @orv_v4i64(ptr %a) vscale_range(2,0) #0 {1020; CHECK-LABEL: orv_v4i64:1021; CHECK: // %bb.0:1022; CHECK-NEXT: ptrue p0.d, vl41023; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1024; CHECK-NEXT: orv d0, p0, z0.d1025; CHECK-NEXT: fmov x0, d01026; CHECK-NEXT: ret1027 %op = load <4 x i64>, ptr %a1028 %res = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %op)1029 ret i64 %res1030}1031 1032define i64 @orv_v8i64(ptr %a) #0 {1033; VBITS_GE_256-LABEL: orv_v8i64:1034; VBITS_GE_256: // %bb.0:1035; VBITS_GE_256-NEXT: ptrue p0.d, vl41036; VBITS_GE_256-NEXT: mov x8, #4 // =0x41037; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]1038; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]1039; VBITS_GE_256-NEXT: orr z0.d, z1.d, z0.d1040; VBITS_GE_256-NEXT: orv d0, p0, z0.d1041; VBITS_GE_256-NEXT: fmov x0, d01042; VBITS_GE_256-NEXT: ret1043;1044; VBITS_GE_512-LABEL: orv_v8i64:1045; VBITS_GE_512: // %bb.0:1046; VBITS_GE_512-NEXT: ptrue p0.d, vl81047; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]1048; VBITS_GE_512-NEXT: orv d0, p0, z0.d1049; VBITS_GE_512-NEXT: fmov x0, d01050; VBITS_GE_512-NEXT: ret1051 %op = load <8 x i64>, ptr %a1052 %res = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %op)1053 ret i64 %res1054}1055 1056define i64 @orv_v16i64(ptr %a) vscale_range(8,0) #0 {1057; CHECK-LABEL: orv_v16i64:1058; CHECK: // %bb.0:1059; CHECK-NEXT: ptrue p0.d, vl161060; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1061; CHECK-NEXT: orv d0, p0, z0.d1062; CHECK-NEXT: fmov x0, d01063; CHECK-NEXT: ret1064 %op = load <16 x i64>, ptr %a1065 %res = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> %op)1066 ret i64 %res1067}1068 1069define i64 @orv_v32i64(ptr %a) vscale_range(16,0) #0 {1070; CHECK-LABEL: orv_v32i64:1071; CHECK: // %bb.0:1072; CHECK-NEXT: ptrue p0.d, vl321073; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1074; CHECK-NEXT: orv d0, p0, z0.d1075; CHECK-NEXT: fmov x0, d01076; CHECK-NEXT: ret1077 %op = load <32 x i64>, ptr %a1078 %res = call i64 @llvm.vector.reduce.or.v32i64(<32 x i64> %op)1079 ret i64 %res1080}1081 1082attributes #0 = { "target-features"="+sve" }1083 1084declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)1085declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)1086declare i8 @llvm.vector.reduce.and.v32i8(<32 x i8>)1087declare i8 @llvm.vector.reduce.and.v64i8(<64 x i8>)1088declare i8 @llvm.vector.reduce.and.v128i8(<128 x i8>)1089declare i8 @llvm.vector.reduce.and.v256i8(<256 x i8>)1090 1091declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)1092declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)1093declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)1094declare i16 @llvm.vector.reduce.and.v32i16(<32 x i16>)1095declare i16 @llvm.vector.reduce.and.v64i16(<64 x i16>)1096declare i16 @llvm.vector.reduce.and.v128i16(<128 x i16>)1097 1098declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)1099declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)1100declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32>)1101declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32>)1102declare i32 @llvm.vector.reduce.and.v32i32(<32 x i32>)1103declare i32 @llvm.vector.reduce.and.v64i32(<64 x i32>)1104 1105declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64>)1106declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)1107declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)1108declare i64 @llvm.vector.reduce.and.v8i64(<8 x i64>)1109declare i64 @llvm.vector.reduce.and.v16i64(<16 x i64>)1110declare i64 @llvm.vector.reduce.and.v32i64(<32 x i64>)1111 1112declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)1113declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)1114declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)1115declare i8 @llvm.vector.reduce.or.v64i8(<64 x i8>)1116declare i8 @llvm.vector.reduce.or.v128i8(<128 x i8>)1117declare i8 @llvm.vector.reduce.or.v256i8(<256 x i8>)1118 1119declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)1120declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)1121declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>)1122declare i16 @llvm.vector.reduce.or.v32i16(<32 x i16>)1123declare i16 @llvm.vector.reduce.or.v64i16(<64 x i16>)1124declare i16 @llvm.vector.reduce.or.v128i16(<128 x i16>)1125 1126declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)1127declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)1128declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)1129declare i32 @llvm.vector.reduce.or.v16i32(<16 x i32>)1130declare i32 @llvm.vector.reduce.or.v32i32(<32 x i32>)1131declare i32 @llvm.vector.reduce.or.v64i32(<64 x i32>)1132 1133declare i64 @llvm.vector.reduce.or.v1i64(<1 x i64>)1134declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)1135declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)1136declare i64 @llvm.vector.reduce.or.v8i64(<8 x i64>)1137declare i64 @llvm.vector.reduce.or.v16i64(<16 x i64>)1138declare i64 @llvm.vector.reduce.or.v32i64(<32 x i64>)1139 1140declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)1141declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)1142declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)1143declare i8 @llvm.vector.reduce.xor.v64i8(<64 x i8>)1144declare i8 @llvm.vector.reduce.xor.v128i8(<128 x i8>)1145declare i8 @llvm.vector.reduce.xor.v256i8(<256 x i8>)1146 1147declare i16 @llvm.vector.reduce.xor.v4i16(<4 x i16>)1148declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)1149declare i16 @llvm.vector.reduce.xor.v16i16(<16 x i16>)1150declare i16 @llvm.vector.reduce.xor.v32i16(<32 x i16>)1151declare i16 @llvm.vector.reduce.xor.v64i16(<64 x i16>)1152declare i16 @llvm.vector.reduce.xor.v128i16(<128 x i16>)1153 1154declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>)1155declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)1156declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)1157declare i32 @llvm.vector.reduce.xor.v16i32(<16 x i32>)1158declare i32 @llvm.vector.reduce.xor.v32i32(<32 x i32>)1159declare i32 @llvm.vector.reduce.xor.v64i32(<64 x i32>)1160 1161declare i64 @llvm.vector.reduce.xor.v1i64(<1 x i64>)1162declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)1163declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)1164declare i64 @llvm.vector.reduce.xor.v8i64(<8 x i64>)1165declare i64 @llvm.vector.reduce.xor.v16i64(<16 x i64>)1166declare i64 @llvm.vector.reduce.xor.v32i64(<32 x i64>)1167