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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; LD1B10;11 12define void @masked_gather_v2i8(ptr %a, ptr %b) vscale_range(2,0) #0 {13; CHECK-LABEL: masked_gather_v2i8:14; CHECK: // %bb.0:15; CHECK-NEXT: ptrue p0.d, vl216; CHECK-NEXT: ldr q0, [x1]17; CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d]18; CHECK-NEXT: ptrue p0.s, vl219; CHECK-NEXT: xtn v0.2s, v0.2d20; CHECK-NEXT: st1b { z0.s }, p0, [x0]21; CHECK-NEXT: ret22 %ptrs = load <2 x ptr>, ptr %b23 %vals = call <2 x i8> @llvm.masked.gather.v2i8(<2 x ptr> %ptrs, i32 8, <2 x i1> splat (i1 true), <2 x i8> poison)24 store <2 x i8> %vals, ptr %a25 ret void26}27 28define void @masked_gather_v4i8(ptr %a, ptr %b) vscale_range(2,0) #0 {29; CHECK-LABEL: masked_gather_v4i8:30; CHECK: // %bb.0:31; CHECK-NEXT: ptrue p0.d, vl432; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]33; CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d]34; CHECK-NEXT: st1b { z0.d }, p0, [x0]35; CHECK-NEXT: ret36 %ptrs = load <4 x ptr>, ptr %b37 %vals = call <4 x i8> @llvm.masked.gather.v4i8(<4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 true), <4 x i8> poison)38 store <4 x i8> %vals, ptr %a39 ret void40}41 42define void @masked_gather_v8i8(ptr %a, ptr %b) #0 {43; VBITS_GE_256-LABEL: masked_gather_v8i8:44; VBITS_GE_256: // %bb.0:45; VBITS_GE_256-NEXT: ptrue p0.d, vl446; VBITS_GE_256-NEXT: mov x8, #4 // =0x447; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x1, x8, lsl #3]48; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1]49; VBITS_GE_256-NEXT: ld1b { z0.d }, p0/z, [z0.d]50; VBITS_GE_256-NEXT: ld1b { z1.d }, p0/z, [z1.d]51; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s52; VBITS_GE_256-NEXT: uzp1 z0.h, z0.h, z0.h53; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s54; VBITS_GE_256-NEXT: uzp1 z1.h, z1.h, z1.h55; VBITS_GE_256-NEXT: uzp1 v0.8b, v1.8b, v0.8b56; VBITS_GE_256-NEXT: str d0, [x0]57; VBITS_GE_256-NEXT: ret58;59; VBITS_GE_512-LABEL: masked_gather_v8i8:60; VBITS_GE_512: // %bb.0:61; VBITS_GE_512-NEXT: ptrue p0.d, vl862; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x1]63; VBITS_GE_512-NEXT: ld1b { z0.d }, p0/z, [z0.d]64; VBITS_GE_512-NEXT: uzp1 z0.s, z0.s, z0.s65; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h66; VBITS_GE_512-NEXT: uzp1 z0.b, z0.b, z0.b67; VBITS_GE_512-NEXT: str d0, [x0]68; VBITS_GE_512-NEXT: ret69 %ptrs = load <8 x ptr>, ptr %b70 %vals = call <8 x i8> @llvm.masked.gather.v8i8(<8 x ptr> %ptrs, i32 8, <8 x i1> splat (i1 true), <8 x i8> poison)71 store <8 x i8> %vals, ptr %a72 ret void73}74 75define void @masked_gather_v16i8(ptr %a, ptr %b) vscale_range(8,0) #0 {76; CHECK-LABEL: masked_gather_v16i8:77; CHECK: // %bb.0:78; CHECK-NEXT: ptrue p0.d, vl1679; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]80; CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d]81; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s82; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h83; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b84; CHECK-NEXT: str q0, [x0]85; CHECK-NEXT: ret86 %ptrs = load <16 x ptr>, ptr %b87 %vals = call <16 x i8> @llvm.masked.gather.v16i8(<16 x ptr> %ptrs, i32 8, <16 x i1> splat (i1 true), <16 x i8> poison)88 store <16 x i8> %vals, ptr %a89 ret void90}91 92define void @masked_gather_v32i8(ptr %a, ptr %b) vscale_range(16,0) #0 {93; CHECK-LABEL: masked_gather_v32i8:94; CHECK: // %bb.0:95; CHECK-NEXT: ptrue p0.d, vl3296; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]97; CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d]98; CHECK-NEXT: st1b { z0.d }, p0, [x0]99; CHECK-NEXT: ret100 %ptrs = load <32 x ptr>, ptr %b101 %vals = call <32 x i8> @llvm.masked.gather.v32i8(<32 x ptr> %ptrs, i32 8, <32 x i1> splat (i1 true), <32 x i8> poison)102 store <32 x i8> %vals, ptr %a103 ret void104}105 106;107; LD1H108;109 110define void @masked_gather_v2i16(ptr %a, ptr %b) vscale_range(2,0) #0 {111; CHECK-LABEL: masked_gather_v2i16:112; CHECK: // %bb.0:113; CHECK-NEXT: ptrue p0.d, vl2114; CHECK-NEXT: ldr q0, [x1]115; CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d]116; CHECK-NEXT: ptrue p0.s, vl2117; CHECK-NEXT: xtn v0.2s, v0.2d118; CHECK-NEXT: st1h { z0.s }, p0, [x0]119; CHECK-NEXT: ret120 %ptrs = load <2 x ptr>, ptr %b121 %vals = call <2 x i16> @llvm.masked.gather.v2i16(<2 x ptr> %ptrs, i32 8, <2 x i1> splat (i1 true), <2 x i16> poison)122 store <2 x i16> %vals, ptr %a123 ret void124}125 126define void @masked_gather_v4i16(ptr %a, ptr %b) vscale_range(2,0) #0 {127; CHECK-LABEL: masked_gather_v4i16:128; CHECK: // %bb.0:129; CHECK-NEXT: ptrue p0.d, vl4130; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]131; CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d]132; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s133; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h134; CHECK-NEXT: str d0, [x0]135; CHECK-NEXT: ret136 %ptrs = load <4 x ptr>, ptr %b137 %vals = call <4 x i16> @llvm.masked.gather.v4i16(<4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 true), <4 x i16> poison)138 store <4 x i16> %vals, ptr %a139 ret void140}141 142define void @masked_gather_v8i16(ptr %a, ptr %b) #0 {143; VBITS_GE_256-LABEL: masked_gather_v8i16:144; VBITS_GE_256: // %bb.0:145; VBITS_GE_256-NEXT: ptrue p0.d, vl4146; VBITS_GE_256-NEXT: mov x8, #4 // =0x4147; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x1, x8, lsl #3]148; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1]149; VBITS_GE_256-NEXT: ld1h { z0.d }, p0/z, [z0.d]150; VBITS_GE_256-NEXT: ld1h { z1.d }, p0/z, [z1.d]151; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s152; VBITS_GE_256-NEXT: uzp1 z0.h, z0.h, z0.h153; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s154; VBITS_GE_256-NEXT: uzp1 z1.h, z1.h, z1.h155; VBITS_GE_256-NEXT: mov v1.d[1], v0.d[0]156; VBITS_GE_256-NEXT: str q1, [x0]157; VBITS_GE_256-NEXT: ret158;159; VBITS_GE_512-LABEL: masked_gather_v8i16:160; VBITS_GE_512: // %bb.0:161; VBITS_GE_512-NEXT: ptrue p0.d, vl8162; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x1]163; VBITS_GE_512-NEXT: ld1h { z0.d }, p0/z, [z0.d]164; VBITS_GE_512-NEXT: uzp1 z0.s, z0.s, z0.s165; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h166; VBITS_GE_512-NEXT: str q0, [x0]167; VBITS_GE_512-NEXT: ret168 %ptrs = load <8 x ptr>, ptr %b169 %vals = call <8 x i16> @llvm.masked.gather.v8i16(<8 x ptr> %ptrs, i32 8, <8 x i1> splat (i1 true), <8 x i16> poison)170 store <8 x i16> %vals, ptr %a171 ret void172}173 174define void @masked_gather_v16i16(ptr %a, ptr %b) vscale_range(8,0) #0 {175; CHECK-LABEL: masked_gather_v16i16:176; CHECK: // %bb.0:177; CHECK-NEXT: ptrue p0.d, vl16178; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]179; CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d]180; CHECK-NEXT: st1h { z0.d }, p0, [x0]181; CHECK-NEXT: ret182 %ptrs = load <16 x ptr>, ptr %b183 %vals = call <16 x i16> @llvm.masked.gather.v16i16(<16 x ptr> %ptrs, i32 8, <16 x i1> splat (i1 true), <16 x i16> poison)184 store <16 x i16> %vals, ptr %a185 ret void186}187 188define void @masked_gather_v32i16(ptr %a, ptr %b) vscale_range(16,0) #0 {189; CHECK-LABEL: masked_gather_v32i16:190; CHECK: // %bb.0:191; CHECK-NEXT: ptrue p0.d, vl32192; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]193; CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d]194; CHECK-NEXT: st1h { z0.d }, p0, [x0]195; CHECK-NEXT: ret196 %ptrs = load <32 x ptr>, ptr %b197 %vals = call <32 x i16> @llvm.masked.gather.v32i16(<32 x ptr> %ptrs, i32 8, <32 x i1> splat (i1 true), <32 x i16> poison)198 store <32 x i16> %vals, ptr %a199 ret void200}201 202;203; LD1W204;205 206define void @masked_gather_v2i32(ptr %a, ptr %b) vscale_range(2,0) #0 {207; CHECK-LABEL: masked_gather_v2i32:208; CHECK: // %bb.0:209; CHECK-NEXT: ptrue p0.d, vl2210; CHECK-NEXT: ldr q0, [x1]211; CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d]212; CHECK-NEXT: xtn v0.2s, v0.2d213; CHECK-NEXT: str d0, [x0]214; CHECK-NEXT: ret215 %ptrs = load <2 x ptr>, ptr %b216 %vals = call <2 x i32> @llvm.masked.gather.v2i32(<2 x ptr> %ptrs, i32 8, <2 x i1> splat (i1 true), <2 x i32> poison)217 store <2 x i32> %vals, ptr %a218 ret void219}220 221define void @masked_gather_v4i32(ptr %a, ptr %b) vscale_range(2,0) #0 {222; CHECK-LABEL: masked_gather_v4i32:223; CHECK: // %bb.0:224; CHECK-NEXT: ptrue p0.d, vl4225; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]226; CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d]227; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s228; CHECK-NEXT: str q0, [x0]229; CHECK-NEXT: ret230 %ptrs = load <4 x ptr>, ptr %b231 %vals = call <4 x i32> @llvm.masked.gather.v4i32(<4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 true), <4 x i32> poison)232 store <4 x i32> %vals, ptr %a233 ret void234}235 236define void @masked_gather_v8i32(ptr %a, ptr %b) #0 {237; VBITS_GE_256-LABEL: masked_gather_v8i32:238; VBITS_GE_256: // %bb.0:239; VBITS_GE_256-NEXT: ptrue p0.d, vl4240; VBITS_GE_256-NEXT: mov x8, #4 // =0x4241; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x1, x8, lsl #3]242; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1]243; VBITS_GE_256-NEXT: ld1w { z0.d }, p0/z, [z0.d]244; VBITS_GE_256-NEXT: ld1w { z1.d }, p0/z, [z1.d]245; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s246; VBITS_GE_256-NEXT: ptrue p0.s, vl4247; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s248; VBITS_GE_256-NEXT: splice z1.s, p0, z1.s, z0.s249; VBITS_GE_256-NEXT: ptrue p0.s, vl8250; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]251; VBITS_GE_256-NEXT: ret252;253; VBITS_GE_512-LABEL: masked_gather_v8i32:254; VBITS_GE_512: // %bb.0:255; VBITS_GE_512-NEXT: ptrue p0.d, vl8256; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x1]257; VBITS_GE_512-NEXT: ld1w { z0.d }, p0/z, [z0.d]258; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [x0]259; VBITS_GE_512-NEXT: ret260 %ptrs = load <8 x ptr>, ptr %b261 %vals = call <8 x i32> @llvm.masked.gather.v8i32(<8 x ptr> %ptrs, i32 8, <8 x i1> splat (i1 true), <8 x i32> poison)262 store <8 x i32> %vals, ptr %a263 ret void264}265 266define void @masked_gather_v16i32(ptr %a, ptr %b) vscale_range(8,0) #0 {267; CHECK-LABEL: masked_gather_v16i32:268; CHECK: // %bb.0:269; CHECK-NEXT: ptrue p0.d, vl16270; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]271; CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d]272; CHECK-NEXT: st1w { z0.d }, p0, [x0]273; CHECK-NEXT: ret274 %ptrs = load <16 x ptr>, ptr %b275 %vals = call <16 x i32> @llvm.masked.gather.v16i32(<16 x ptr> %ptrs, i32 8, <16 x i1> splat (i1 true), <16 x i32> poison)276 store <16 x i32> %vals, ptr %a277 ret void278}279 280define void @masked_gather_v32i32(ptr %a, ptr %b) vscale_range(16,0) #0 {281; CHECK-LABEL: masked_gather_v32i32:282; CHECK: // %bb.0:283; CHECK-NEXT: ptrue p0.d, vl32284; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]285; CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d]286; CHECK-NEXT: st1w { z0.d }, p0, [x0]287; CHECK-NEXT: ret288 %ptrs = load <32 x ptr>, ptr %b289 %vals = call <32 x i32> @llvm.masked.gather.v32i32(<32 x ptr> %ptrs, i32 8, <32 x i1> splat (i1 true), <32 x i32> poison)290 store <32 x i32> %vals, ptr %a291 ret void292}293 294;295; LD1D296;297 298define void @masked_gather_v2i64(ptr %a, ptr %b) vscale_range(2,0) #0 {299; CHECK-LABEL: masked_gather_v2i64:300; CHECK: // %bb.0:301; CHECK-NEXT: ptrue p0.d, vl2302; CHECK-NEXT: ldr q0, [x1]303; CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d]304; CHECK-NEXT: str q0, [x0]305; CHECK-NEXT: ret306 %ptrs = load <2 x ptr>, ptr %b307 %vals = call <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr> %ptrs, i32 8, <2 x i1> splat (i1 true), <2 x i64> poison)308 store <2 x i64> %vals, ptr %a309 ret void310}311 312define void @masked_gather_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {313; CHECK-LABEL: masked_gather_v4i64:314; CHECK: // %bb.0:315; CHECK-NEXT: ptrue p0.d, vl4316; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]317; CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d]318; CHECK-NEXT: st1d { z0.d }, p0, [x0]319; CHECK-NEXT: ret320 %ptrs = load <4 x ptr>, ptr %b321 %vals = call <4 x i64> @llvm.masked.gather.v4i64(<4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 true), <4 x i64> poison)322 store <4 x i64> %vals, ptr %a323 ret void324}325 326define void @masked_gather_v8i64(ptr %a, ptr %b) #0 {327; VBITS_GE_256-LABEL: masked_gather_v8i64:328; VBITS_GE_256: // %bb.0:329; VBITS_GE_256-NEXT: ptrue p0.d, vl4330; VBITS_GE_256-NEXT: mov x8, #4 // =0x4331; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x1, x8, lsl #3]332; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1]333; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [z0.d]334; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [z1.d]335; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]336; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]337; VBITS_GE_256-NEXT: ret338;339; VBITS_GE_512-LABEL: masked_gather_v8i64:340; VBITS_GE_512: // %bb.0:341; VBITS_GE_512-NEXT: ptrue p0.d, vl8342; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x1]343; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [z0.d]344; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]345; VBITS_GE_512-NEXT: ret346 %ptrs = load <8 x ptr>, ptr %b347 %vals = call <8 x i64> @llvm.masked.gather.v8i64(<8 x ptr> %ptrs, i32 8, <8 x i1> splat (i1 true), <8 x i64> poison)348 store <8 x i64> %vals, ptr %a349 ret void350}351 352define void @masked_gather_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {353; CHECK-LABEL: masked_gather_v16i64:354; CHECK: // %bb.0:355; CHECK-NEXT: ptrue p0.d, vl16356; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]357; CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d]358; CHECK-NEXT: st1d { z0.d }, p0, [x0]359; CHECK-NEXT: ret360 %ptrs = load <16 x ptr>, ptr %b361 %vals = call <16 x i64> @llvm.masked.gather.v16i64(<16 x ptr> %ptrs, i32 8, <16 x i1> splat (i1 true), <16 x i64> poison)362 store <16 x i64> %vals, ptr %a363 ret void364}365 366define void @masked_gather_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {367; CHECK-LABEL: masked_gather_v32i64:368; CHECK: // %bb.0:369; CHECK-NEXT: ptrue p0.d, vl32370; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]371; CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d]372; CHECK-NEXT: st1d { z0.d }, p0, [x0]373; CHECK-NEXT: ret374 %ptrs = load <32 x ptr>, ptr %b375 %vals = call <32 x i64> @llvm.masked.gather.v32i64(<32 x ptr> %ptrs, i32 8, <32 x i1> splat (i1 true), <32 x i64> poison)376 store <32 x i64> %vals, ptr %a377 ret void378}379 380declare <2 x i8> @llvm.masked.gather.v2i8(<2 x ptr>, i32, <2 x i1>, <2 x i8>)381declare <4 x i8> @llvm.masked.gather.v4i8(<4 x ptr>, i32, <4 x i1>, <4 x i8>)382declare <8 x i8> @llvm.masked.gather.v8i8(<8 x ptr>, i32, <8 x i1>, <8 x i8>)383declare <16 x i8> @llvm.masked.gather.v16i8(<16 x ptr>, i32, <16 x i1>, <16 x i8>)384declare <32 x i8> @llvm.masked.gather.v32i8(<32 x ptr>, i32, <32 x i1>, <32 x i8>)385 386declare <2 x i16> @llvm.masked.gather.v2i16(<2 x ptr>, i32, <2 x i1>, <2 x i16>)387declare <4 x i16> @llvm.masked.gather.v4i16(<4 x ptr>, i32, <4 x i1>, <4 x i16>)388declare <8 x i16> @llvm.masked.gather.v8i16(<8 x ptr>, i32, <8 x i1>, <8 x i16>)389declare <16 x i16> @llvm.masked.gather.v16i16(<16 x ptr>, i32, <16 x i1>, <16 x i16>)390declare <32 x i16> @llvm.masked.gather.v32i16(<32 x ptr>, i32, <32 x i1>, <32 x i16>)391 392declare <2 x i32> @llvm.masked.gather.v2i32(<2 x ptr>, i32, <2 x i1>, <2 x i32>)393declare <4 x i32> @llvm.masked.gather.v4i32(<4 x ptr>, i32, <4 x i1>, <4 x i32>)394declare <8 x i32> @llvm.masked.gather.v8i32(<8 x ptr>, i32, <8 x i1>, <8 x i32>)395declare <16 x i32> @llvm.masked.gather.v16i32(<16 x ptr>, i32, <16 x i1>, <16 x i32>)396declare <32 x i32> @llvm.masked.gather.v32i32(<32 x ptr>, i32, <32 x i1>, <32 x i32>)397 398declare <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr>, i32, <2 x i1>, <2 x i64>)399declare <4 x i64> @llvm.masked.gather.v4i64(<4 x ptr>, i32, <4 x i1>, <4 x i64>)400declare <8 x i64> @llvm.masked.gather.v8i64(<8 x ptr>, i32, <8 x i1>, <8 x i64>)401declare <16 x i64> @llvm.masked.gather.v16i64(<16 x ptr>, i32, <16 x i1>, <16 x i64>)402declare <32 x i64> @llvm.masked.gather.v32i64(<32 x ptr>, i32, <32 x i1>, <32 x i64>)403 404attributes #0 = { "target-features"="+sve" }405