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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; ST1B10;11 12define void @masked_scatter_v2i8(ptr %a, ptr %b) vscale_range(2,0) #0 {13; CHECK-LABEL: masked_scatter_v2i8:14; CHECK: // %bb.0:15; CHECK-NEXT: ldr h0, [x0]16; CHECK-NEXT: ptrue p0.d, vl217; CHECK-NEXT: ushll v0.8h, v0.8b, #018; CHECK-NEXT: ushll v0.4s, v0.4h, #019; CHECK-NEXT: cmeq v1.2s, v0.2s, #020; CHECK-NEXT: ushll v0.2d, v0.2s, #021; CHECK-NEXT: sshll v1.2d, v1.2s, #022; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #023; CHECK-NEXT: ldr q1, [x1]24; CHECK-NEXT: st1b { z0.d }, p0, [z1.d]25; CHECK-NEXT: ret26 %vals = load <2 x i8>, ptr %a27 %ptrs = load <2 x ptr>, ptr %b28 %mask = icmp eq <2 x i8> %vals, zeroinitializer29 call void @llvm.masked.scatter.v2i8(<2 x i8> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask)30 ret void31}32 33define void @masked_scatter_v4i8(ptr %a, ptr %b) vscale_range(2,0) #0 {34; CHECK-LABEL: masked_scatter_v4i8:35; CHECK: // %bb.0:36; CHECK-NEXT: ldr s0, [x0]37; CHECK-NEXT: ptrue p0.d, vl438; CHECK-NEXT: ushll v0.8h, v0.8b, #039; CHECK-NEXT: cmeq v1.4h, v0.4h, #040; CHECK-NEXT: uunpklo z0.s, z0.h41; CHECK-NEXT: sunpklo z1.s, z1.h42; CHECK-NEXT: uunpklo z0.d, z0.s43; CHECK-NEXT: sunpklo z1.d, z1.s44; CHECK-NEXT: cmpne p1.d, p0/z, z1.d, #045; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]46; CHECK-NEXT: st1b { z0.d }, p1, [z1.d]47; CHECK-NEXT: ret48 %vals = load <4 x i8>, ptr %a49 %ptrs = load <4 x ptr>, ptr %b50 %mask = icmp eq <4 x i8> %vals, zeroinitializer51 call void @llvm.masked.scatter.v4i8(<4 x i8> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask)52 ret void53}54 55define void @masked_scatter_v8i8(ptr %a, ptr %b) #0 {56; VBITS_GE_256-LABEL: masked_scatter_v8i8:57; VBITS_GE_256: // %bb.0:58; VBITS_GE_256-NEXT: ldr d0, [x0]59; VBITS_GE_256-NEXT: ptrue p0.d, vl460; VBITS_GE_256-NEXT: mov x8, #4 // =0x461; VBITS_GE_256-NEXT: cmeq v1.8b, v0.8b, #062; VBITS_GE_256-NEXT: zip1 v3.8b, v0.8b, v0.8b63; VBITS_GE_256-NEXT: ld1d { z4.d }, p0/z, [x1, x8, lsl #3]64; VBITS_GE_256-NEXT: zip1 v2.8b, v1.8b, v0.8b65; VBITS_GE_256-NEXT: zip2 v1.8b, v1.8b, v0.8b66; VBITS_GE_256-NEXT: zip2 v0.8b, v0.8b, v0.8b67; VBITS_GE_256-NEXT: uunpklo z3.s, z3.h68; VBITS_GE_256-NEXT: shl v2.4h, v2.4h, #869; VBITS_GE_256-NEXT: shl v1.4h, v1.4h, #870; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h71; VBITS_GE_256-NEXT: uunpklo z3.d, z3.s72; VBITS_GE_256-NEXT: sshr v2.4h, v2.4h, #873; VBITS_GE_256-NEXT: sshr v1.4h, v1.4h, #874; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s75; VBITS_GE_256-NEXT: sunpklo z2.s, z2.h76; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h77; VBITS_GE_256-NEXT: sunpklo z2.d, z2.s78; VBITS_GE_256-NEXT: sunpklo z1.d, z1.s79; VBITS_GE_256-NEXT: cmpne p1.d, p0/z, z2.d, #080; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x1]81; VBITS_GE_256-NEXT: cmpne p0.d, p0/z, z1.d, #082; VBITS_GE_256-NEXT: st1b { z3.d }, p1, [z2.d]83; VBITS_GE_256-NEXT: st1b { z0.d }, p0, [z4.d]84; VBITS_GE_256-NEXT: ret85;86; VBITS_GE_512-LABEL: masked_scatter_v8i8:87; VBITS_GE_512: // %bb.0:88; VBITS_GE_512-NEXT: ldr d0, [x0]89; VBITS_GE_512-NEXT: ptrue p0.d, vl890; VBITS_GE_512-NEXT: cmeq v1.8b, v0.8b, #091; VBITS_GE_512-NEXT: uunpklo z0.h, z0.b92; VBITS_GE_512-NEXT: sunpklo z1.h, z1.b93; VBITS_GE_512-NEXT: uunpklo z0.s, z0.h94; VBITS_GE_512-NEXT: sunpklo z1.s, z1.h95; VBITS_GE_512-NEXT: uunpklo z0.d, z0.s96; VBITS_GE_512-NEXT: sunpklo z1.d, z1.s97; VBITS_GE_512-NEXT: cmpne p1.d, p0/z, z1.d, #098; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]99; VBITS_GE_512-NEXT: st1b { z0.d }, p1, [z1.d]100; VBITS_GE_512-NEXT: ret101 %vals = load <8 x i8>, ptr %a102 %ptrs = load <8 x ptr>, ptr %b103 %mask = icmp eq <8 x i8> %vals, zeroinitializer104 call void @llvm.masked.scatter.v8i8(<8 x i8> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask)105 ret void106}107 108define void @masked_scatter_v16i8(ptr %a, ptr %b) vscale_range(8,0) #0 {109; CHECK-LABEL: masked_scatter_v16i8:110; CHECK: // %bb.0:111; CHECK-NEXT: ldr q0, [x0]112; CHECK-NEXT: ptrue p0.d, vl16113; CHECK-NEXT: cmeq v1.16b, v0.16b, #0114; CHECK-NEXT: uunpklo z0.h, z0.b115; CHECK-NEXT: sunpklo z1.h, z1.b116; CHECK-NEXT: uunpklo z0.s, z0.h117; CHECK-NEXT: sunpklo z1.s, z1.h118; CHECK-NEXT: uunpklo z0.d, z0.s119; CHECK-NEXT: sunpklo z1.d, z1.s120; CHECK-NEXT: cmpne p1.d, p0/z, z1.d, #0121; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]122; CHECK-NEXT: st1b { z0.d }, p1, [z1.d]123; CHECK-NEXT: ret124 %vals = load <16 x i8>, ptr %a125 %ptrs = load <16 x ptr>, ptr %b126 %mask = icmp eq <16 x i8> %vals, zeroinitializer127 call void @llvm.masked.scatter.v16i8(<16 x i8> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask)128 ret void129}130 131define void @masked_scatter_v32i8(ptr %a, ptr %b) vscale_range(16,0) #0 {132; CHECK-LABEL: masked_scatter_v32i8:133; CHECK: // %bb.0:134; CHECK-NEXT: ptrue p0.b, vl32135; CHECK-NEXT: ptrue p1.d, vl32136; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]137; CHECK-NEXT: uunpklo z1.h, z0.b138; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0139; CHECK-NEXT: uunpklo z0.s, z1.h140; CHECK-NEXT: punpklo p0.h, p0.b141; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]142; CHECK-NEXT: punpklo p0.h, p0.b143; CHECK-NEXT: uunpklo z0.d, z0.s144; CHECK-NEXT: punpklo p0.h, p0.b145; CHECK-NEXT: st1b { z0.d }, p0, [z1.d]146; CHECK-NEXT: ret147 %vals = load <32 x i8>, ptr %a148 %ptrs = load <32 x ptr>, ptr %b149 %mask = icmp eq <32 x i8> %vals, zeroinitializer150 call void @llvm.masked.scatter.v32i8(<32 x i8> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)151 ret void152}153 154;155; ST1H156;157 158define void @masked_scatter_v2i16(ptr %a, ptr %b) vscale_range(2,0) #0 {159; CHECK-LABEL: masked_scatter_v2i16:160; CHECK: // %bb.0:161; CHECK-NEXT: ldr s0, [x0]162; CHECK-NEXT: ptrue p0.d, vl2163; CHECK-NEXT: ushll v0.4s, v0.4h, #0164; CHECK-NEXT: cmeq v1.2s, v0.2s, #0165; CHECK-NEXT: ushll v0.2d, v0.2s, #0166; CHECK-NEXT: sshll v1.2d, v1.2s, #0167; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0168; CHECK-NEXT: ldr q1, [x1]169; CHECK-NEXT: st1h { z0.d }, p0, [z1.d]170; CHECK-NEXT: ret171 %vals = load <2 x i16>, ptr %a172 %ptrs = load <2 x ptr>, ptr %b173 %mask = icmp eq <2 x i16> %vals, zeroinitializer174 call void @llvm.masked.scatter.v2i16(<2 x i16> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask)175 ret void176}177 178define void @masked_scatter_v4i16(ptr %a, ptr %b) vscale_range(2,0) #0 {179; CHECK-LABEL: masked_scatter_v4i16:180; CHECK: // %bb.0:181; CHECK-NEXT: ldr d0, [x0]182; CHECK-NEXT: ptrue p0.d, vl4183; CHECK-NEXT: cmeq v1.4h, v0.4h, #0184; CHECK-NEXT: uunpklo z0.s, z0.h185; CHECK-NEXT: sunpklo z1.s, z1.h186; CHECK-NEXT: uunpklo z0.d, z0.s187; CHECK-NEXT: sunpklo z1.d, z1.s188; CHECK-NEXT: cmpne p1.d, p0/z, z1.d, #0189; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]190; CHECK-NEXT: st1h { z0.d }, p1, [z1.d]191; CHECK-NEXT: ret192 %vals = load <4 x i16>, ptr %a193 %ptrs = load <4 x ptr>, ptr %b194 %mask = icmp eq <4 x i16> %vals, zeroinitializer195 call void @llvm.masked.scatter.v4i16(<4 x i16> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask)196 ret void197}198 199define void @masked_scatter_v8i16(ptr %a, ptr %b) #0 {200; VBITS_GE_256-LABEL: masked_scatter_v8i16:201; VBITS_GE_256: // %bb.0:202; VBITS_GE_256-NEXT: ldr q0, [x0]203; VBITS_GE_256-NEXT: ptrue p0.d, vl4204; VBITS_GE_256-NEXT: mov x8, #4 // =0x4205; VBITS_GE_256-NEXT: cmeq v1.8h, v0.8h, #0206; VBITS_GE_256-NEXT: uunpklo z3.s, z0.h207; VBITS_GE_256-NEXT: ext v0.16b, v0.16b, v0.16b, #8208; VBITS_GE_256-NEXT: ld1d { z4.d }, p0/z, [x1, x8, lsl #3]209; VBITS_GE_256-NEXT: sunpklo z2.s, z1.h210; VBITS_GE_256-NEXT: ext v1.16b, v1.16b, v1.16b, #8211; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h212; VBITS_GE_256-NEXT: uunpklo z3.d, z3.s213; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h214; VBITS_GE_256-NEXT: sunpklo z2.d, z2.s215; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s216; VBITS_GE_256-NEXT: sunpklo z1.d, z1.s217; VBITS_GE_256-NEXT: cmpne p1.d, p0/z, z2.d, #0218; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x1]219; VBITS_GE_256-NEXT: cmpne p0.d, p0/z, z1.d, #0220; VBITS_GE_256-NEXT: st1h { z3.d }, p1, [z2.d]221; VBITS_GE_256-NEXT: st1h { z0.d }, p0, [z4.d]222; VBITS_GE_256-NEXT: ret223;224; VBITS_GE_512-LABEL: masked_scatter_v8i16:225; VBITS_GE_512: // %bb.0:226; VBITS_GE_512-NEXT: ldr q0, [x0]227; VBITS_GE_512-NEXT: ptrue p0.d, vl8228; VBITS_GE_512-NEXT: cmeq v1.8h, v0.8h, #0229; VBITS_GE_512-NEXT: uunpklo z0.s, z0.h230; VBITS_GE_512-NEXT: sunpklo z1.s, z1.h231; VBITS_GE_512-NEXT: uunpklo z0.d, z0.s232; VBITS_GE_512-NEXT: sunpklo z1.d, z1.s233; VBITS_GE_512-NEXT: cmpne p1.d, p0/z, z1.d, #0234; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]235; VBITS_GE_512-NEXT: st1h { z0.d }, p1, [z1.d]236; VBITS_GE_512-NEXT: ret237 %vals = load <8 x i16>, ptr %a238 %ptrs = load <8 x ptr>, ptr %b239 %mask = icmp eq <8 x i16> %vals, zeroinitializer240 call void @llvm.masked.scatter.v8i16(<8 x i16> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask)241 ret void242}243 244define void @masked_scatter_v16i16(ptr %a, ptr %b) vscale_range(8,0) #0 {245; CHECK-LABEL: masked_scatter_v16i16:246; CHECK: // %bb.0:247; CHECK-NEXT: ptrue p0.h, vl16248; CHECK-NEXT: ptrue p1.d, vl16249; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]250; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]251; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0252; CHECK-NEXT: uunpklo z0.s, z0.h253; CHECK-NEXT: uunpklo z0.d, z0.s254; CHECK-NEXT: punpklo p0.h, p0.b255; CHECK-NEXT: punpklo p0.h, p0.b256; CHECK-NEXT: st1h { z0.d }, p0, [z1.d]257; CHECK-NEXT: ret258 %vals = load <16 x i16>, ptr %a259 %ptrs = load <16 x ptr>, ptr %b260 %mask = icmp eq <16 x i16> %vals, zeroinitializer261 call void @llvm.masked.scatter.v16i16(<16 x i16> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask)262 ret void263}264 265define void @masked_scatter_v32i16(ptr %a, ptr %b) vscale_range(16,0) #0 {266; CHECK-LABEL: masked_scatter_v32i16:267; CHECK: // %bb.0:268; CHECK-NEXT: ptrue p0.h, vl32269; CHECK-NEXT: ptrue p1.d, vl32270; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]271; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]272; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0273; CHECK-NEXT: uunpklo z0.s, z0.h274; CHECK-NEXT: uunpklo z0.d, z0.s275; CHECK-NEXT: punpklo p0.h, p0.b276; CHECK-NEXT: punpklo p0.h, p0.b277; CHECK-NEXT: st1h { z0.d }, p0, [z1.d]278; CHECK-NEXT: ret279 %vals = load <32 x i16>, ptr %a280 %ptrs = load <32 x ptr>, ptr %b281 %mask = icmp eq <32 x i16> %vals, zeroinitializer282 call void @llvm.masked.scatter.v32i16(<32 x i16> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)283 ret void284}285 286;287; ST1W288;289 290define void @masked_scatter_v2i32(ptr %a, ptr %b) vscale_range(2,0) #0 {291; CHECK-LABEL: masked_scatter_v2i32:292; CHECK: // %bb.0:293; CHECK-NEXT: ldr d0, [x0]294; CHECK-NEXT: ptrue p0.d, vl2295; CHECK-NEXT: ushll v0.2d, v0.2s, #0296; CHECK-NEXT: cmeq v1.2d, v0.2d, #0297; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0298; CHECK-NEXT: ldr q1, [x1]299; CHECK-NEXT: st1w { z0.d }, p0, [z1.d]300; CHECK-NEXT: ret301 %vals = load <2 x i32>, ptr %a302 %ptrs = load <2 x ptr>, ptr %b303 %mask = icmp eq <2 x i32> %vals, zeroinitializer304 call void @llvm.masked.scatter.v2i32(<2 x i32> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask)305 ret void306}307 308define void @masked_scatter_v4i32(ptr %a, ptr %b) vscale_range(2,0) #0 {309; CHECK-LABEL: masked_scatter_v4i32:310; CHECK: // %bb.0:311; CHECK-NEXT: ldr q0, [x0]312; CHECK-NEXT: ptrue p0.d, vl4313; CHECK-NEXT: cmeq v1.4s, v0.4s, #0314; CHECK-NEXT: uunpklo z0.d, z0.s315; CHECK-NEXT: sunpklo z1.d, z1.s316; CHECK-NEXT: cmpne p1.d, p0/z, z1.d, #0317; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]318; CHECK-NEXT: st1w { z0.d }, p1, [z1.d]319; CHECK-NEXT: ret320 %vals = load <4 x i32>, ptr %a321 %ptrs = load <4 x ptr>, ptr %b322 %mask = icmp eq <4 x i32> %vals, zeroinitializer323 call void @llvm.masked.scatter.v4i32(<4 x i32> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask)324 ret void325}326 327define void @masked_scatter_v8i32(ptr %a, ptr %b) #0 {328; VBITS_GE_256-LABEL: masked_scatter_v8i32:329; VBITS_GE_256: // %bb.0:330; VBITS_GE_256-NEXT: ptrue p0.s, vl8331; VBITS_GE_256-NEXT: mov x8, #4 // =0x4332; VBITS_GE_256-NEXT: ptrue p1.d, vl4333; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0]334; VBITS_GE_256-NEXT: ld1d { z3.d }, p1/z, [x1]335; VBITS_GE_256-NEXT: ld1d { z4.d }, p1/z, [x1, x8, lsl #3]336; VBITS_GE_256-NEXT: cmpeq p0.s, p0/z, z0.s, #0337; VBITS_GE_256-NEXT: uunpklo z2.d, z0.s338; VBITS_GE_256-NEXT: ext z0.b, z0.b, z0.b, #16339; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s340; VBITS_GE_256-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff341; VBITS_GE_256-NEXT: punpklo p0.h, p0.b342; VBITS_GE_256-NEXT: and p0.b, p0/z, p0.b, p1.b343; VBITS_GE_256-NEXT: ext z1.b, z1.b, z1.b, #16344; VBITS_GE_256-NEXT: st1w { z2.d }, p0, [z3.d]345; VBITS_GE_256-NEXT: sunpklo z1.d, z1.s346; VBITS_GE_256-NEXT: cmpne p0.d, p1/z, z1.d, #0347; VBITS_GE_256-NEXT: st1w { z0.d }, p0, [z4.d]348; VBITS_GE_256-NEXT: ret349;350; VBITS_GE_512-LABEL: masked_scatter_v8i32:351; VBITS_GE_512: // %bb.0:352; VBITS_GE_512-NEXT: ptrue p0.s, vl8353; VBITS_GE_512-NEXT: ptrue p1.d, vl8354; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]355; VBITS_GE_512-NEXT: ld1d { z1.d }, p1/z, [x1]356; VBITS_GE_512-NEXT: cmpeq p0.s, p0/z, z0.s, #0357; VBITS_GE_512-NEXT: uunpklo z0.d, z0.s358; VBITS_GE_512-NEXT: punpklo p0.h, p0.b359; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [z1.d]360; VBITS_GE_512-NEXT: ret361 %vals = load <8 x i32>, ptr %a362 %ptrs = load <8 x ptr>, ptr %b363 %mask = icmp eq <8 x i32> %vals, zeroinitializer364 call void @llvm.masked.scatter.v8i32(<8 x i32> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask)365 ret void366}367 368define void @masked_scatter_v16i32(ptr %a, ptr %b) vscale_range(8,0) #0 {369; CHECK-LABEL: masked_scatter_v16i32:370; CHECK: // %bb.0:371; CHECK-NEXT: ptrue p0.s, vl16372; CHECK-NEXT: ptrue p1.d, vl16373; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]374; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]375; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0376; CHECK-NEXT: uunpklo z0.d, z0.s377; CHECK-NEXT: punpklo p0.h, p0.b378; CHECK-NEXT: st1w { z0.d }, p0, [z1.d]379; CHECK-NEXT: ret380 %vals = load <16 x i32>, ptr %a381 %ptrs = load <16 x ptr>, ptr %b382 %mask = icmp eq <16 x i32> %vals, zeroinitializer383 call void @llvm.masked.scatter.v16i32(<16 x i32> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask)384 ret void385}386 387define void @masked_scatter_v32i32(ptr %a, ptr %b) vscale_range(16,0) #0 {388; CHECK-LABEL: masked_scatter_v32i32:389; CHECK: // %bb.0:390; CHECK-NEXT: ptrue p0.s, vl32391; CHECK-NEXT: ptrue p1.d, vl32392; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]393; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]394; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0395; CHECK-NEXT: uunpklo z0.d, z0.s396; CHECK-NEXT: punpklo p0.h, p0.b397; CHECK-NEXT: st1w { z0.d }, p0, [z1.d]398; CHECK-NEXT: ret399 %vals = load <32 x i32>, ptr %a400 %ptrs = load <32 x ptr>, ptr %b401 %mask = icmp eq <32 x i32> %vals, zeroinitializer402 call void @llvm.masked.scatter.v32i32(<32 x i32> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)403 ret void404}405 406;407; ST1D408;409 410; Scalarize 1 x i64 scatters411define void @masked_scatter_v1i64(ptr %a, ptr %b) vscale_range(2,0) #0 {412; CHECK-LABEL: masked_scatter_v1i64:413; CHECK: // %bb.0:414; CHECK-NEXT: ldr d0, [x0]415; CHECK-NEXT: fmov x8, d0416; CHECK-NEXT: cbnz x8, .LBB15_2417; CHECK-NEXT: // %bb.1: // %cond.store418; CHECK-NEXT: ldr d1, [x1]419; CHECK-NEXT: fmov x8, d1420; CHECK-NEXT: str d0, [x8]421; CHECK-NEXT: .LBB15_2: // %else422; CHECK-NEXT: ret423 %vals = load <1 x i64>, ptr %a424 %ptrs = load <1 x ptr>, ptr %b425 %mask = icmp eq <1 x i64> %vals, zeroinitializer426 call void @llvm.masked.scatter.v1i64(<1 x i64> %vals, <1 x ptr> %ptrs, i32 8, <1 x i1> %mask)427 ret void428}429 430define void @masked_scatter_v2i64(ptr %a, ptr %b) vscale_range(2,0) #0 {431; CHECK-LABEL: masked_scatter_v2i64:432; CHECK: // %bb.0:433; CHECK-NEXT: ptrue p0.d, vl2434; CHECK-NEXT: ldr q0, [x0]435; CHECK-NEXT: ldr q1, [x1]436; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #0437; CHECK-NEXT: st1d { z0.d }, p0, [z1.d]438; CHECK-NEXT: ret439 %vals = load <2 x i64>, ptr %a440 %ptrs = load <2 x ptr>, ptr %b441 %mask = icmp eq <2 x i64> %vals, zeroinitializer442 call void @llvm.masked.scatter.v2i64(<2 x i64> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask)443 ret void444}445 446define void @masked_scatter_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {447; CHECK-LABEL: masked_scatter_v4i64:448; CHECK: // %bb.0:449; CHECK-NEXT: ptrue p0.d, vl4450; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]451; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]452; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, #0453; CHECK-NEXT: st1d { z0.d }, p1, [z1.d]454; CHECK-NEXT: ret455 %vals = load <4 x i64>, ptr %a456 %ptrs = load <4 x ptr>, ptr %b457 %mask = icmp eq <4 x i64> %vals, zeroinitializer458 call void @llvm.masked.scatter.v4i64(<4 x i64> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask)459 ret void460}461 462define void @masked_scatter_v8i64(ptr %a, ptr %b) #0 {463; VBITS_GE_256-LABEL: masked_scatter_v8i64:464; VBITS_GE_256: // %bb.0:465; VBITS_GE_256-NEXT: ptrue p0.d, vl4466; VBITS_GE_256-NEXT: mov x8, #4 // =0x4467; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0]468; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0, x8, lsl #3]469; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1]470; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1, x8, lsl #3]471; VBITS_GE_256-NEXT: cmpeq p1.d, p0/z, z0.d, #0472; VBITS_GE_256-NEXT: cmpeq p0.d, p0/z, z2.d, #0473; VBITS_GE_256-NEXT: st1d { z0.d }, p1, [z1.d]474; VBITS_GE_256-NEXT: st1d { z2.d }, p0, [z3.d]475; VBITS_GE_256-NEXT: ret476;477; VBITS_GE_512-LABEL: masked_scatter_v8i64:478; VBITS_GE_512: // %bb.0:479; VBITS_GE_512-NEXT: ptrue p0.d, vl8480; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]481; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]482; VBITS_GE_512-NEXT: cmpeq p1.d, p0/z, z0.d, #0483; VBITS_GE_512-NEXT: st1d { z0.d }, p1, [z1.d]484; VBITS_GE_512-NEXT: ret485 %vals = load <8 x i64>, ptr %a486 %ptrs = load <8 x ptr>, ptr %b487 %mask = icmp eq <8 x i64> %vals, zeroinitializer488 call void @llvm.masked.scatter.v8i64(<8 x i64> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask)489 ret void490}491 492define void @masked_scatter_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {493; CHECK-LABEL: masked_scatter_v16i64:494; CHECK: // %bb.0:495; CHECK-NEXT: ptrue p0.d, vl16496; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]497; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]498; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, #0499; CHECK-NEXT: st1d { z0.d }, p1, [z1.d]500; CHECK-NEXT: ret501 %vals = load <16 x i64>, ptr %a502 %ptrs = load <16 x ptr>, ptr %b503 %mask = icmp eq <16 x i64> %vals, zeroinitializer504 call void @llvm.masked.scatter.v16i64(<16 x i64> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask)505 ret void506}507 508define void @masked_scatter_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {509; CHECK-LABEL: masked_scatter_v32i64:510; CHECK: // %bb.0:511; CHECK-NEXT: ptrue p0.d, vl32512; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]513; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]514; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, #0515; CHECK-NEXT: st1d { z0.d }, p1, [z1.d]516; CHECK-NEXT: ret517 %vals = load <32 x i64>, ptr %a518 %ptrs = load <32 x ptr>, ptr %b519 %mask = icmp eq <32 x i64> %vals, zeroinitializer520 call void @llvm.masked.scatter.v32i64(<32 x i64> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)521 ret void522}523 524;525; ST1H (float)526;527 528define void @masked_scatter_v2f16(ptr %a, ptr %b) vscale_range(2,0) #0 {529; CHECK-LABEL: masked_scatter_v2f16:530; CHECK: // %bb.0:531; CHECK-NEXT: ldr s1, [x0]532; CHECK-NEXT: movi v0.2d, #0000000000000000533; CHECK-NEXT: ptrue p0.d, vl4534; CHECK-NEXT: fcmeq v2.4h, v1.4h, #0.0535; CHECK-NEXT: uunpklo z1.s, z1.h536; CHECK-NEXT: sshll v2.4s, v2.4h, #0537; CHECK-NEXT: mov v0.h[0], v2.h[0]538; CHECK-NEXT: mov w8, v2.s[1]539; CHECK-NEXT: mov v0.h[1], w8540; CHECK-NEXT: sunpklo z0.s, z0.h541; CHECK-NEXT: sunpklo z0.d, z0.s542; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0543; CHECK-NEXT: uunpklo z0.d, z1.s544; CHECK-NEXT: ldr q1, [x1]545; CHECK-NEXT: st1h { z0.d }, p0, [z1.d]546; CHECK-NEXT: ret547 %vals = load <2 x half>, ptr %a548 %ptrs = load <2 x ptr>, ptr %b549 %mask = fcmp oeq <2 x half> %vals, zeroinitializer550 call void @llvm.masked.scatter.v2f16(<2 x half> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask)551 ret void552}553 554define void @masked_scatter_v4f16(ptr %a, ptr %b) vscale_range(2,0) #0 {555; CHECK-LABEL: masked_scatter_v4f16:556; CHECK: // %bb.0:557; CHECK-NEXT: ldr d0, [x0]558; CHECK-NEXT: ptrue p0.d, vl4559; CHECK-NEXT: fcmeq v1.4h, v0.4h, #0.0560; CHECK-NEXT: uunpklo z0.s, z0.h561; CHECK-NEXT: sunpklo z1.s, z1.h562; CHECK-NEXT: uunpklo z0.d, z0.s563; CHECK-NEXT: sunpklo z1.d, z1.s564; CHECK-NEXT: cmpne p1.d, p0/z, z1.d, #0565; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]566; CHECK-NEXT: st1h { z0.d }, p1, [z1.d]567; CHECK-NEXT: ret568 %vals = load <4 x half>, ptr %a569 %ptrs = load <4 x ptr>, ptr %b570 %mask = fcmp oeq <4 x half> %vals, zeroinitializer571 call void @llvm.masked.scatter.v4f16(<4 x half> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask)572 ret void573}574 575define void @masked_scatter_v8f16(ptr %a, ptr %b) #0 {576; VBITS_GE_256-LABEL: masked_scatter_v8f16:577; VBITS_GE_256: // %bb.0:578; VBITS_GE_256-NEXT: ldr q0, [x0]579; VBITS_GE_256-NEXT: ptrue p0.d, vl4580; VBITS_GE_256-NEXT: mov x8, #4 // =0x4581; VBITS_GE_256-NEXT: fcmeq v1.8h, v0.8h, #0.0582; VBITS_GE_256-NEXT: uunpklo z3.s, z0.h583; VBITS_GE_256-NEXT: ext v0.16b, v0.16b, v0.16b, #8584; VBITS_GE_256-NEXT: ld1d { z4.d }, p0/z, [x1, x8, lsl #3]585; VBITS_GE_256-NEXT: sunpklo z2.s, z1.h586; VBITS_GE_256-NEXT: ext v1.16b, v1.16b, v1.16b, #8587; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h588; VBITS_GE_256-NEXT: uunpklo z3.d, z3.s589; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h590; VBITS_GE_256-NEXT: sunpklo z2.d, z2.s591; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s592; VBITS_GE_256-NEXT: sunpklo z1.d, z1.s593; VBITS_GE_256-NEXT: cmpne p1.d, p0/z, z2.d, #0594; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x1]595; VBITS_GE_256-NEXT: cmpne p0.d, p0/z, z1.d, #0596; VBITS_GE_256-NEXT: st1h { z3.d }, p1, [z2.d]597; VBITS_GE_256-NEXT: st1h { z0.d }, p0, [z4.d]598; VBITS_GE_256-NEXT: ret599;600; VBITS_GE_512-LABEL: masked_scatter_v8f16:601; VBITS_GE_512: // %bb.0:602; VBITS_GE_512-NEXT: ldr q0, [x0]603; VBITS_GE_512-NEXT: ptrue p0.d, vl8604; VBITS_GE_512-NEXT: fcmeq v1.8h, v0.8h, #0.0605; VBITS_GE_512-NEXT: uunpklo z0.s, z0.h606; VBITS_GE_512-NEXT: sunpklo z1.s, z1.h607; VBITS_GE_512-NEXT: uunpklo z0.d, z0.s608; VBITS_GE_512-NEXT: sunpklo z1.d, z1.s609; VBITS_GE_512-NEXT: cmpne p1.d, p0/z, z1.d, #0610; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]611; VBITS_GE_512-NEXT: st1h { z0.d }, p1, [z1.d]612; VBITS_GE_512-NEXT: ret613 %vals = load <8 x half>, ptr %a614 %ptrs = load <8 x ptr>, ptr %b615 %mask = fcmp oeq <8 x half> %vals, zeroinitializer616 call void @llvm.masked.scatter.v8f16(<8 x half> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask)617 ret void618}619 620define void @masked_scatter_v16f16(ptr %a, ptr %b) vscale_range(8,0) #0 {621; CHECK-LABEL: masked_scatter_v16f16:622; CHECK: // %bb.0:623; CHECK-NEXT: ptrue p0.h, vl16624; CHECK-NEXT: ptrue p1.d, vl16625; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]626; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]627; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0628; CHECK-NEXT: uunpklo z0.s, z0.h629; CHECK-NEXT: uunpklo z0.d, z0.s630; CHECK-NEXT: punpklo p0.h, p0.b631; CHECK-NEXT: punpklo p0.h, p0.b632; CHECK-NEXT: st1h { z0.d }, p0, [z1.d]633; CHECK-NEXT: ret634 %vals = load <16 x half>, ptr %a635 %ptrs = load <16 x ptr>, ptr %b636 %mask = fcmp oeq <16 x half> %vals, zeroinitializer637 call void @llvm.masked.scatter.v16f16(<16 x half> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask)638 ret void639}640 641define void @masked_scatter_v32f16(ptr %a, ptr %b) vscale_range(16,0) #0 {642; CHECK-LABEL: masked_scatter_v32f16:643; CHECK: // %bb.0:644; CHECK-NEXT: ptrue p0.h, vl32645; CHECK-NEXT: ptrue p1.d, vl32646; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]647; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]648; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0649; CHECK-NEXT: uunpklo z0.s, z0.h650; CHECK-NEXT: uunpklo z0.d, z0.s651; CHECK-NEXT: punpklo p0.h, p0.b652; CHECK-NEXT: punpklo p0.h, p0.b653; CHECK-NEXT: st1h { z0.d }, p0, [z1.d]654; CHECK-NEXT: ret655 %vals = load <32 x half>, ptr %a656 %ptrs = load <32 x ptr>, ptr %b657 %mask = fcmp oeq <32 x half> %vals, zeroinitializer658 call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)659 ret void660}661 662;663; ST1W (float)664;665 666define void @masked_scatter_v2f32(ptr %a, ptr %b) vscale_range(2,0) #0 {667; CHECK-LABEL: masked_scatter_v2f32:668; CHECK: // %bb.0:669; CHECK-NEXT: ldr d0, [x0]670; CHECK-NEXT: ptrue p0.d, vl2671; CHECK-NEXT: fcmeq v1.2s, v0.2s, #0.0672; CHECK-NEXT: ushll v0.2d, v0.2s, #0673; CHECK-NEXT: sshll v1.2d, v1.2s, #0674; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0675; CHECK-NEXT: ldr q1, [x1]676; CHECK-NEXT: st1w { z0.d }, p0, [z1.d]677; CHECK-NEXT: ret678 %vals = load <2 x float>, ptr %a679 %ptrs = load <2 x ptr>, ptr %b680 %mask = fcmp oeq <2 x float> %vals, zeroinitializer681 call void @llvm.masked.scatter.v2f32(<2 x float> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask)682 ret void683}684 685define void @masked_scatter_v4f32(ptr %a, ptr %b) vscale_range(2,0) #0 {686; CHECK-LABEL: masked_scatter_v4f32:687; CHECK: // %bb.0:688; CHECK-NEXT: ldr q0, [x0]689; CHECK-NEXT: ptrue p0.d, vl4690; CHECK-NEXT: fcmeq v1.4s, v0.4s, #0.0691; CHECK-NEXT: uunpklo z0.d, z0.s692; CHECK-NEXT: sunpklo z1.d, z1.s693; CHECK-NEXT: cmpne p1.d, p0/z, z1.d, #0694; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]695; CHECK-NEXT: st1w { z0.d }, p1, [z1.d]696; CHECK-NEXT: ret697 %vals = load <4 x float>, ptr %a698 %ptrs = load <4 x ptr>, ptr %b699 %mask = fcmp oeq <4 x float> %vals, zeroinitializer700 call void @llvm.masked.scatter.v4f32(<4 x float> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask)701 ret void702}703 704define void @masked_scatter_v8f32(ptr %a, ptr %b) #0 {705; VBITS_GE_256-LABEL: masked_scatter_v8f32:706; VBITS_GE_256: // %bb.0:707; VBITS_GE_256-NEXT: ptrue p0.s, vl8708; VBITS_GE_256-NEXT: mov x8, #4 // =0x4709; VBITS_GE_256-NEXT: ptrue p1.d, vl4710; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0]711; VBITS_GE_256-NEXT: ld1d { z3.d }, p1/z, [x1]712; VBITS_GE_256-NEXT: ld1d { z4.d }, p1/z, [x1, x8, lsl #3]713; VBITS_GE_256-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0714; VBITS_GE_256-NEXT: uunpklo z2.d, z0.s715; VBITS_GE_256-NEXT: ext z0.b, z0.b, z0.b, #16716; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s717; VBITS_GE_256-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff718; VBITS_GE_256-NEXT: punpklo p0.h, p0.b719; VBITS_GE_256-NEXT: and p0.b, p0/z, p0.b, p1.b720; VBITS_GE_256-NEXT: ext z1.b, z1.b, z1.b, #16721; VBITS_GE_256-NEXT: st1w { z2.d }, p0, [z3.d]722; VBITS_GE_256-NEXT: sunpklo z1.d, z1.s723; VBITS_GE_256-NEXT: cmpne p0.d, p1/z, z1.d, #0724; VBITS_GE_256-NEXT: st1w { z0.d }, p0, [z4.d]725; VBITS_GE_256-NEXT: ret726;727; VBITS_GE_512-LABEL: masked_scatter_v8f32:728; VBITS_GE_512: // %bb.0:729; VBITS_GE_512-NEXT: ptrue p0.s, vl8730; VBITS_GE_512-NEXT: ptrue p1.d, vl8731; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]732; VBITS_GE_512-NEXT: ld1d { z1.d }, p1/z, [x1]733; VBITS_GE_512-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0734; VBITS_GE_512-NEXT: uunpklo z0.d, z0.s735; VBITS_GE_512-NEXT: punpklo p0.h, p0.b736; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [z1.d]737; VBITS_GE_512-NEXT: ret738 %vals = load <8 x float>, ptr %a739 %ptrs = load <8 x ptr>, ptr %b740 %mask = fcmp oeq <8 x float> %vals, zeroinitializer741 call void @llvm.masked.scatter.v8f32(<8 x float> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask)742 ret void743}744 745define void @masked_scatter_v16f32(ptr %a, ptr %b) vscale_range(8,0) #0 {746; CHECK-LABEL: masked_scatter_v16f32:747; CHECK: // %bb.0:748; CHECK-NEXT: ptrue p0.s, vl16749; CHECK-NEXT: ptrue p1.d, vl16750; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]751; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]752; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0753; CHECK-NEXT: uunpklo z0.d, z0.s754; CHECK-NEXT: punpklo p0.h, p0.b755; CHECK-NEXT: st1w { z0.d }, p0, [z1.d]756; CHECK-NEXT: ret757 %vals = load <16 x float>, ptr %a758 %ptrs = load <16 x ptr>, ptr %b759 %mask = fcmp oeq <16 x float> %vals, zeroinitializer760 call void @llvm.masked.scatter.v16f32(<16 x float> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask)761 ret void762}763 764define void @masked_scatter_v32f32(ptr %a, ptr %b) vscale_range(16,0) #0 {765; CHECK-LABEL: masked_scatter_v32f32:766; CHECK: // %bb.0:767; CHECK-NEXT: ptrue p0.s, vl32768; CHECK-NEXT: ptrue p1.d, vl32769; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]770; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]771; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0772; CHECK-NEXT: uunpklo z0.d, z0.s773; CHECK-NEXT: punpklo p0.h, p0.b774; CHECK-NEXT: st1w { z0.d }, p0, [z1.d]775; CHECK-NEXT: ret776 %vals = load <32 x float>, ptr %a777 %ptrs = load <32 x ptr>, ptr %b778 %mask = fcmp oeq <32 x float> %vals, zeroinitializer779 call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)780 ret void781}782 783;784; ST1D (float)785;786 787; Scalarize 1 x double scatters788define void @masked_scatter_v1f64(ptr %a, ptr %b) vscale_range(8,0) #0 {789; CHECK-LABEL: masked_scatter_v1f64:790; CHECK: // %bb.0:791; CHECK-NEXT: ldr d0, [x0]792; CHECK-NEXT: fcmp d0, #0.0793; CHECK-NEXT: b.ne .LBB31_2794; CHECK-NEXT: // %bb.1: // %cond.store795; CHECK-NEXT: ldr d1, [x1]796; CHECK-NEXT: fmov x8, d1797; CHECK-NEXT: str d0, [x8]798; CHECK-NEXT: .LBB31_2: // %else799; CHECK-NEXT: ret800 %vals = load <1 x double>, ptr %a801 %ptrs = load <1 x ptr>, ptr %b802 %mask = fcmp oeq <1 x double> %vals, zeroinitializer803 call void @llvm.masked.scatter.v1f64(<1 x double> %vals, <1 x ptr> %ptrs, i32 8, <1 x i1> %mask)804 ret void805}806 807define void @masked_scatter_v2f64(ptr %a, ptr %b) vscale_range(2,0) #0 {808; CHECK-LABEL: masked_scatter_v2f64:809; CHECK: // %bb.0:810; CHECK-NEXT: ldr q0, [x0]811; CHECK-NEXT: ptrue p0.d, vl2812; CHECK-NEXT: fcmeq v1.2d, v0.2d, #0.0813; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0814; CHECK-NEXT: ldr q1, [x1]815; CHECK-NEXT: st1d { z0.d }, p0, [z1.d]816; CHECK-NEXT: ret817 %vals = load <2 x double>, ptr %a818 %ptrs = load <2 x ptr>, ptr %b819 %mask = fcmp oeq <2 x double> %vals, zeroinitializer820 call void @llvm.masked.scatter.v2f64(<2 x double> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask)821 ret void822}823 824define void @masked_scatter_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {825; CHECK-LABEL: masked_scatter_v4f64:826; CHECK: // %bb.0:827; CHECK-NEXT: ptrue p0.d, vl4828; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]829; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]830; CHECK-NEXT: fcmeq p1.d, p0/z, z0.d, #0.0831; CHECK-NEXT: st1d { z0.d }, p1, [z1.d]832; CHECK-NEXT: ret833 %vals = load <4 x double>, ptr %a834 %ptrs = load <4 x ptr>, ptr %b835 %mask = fcmp oeq <4 x double> %vals, zeroinitializer836 call void @llvm.masked.scatter.v4f64(<4 x double> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask)837 ret void838}839 840define void @masked_scatter_v8f64(ptr %a, ptr %b) #0 {841; VBITS_GE_256-LABEL: masked_scatter_v8f64:842; VBITS_GE_256: // %bb.0:843; VBITS_GE_256-NEXT: ptrue p0.d, vl4844; VBITS_GE_256-NEXT: mov x8, #4 // =0x4845; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0]846; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0, x8, lsl #3]847; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1]848; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1, x8, lsl #3]849; VBITS_GE_256-NEXT: fcmeq p1.d, p0/z, z0.d, #0.0850; VBITS_GE_256-NEXT: fcmeq p0.d, p0/z, z2.d, #0.0851; VBITS_GE_256-NEXT: st1d { z0.d }, p1, [z1.d]852; VBITS_GE_256-NEXT: st1d { z2.d }, p0, [z3.d]853; VBITS_GE_256-NEXT: ret854;855; VBITS_GE_512-LABEL: masked_scatter_v8f64:856; VBITS_GE_512: // %bb.0:857; VBITS_GE_512-NEXT: ptrue p0.d, vl8858; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]859; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]860; VBITS_GE_512-NEXT: fcmeq p1.d, p0/z, z0.d, #0.0861; VBITS_GE_512-NEXT: st1d { z0.d }, p1, [z1.d]862; VBITS_GE_512-NEXT: ret863 %vals = load <8 x double>, ptr %a864 %ptrs = load <8 x ptr>, ptr %b865 %mask = fcmp oeq <8 x double> %vals, zeroinitializer866 call void @llvm.masked.scatter.v8f64(<8 x double> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask)867 ret void868}869 870define void @masked_scatter_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {871; CHECK-LABEL: masked_scatter_v16f64:872; CHECK: // %bb.0:873; CHECK-NEXT: ptrue p0.d, vl16874; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]875; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]876; CHECK-NEXT: fcmeq p1.d, p0/z, z0.d, #0.0877; CHECK-NEXT: st1d { z0.d }, p1, [z1.d]878; CHECK-NEXT: ret879 %vals = load <16 x double>, ptr %a880 %ptrs = load <16 x ptr>, ptr %b881 %mask = fcmp oeq <16 x double> %vals, zeroinitializer882 call void @llvm.masked.scatter.v16f64(<16 x double> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask)883 ret void884}885 886define void @masked_scatter_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {887; CHECK-LABEL: masked_scatter_v32f64:888; CHECK: // %bb.0:889; CHECK-NEXT: ptrue p0.d, vl32890; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]891; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]892; CHECK-NEXT: fcmeq p1.d, p0/z, z0.d, #0.0893; CHECK-NEXT: st1d { z0.d }, p1, [z1.d]894; CHECK-NEXT: ret895 %vals = load <32 x double>, ptr %a896 %ptrs = load <32 x ptr>, ptr %b897 %mask = fcmp oeq <32 x double> %vals, zeroinitializer898 call void @llvm.masked.scatter.v32f64(<32 x double> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)899 ret void900}901 902; The above tests test the types, the below tests check that the addressing903; modes still function904 905define void @masked_scatter_32b_scaled_sext_f16(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 {906; CHECK-LABEL: masked_scatter_32b_scaled_sext_f16:907; CHECK: // %bb.0:908; CHECK-NEXT: ptrue p0.h, vl32909; CHECK-NEXT: ptrue p1.s, vl32910; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]911; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]912; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0913; CHECK-NEXT: uunpklo z0.s, z0.h914; CHECK-NEXT: punpklo p0.h, p0.b915; CHECK-NEXT: st1h { z0.s }, p0, [x2, z1.s, sxtw #1]916; CHECK-NEXT: ret917 %vals = load <32 x half>, ptr %a918 %idxs = load <32 x i32>, ptr %b919 %ext = sext <32 x i32> %idxs to <32 x i64>920 %ptrs = getelementptr half, ptr %base, <32 x i64> %ext921 %mask = fcmp oeq <32 x half> %vals, zeroinitializer922 call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)923 ret void924}925 926define void @masked_scatter_32b_scaled_sext_f32(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 {927; CHECK-LABEL: masked_scatter_32b_scaled_sext_f32:928; CHECK: // %bb.0:929; CHECK-NEXT: ptrue p0.s, vl32930; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]931; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]932; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, #0.0933; CHECK-NEXT: st1w { z0.s }, p1, [x2, z1.s, sxtw #2]934; CHECK-NEXT: ret935 %vals = load <32 x float>, ptr %a936 %idxs = load <32 x i32>, ptr %b937 %ext = sext <32 x i32> %idxs to <32 x i64>938 %ptrs = getelementptr float, ptr %base, <32 x i64> %ext939 %mask = fcmp oeq <32 x float> %vals, zeroinitializer940 call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)941 ret void942}943 944define void @masked_scatter_32b_scaled_sext_f64(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 {945; CHECK-LABEL: masked_scatter_32b_scaled_sext_f64:946; CHECK: // %bb.0:947; CHECK-NEXT: ptrue p0.d, vl32948; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]949; CHECK-NEXT: ld1sw { z1.d }, p0/z, [x1]950; CHECK-NEXT: fcmeq p1.d, p0/z, z0.d, #0.0951; CHECK-NEXT: st1d { z0.d }, p1, [x2, z1.d, lsl #3]952; CHECK-NEXT: ret953 %vals = load <32 x double>, ptr %a954 %idxs = load <32 x i32>, ptr %b955 %ext = sext <32 x i32> %idxs to <32 x i64>956 %ptrs = getelementptr double, ptr %base, <32 x i64> %ext957 %mask = fcmp oeq <32 x double> %vals, zeroinitializer958 call void @llvm.masked.scatter.v32f64(<32 x double> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)959 ret void960}961 962define void @masked_scatter_32b_scaled_zext(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 {963; CHECK-LABEL: masked_scatter_32b_scaled_zext:964; CHECK: // %bb.0:965; CHECK-NEXT: ptrue p0.h, vl32966; CHECK-NEXT: ptrue p1.s, vl32967; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]968; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]969; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0970; CHECK-NEXT: uunpklo z0.s, z0.h971; CHECK-NEXT: punpklo p0.h, p0.b972; CHECK-NEXT: st1h { z0.s }, p0, [x2, z1.s, uxtw #1]973; CHECK-NEXT: ret974 %vals = load <32 x half>, ptr %a975 %idxs = load <32 x i32>, ptr %b976 %ext = zext <32 x i32> %idxs to <32 x i64>977 %ptrs = getelementptr half, ptr %base, <32 x i64> %ext978 %mask = fcmp oeq <32 x half> %vals, zeroinitializer979 call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)980 ret void981}982 983define void @masked_scatter_32b_unscaled_sext(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 {984; CHECK-LABEL: masked_scatter_32b_unscaled_sext:985; CHECK: // %bb.0:986; CHECK-NEXT: ptrue p0.h, vl32987; CHECK-NEXT: ptrue p1.s, vl32988; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]989; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]990; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0991; CHECK-NEXT: uunpklo z0.s, z0.h992; CHECK-NEXT: punpklo p0.h, p0.b993; CHECK-NEXT: st1h { z0.s }, p0, [x2, z1.s, sxtw]994; CHECK-NEXT: ret995 %vals = load <32 x half>, ptr %a996 %idxs = load <32 x i32>, ptr %b997 %ext = sext <32 x i32> %idxs to <32 x i64>998 %byte_ptrs = getelementptr i8, ptr %base, <32 x i64> %ext999 %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr>1000 %mask = fcmp oeq <32 x half> %vals, zeroinitializer1001 call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)1002 ret void1003}1004 1005define void @masked_scatter_32b_unscaled_zext(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 {1006; CHECK-LABEL: masked_scatter_32b_unscaled_zext:1007; CHECK: // %bb.0:1008; CHECK-NEXT: ptrue p0.h, vl321009; CHECK-NEXT: ptrue p1.s, vl321010; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]1011; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]1012; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.01013; CHECK-NEXT: uunpklo z0.s, z0.h1014; CHECK-NEXT: punpklo p0.h, p0.b1015; CHECK-NEXT: st1h { z0.s }, p0, [x2, z1.s, uxtw]1016; CHECK-NEXT: ret1017 %vals = load <32 x half>, ptr %a1018 %idxs = load <32 x i32>, ptr %b1019 %ext = zext <32 x i32> %idxs to <32 x i64>1020 %byte_ptrs = getelementptr i8, ptr %base, <32 x i64> %ext1021 %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr>1022 %mask = fcmp oeq <32 x half> %vals, zeroinitializer1023 call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)1024 ret void1025}1026 1027define void @masked_scatter_64b_scaled(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 {1028; CHECK-LABEL: masked_scatter_64b_scaled:1029; CHECK: // %bb.0:1030; CHECK-NEXT: ptrue p0.s, vl321031; CHECK-NEXT: ptrue p1.d, vl321032; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1033; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]1034; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.01035; CHECK-NEXT: uunpklo z0.d, z0.s1036; CHECK-NEXT: punpklo p0.h, p0.b1037; CHECK-NEXT: st1w { z0.d }, p0, [x2, z1.d, lsl #2]1038; CHECK-NEXT: ret1039 %vals = load <32 x float>, ptr %a1040 %idxs = load <32 x i64>, ptr %b1041 %ptrs = getelementptr float, ptr %base, <32 x i64> %idxs1042 %mask = fcmp oeq <32 x float> %vals, zeroinitializer1043 call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)1044 ret void1045}1046 1047define void @masked_scatter_64b_unscaled(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 {1048; CHECK-LABEL: masked_scatter_64b_unscaled:1049; CHECK: // %bb.0:1050; CHECK-NEXT: ptrue p0.s, vl321051; CHECK-NEXT: ptrue p1.d, vl321052; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1053; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]1054; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.01055; CHECK-NEXT: uunpklo z0.d, z0.s1056; CHECK-NEXT: punpklo p0.h, p0.b1057; CHECK-NEXT: st1w { z0.d }, p0, [x2, z1.d]1058; CHECK-NEXT: ret1059 %vals = load <32 x float>, ptr %a1060 %idxs = load <32 x i64>, ptr %b1061 %byte_ptrs = getelementptr i8, ptr %base, <32 x i64> %idxs1062 %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr>1063 %mask = fcmp oeq <32 x float> %vals, zeroinitializer1064 call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)1065 ret void1066}1067 1068define void @masked_scatter_vec_plus_reg(ptr %a, ptr %b, i64 %off) vscale_range(16,0) #0 {1069; CHECK-LABEL: masked_scatter_vec_plus_reg:1070; CHECK: // %bb.0:1071; CHECK-NEXT: ptrue p0.s, vl321072; CHECK-NEXT: ptrue p1.d, vl321073; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1074; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]1075; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.01076; CHECK-NEXT: uunpklo z0.d, z0.s1077; CHECK-NEXT: punpklo p0.h, p0.b1078; CHECK-NEXT: st1w { z0.d }, p0, [x2, z1.d]1079; CHECK-NEXT: ret1080 %vals = load <32 x float>, ptr %a1081 %bases = load <32 x ptr>, ptr %b1082 %byte_ptrs = getelementptr i8, <32 x ptr> %bases, i64 %off1083 %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr>1084 %mask = fcmp oeq <32 x float> %vals, zeroinitializer1085 call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)1086 ret void1087}1088 1089define void @masked_scatter_vec_plus_imm(ptr %a, ptr %b) vscale_range(16,0) #0 {1090; CHECK-LABEL: masked_scatter_vec_plus_imm:1091; CHECK: // %bb.0:1092; CHECK-NEXT: ptrue p0.s, vl321093; CHECK-NEXT: ptrue p1.d, vl321094; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]1095; CHECK-NEXT: ld1d { z1.d }, p1/z, [x1]1096; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.01097; CHECK-NEXT: uunpklo z0.d, z0.s1098; CHECK-NEXT: punpklo p0.h, p0.b1099; CHECK-NEXT: st1w { z0.d }, p0, [z1.d, #4]1100; CHECK-NEXT: ret1101 %vals = load <32 x float>, ptr %a1102 %bases = load <32 x ptr>, ptr %b1103 %byte_ptrs = getelementptr i8, <32 x ptr> %bases, i64 41104 %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr>1105 %mask = fcmp oeq <32 x float> %vals, zeroinitializer1106 call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask)1107 ret void1108}1109 1110; extract_subvec(...(insert_subvec(a,b,c))) -> extract_subvec(bitcast(b),d) like1111; combines can effectively unlegalise bitcast operations. This test ensures such1112; combines do not happen after operation legalisation. When not prevented the1113; test triggers infinite combine->legalise->combine->...1114;1115; NOTE: For this test to function correctly it's critical for %vals to be in a1116; different block to the scatter store. If not, the problematic bitcast will be1117; removed before operation legalisation and thus not exercise the combine.1118define void @masked_scatter_bitcast_infinite_loop(ptr %a, ptr %b, i1 %cond) vscale_range(4,0) #0 {1119; CHECK-LABEL: masked_scatter_bitcast_infinite_loop:1120; CHECK: // %bb.0:1121; CHECK-NEXT: ptrue p0.d, vl81122; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]1123; CHECK-NEXT: tbz w2, #0, .LBB47_21124; CHECK-NEXT: // %bb.1: // %bb.11125; CHECK-NEXT: fcmeq p1.d, p0/z, z0.d, #0.01126; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]1127; CHECK-NEXT: st1d { z0.d }, p1, [z1.d]1128; CHECK-NEXT: .LBB47_2: // %bb.21129; CHECK-NEXT: ret1130 %vals = load volatile <8 x double>, ptr %a1131 br i1 %cond, label %bb.1, label %bb.21132 1133bb.1:1134 %ptrs = load <8 x ptr>, ptr %b1135 %mask = fcmp oeq <8 x double> %vals, zeroinitializer1136 call void @llvm.masked.scatter.v8f64(<8 x double> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask)1137 br label %bb.21138 1139bb.2:1140 ret void1141}1142 1143declare void @llvm.masked.scatter.v2i8(<2 x i8>, <2 x ptr>, i32, <2 x i1>)1144declare void @llvm.masked.scatter.v4i8(<4 x i8>, <4 x ptr>, i32, <4 x i1>)1145declare void @llvm.masked.scatter.v8i8(<8 x i8>, <8 x ptr>, i32, <8 x i1>)1146declare void @llvm.masked.scatter.v16i8(<16 x i8>, <16 x ptr>, i32, <16 x i1>)1147declare void @llvm.masked.scatter.v32i8(<32 x i8>, <32 x ptr>, i32, <32 x i1>)1148 1149declare void @llvm.masked.scatter.v2i16(<2 x i16>, <2 x ptr>, i32, <2 x i1>)1150declare void @llvm.masked.scatter.v4i16(<4 x i16>, <4 x ptr>, i32, <4 x i1>)1151declare void @llvm.masked.scatter.v8i16(<8 x i16>, <8 x ptr>, i32, <8 x i1>)1152declare void @llvm.masked.scatter.v16i16(<16 x i16>, <16 x ptr>, i32, <16 x i1>)1153declare void @llvm.masked.scatter.v32i16(<32 x i16>, <32 x ptr>, i32, <32 x i1>)1154 1155declare void @llvm.masked.scatter.v2i32(<2 x i32>, <2 x ptr>, i32, <2 x i1>)1156declare void @llvm.masked.scatter.v4i32(<4 x i32>, <4 x ptr>, i32, <4 x i1>)1157declare void @llvm.masked.scatter.v8i32(<8 x i32>, <8 x ptr>, i32, <8 x i1>)1158declare void @llvm.masked.scatter.v16i32(<16 x i32>, <16 x ptr>, i32, <16 x i1>)1159declare void @llvm.masked.scatter.v32i32(<32 x i32>, <32 x ptr>, i32, <32 x i1>)1160 1161declare void @llvm.masked.scatter.v1i64(<1 x i64>, <1 x ptr>, i32, <1 x i1>)1162declare void @llvm.masked.scatter.v2i64(<2 x i64>, <2 x ptr>, i32, <2 x i1>)1163declare void @llvm.masked.scatter.v4i64(<4 x i64>, <4 x ptr>, i32, <4 x i1>)1164declare void @llvm.masked.scatter.v8i64(<8 x i64>, <8 x ptr>, i32, <8 x i1>)1165declare void @llvm.masked.scatter.v16i64(<16 x i64>, <16 x ptr>, i32, <16 x i1>)1166declare void @llvm.masked.scatter.v32i64(<32 x i64>, <32 x ptr>, i32, <32 x i1>)1167 1168declare void @llvm.masked.scatter.v2f16(<2 x half>, <2 x ptr>, i32, <2 x i1>)1169declare void @llvm.masked.scatter.v4f16(<4 x half>, <4 x ptr>, i32, <4 x i1>)1170declare void @llvm.masked.scatter.v8f16(<8 x half>, <8 x ptr>, i32, <8 x i1>)1171declare void @llvm.masked.scatter.v16f16(<16 x half>, <16 x ptr>, i32, <16 x i1>)1172declare void @llvm.masked.scatter.v32f16(<32 x half>, <32 x ptr>, i32, <32 x i1>)1173 1174declare void @llvm.masked.scatter.v2f32(<2 x float>, <2 x ptr>, i32, <2 x i1>)1175declare void @llvm.masked.scatter.v4f32(<4 x float>, <4 x ptr>, i32, <4 x i1>)1176declare void @llvm.masked.scatter.v8f32(<8 x float>, <8 x ptr>, i32, <8 x i1>)1177declare void @llvm.masked.scatter.v16f32(<16 x float>, <16 x ptr>, i32, <16 x i1>)1178declare void @llvm.masked.scatter.v32f32(<32 x float>, <32 x ptr>, i32, <32 x i1>)1179 1180declare void @llvm.masked.scatter.v1f64(<1 x double>, <1 x ptr>, i32, <1 x i1>)1181declare void @llvm.masked.scatter.v2f64(<2 x double>, <2 x ptr>, i32, <2 x i1>)1182declare void @llvm.masked.scatter.v4f64(<4 x double>, <4 x ptr>, i32, <4 x i1>)1183declare void @llvm.masked.scatter.v8f64(<8 x double>, <8 x ptr>, i32, <8 x i1>)1184declare void @llvm.masked.scatter.v16f64(<16 x double>, <16 x ptr>, i32, <16 x i1>)1185declare void @llvm.masked.scatter.v32f64(<32 x double>, <32 x ptr>, i32, <32 x i1>)1186 1187attributes #0 = { "target-features"="+sve" }1188