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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; Masked Stores10;11 12define void @masked_store_v2f16(ptr %ap, ptr %bp) vscale_range(2,0) #0 {13; CHECK-LABEL: masked_store_v2f16:14; CHECK: // %bb.0:15; CHECK-NEXT: ldr s1, [x0]16; CHECK-NEXT: ldr s2, [x1]17; CHECK-NEXT: movi v0.2d, #000000000000000018; CHECK-NEXT: ptrue p0.h, vl419; CHECK-NEXT: fcmeq v2.4h, v1.4h, v2.4h20; CHECK-NEXT: sshll v2.4s, v2.4h, #021; CHECK-NEXT: mov v0.h[0], v2.h[0]22; CHECK-NEXT: mov w8, v2.s[1]23; CHECK-NEXT: mov v0.h[1], w824; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #025; CHECK-NEXT: st1h { z1.h }, p0, [x1]26; CHECK-NEXT: ret27 %a = load <2 x half>, ptr %ap28 %b = load <2 x half>, ptr %bp29 %mask = fcmp oeq <2 x half> %a, %b30 call void @llvm.masked.store.v2f16(<2 x half> %a, ptr %bp, i32 8, <2 x i1> %mask)31 ret void32}33 34define void @masked_store_v2f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {35; CHECK-LABEL: masked_store_v2f32:36; CHECK: // %bb.0:37; CHECK-NEXT: ldr d0, [x0]38; CHECK-NEXT: ldr d1, [x1]39; CHECK-NEXT: ptrue p0.s, vl240; CHECK-NEXT: fcmeq v1.2s, v0.2s, v1.2s41; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, #042; CHECK-NEXT: st1w { z0.s }, p0, [x1]43; CHECK-NEXT: ret44 %a = load <2 x float>, ptr %ap45 %b = load <2 x float>, ptr %bp46 %mask = fcmp oeq <2 x float> %a, %b47 call void @llvm.masked.store.v2f32(<2 x float> %a, ptr %bp, i32 8, <2 x i1> %mask)48 ret void49}50 51define void @masked_store_v4f32(ptr %ap, ptr %bp) vscale_range(1,0) #0 {52; CHECK-LABEL: masked_store_v4f32:53; CHECK: // %bb.0:54; CHECK-NEXT: ldr q0, [x0]55; CHECK-NEXT: ldr q1, [x1]56; CHECK-NEXT: ptrue p0.s, vl457; CHECK-NEXT: fcmeq v1.4s, v0.4s, v1.4s58; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, #059; CHECK-NEXT: st1w { z0.s }, p0, [x1]60; CHECK-NEXT: ret61 %a = load <4 x float>, ptr %ap62 %b = load <4 x float>, ptr %bp63 %mask = fcmp oeq <4 x float> %a, %b64 call void @llvm.masked.store.v4f32(<4 x float> %a, ptr %bp, i32 8, <4 x i1> %mask)65 ret void66}67 68define void @masked_store_v8f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {69; CHECK-LABEL: masked_store_v8f32:70; CHECK: // %bb.0:71; CHECK-NEXT: ptrue p0.s, vl872; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]73; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]74; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s75; CHECK-NEXT: st1w { z0.s }, p0, [x1]76; CHECK-NEXT: ret77 %a = load <8 x float>, ptr %ap78 %b = load <8 x float>, ptr %bp79 %mask = fcmp oeq <8 x float> %a, %b80 call void @llvm.masked.store.v8f32(<8 x float> %a, ptr %bp, i32 8, <8 x i1> %mask)81 ret void82}83 84define void @masked_store_v16f32(ptr %ap, ptr %bp) #0 {85; VBITS_GE_256-LABEL: masked_store_v16f32:86; VBITS_GE_256: // %bb.0:87; VBITS_GE_256-NEXT: ptrue p0.s, vl888; VBITS_GE_256-NEXT: mov x8, #8 // =0x889; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]90; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]91; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]92; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]93; VBITS_GE_256-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s94; VBITS_GE_256-NEXT: fcmeq p0.s, p0/z, z2.s, z3.s95; VBITS_GE_256-NEXT: st1w { z0.s }, p1, [x0, x8, lsl #2]96; VBITS_GE_256-NEXT: st1w { z2.s }, p0, [x0]97; VBITS_GE_256-NEXT: ret98;99; VBITS_GE_512-LABEL: masked_store_v16f32:100; VBITS_GE_512: // %bb.0:101; VBITS_GE_512-NEXT: ptrue p0.s, vl16102; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]103; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]104; VBITS_GE_512-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s105; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]106; VBITS_GE_512-NEXT: ret107 %a = load <16 x float>, ptr %ap108 %b = load <16 x float>, ptr %bp109 %mask = fcmp oeq <16 x float> %a, %b110 call void @llvm.masked.store.v16f32(<16 x float> %a, ptr %ap, i32 8, <16 x i1> %mask)111 ret void112}113 114define void @masked_store_v32f32(ptr %ap, ptr %bp) vscale_range(8,0) #0 {115; CHECK-LABEL: masked_store_v32f32:116; CHECK: // %bb.0:117; CHECK-NEXT: ptrue p0.s, vl32118; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]119; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]120; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s121; CHECK-NEXT: st1w { z0.s }, p0, [x0]122; CHECK-NEXT: ret123 %a = load <32 x float>, ptr %ap124 %b = load <32 x float>, ptr %bp125 %mask = fcmp oeq <32 x float> %a, %b126 call void @llvm.masked.store.v32f32(<32 x float> %a, ptr %ap, i32 8, <32 x i1> %mask)127 ret void128}129 130define void @masked_store_v64f32(ptr %ap, ptr %bp) vscale_range(16,0) #0 {131; CHECK-LABEL: masked_store_v64f32:132; CHECK: // %bb.0:133; CHECK-NEXT: ptrue p0.s, vl64134; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]135; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]136; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s137; CHECK-NEXT: st1w { z0.s }, p0, [x0]138; CHECK-NEXT: ret139 %a = load <64 x float>, ptr %ap140 %b = load <64 x float>, ptr %bp141 %mask = fcmp oeq <64 x float> %a, %b142 call void @llvm.masked.store.v64f32(<64 x float> %a, ptr %ap, i32 8, <64 x i1> %mask)143 ret void144}145 146define void @masked_store_trunc_v8i64i8(ptr %ap, ptr %bp, ptr %dest) #0 {147; VBITS_GE_256-LABEL: masked_store_trunc_v8i64i8:148; VBITS_GE_256: // %bb.0:149; VBITS_GE_256-NEXT: ptrue p0.d, vl4150; VBITS_GE_256-NEXT: mov x8, #4 // =0x4151; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]152; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]153; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x1, x8, lsl #3]154; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]155; VBITS_GE_256-NEXT: cmpeq p1.d, p0/z, z0.d, z2.d156; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s157; VBITS_GE_256-NEXT: cmpeq p0.d, p0/z, z1.d, z3.d158; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s159; VBITS_GE_256-NEXT: mov z2.d, p1/z, #-1 // =0xffffffffffffffff160; VBITS_GE_256-NEXT: ptrue p1.s, vl8161; VBITS_GE_256-NEXT: mov z3.d, p0/z, #-1 // =0xffffffffffffffff162; VBITS_GE_256-NEXT: ptrue p0.s, vl4163; VBITS_GE_256-NEXT: uzp1 z2.s, z2.s, z2.s164; VBITS_GE_256-NEXT: splice z1.s, p0, z1.s, z0.s165; VBITS_GE_256-NEXT: uzp1 z3.s, z3.s, z3.s166; VBITS_GE_256-NEXT: splice z3.s, p0, z3.s, z2.s167; VBITS_GE_256-NEXT: cmpne p1.s, p1/z, z3.s, #0168; VBITS_GE_256-NEXT: st1b { z1.s }, p1, [x2]169; VBITS_GE_256-NEXT: ret170;171; VBITS_GE_512-LABEL: masked_store_trunc_v8i64i8:172; VBITS_GE_512: // %bb.0:173; VBITS_GE_512-NEXT: ptrue p0.d, vl8174; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]175; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]176; VBITS_GE_512-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d177; VBITS_GE_512-NEXT: st1b { z0.d }, p0, [x2]178; VBITS_GE_512-NEXT: ret179 %a = load <8 x i64>, ptr %ap180 %b = load <8 x i64>, ptr %bp181 %mask = icmp eq <8 x i64> %a, %b182 %val = trunc <8 x i64> %a to <8 x i8>183 call void @llvm.masked.store.v8i8(<8 x i8> %val, ptr %dest, i32 8, <8 x i1> %mask)184 ret void185}186 187define void @masked_store_trunc_v8i64i16(ptr %ap, ptr %bp, ptr %dest) #0 {188; VBITS_GE_256-LABEL: masked_store_trunc_v8i64i16:189; VBITS_GE_256: // %bb.0:190; VBITS_GE_256-NEXT: ptrue p0.d, vl4191; VBITS_GE_256-NEXT: mov x8, #4 // =0x4192; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]193; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]194; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x1, x8, lsl #3]195; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]196; VBITS_GE_256-NEXT: cmpeq p1.d, p0/z, z0.d, z2.d197; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s198; VBITS_GE_256-NEXT: cmpeq p0.d, p0/z, z1.d, z3.d199; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s200; VBITS_GE_256-NEXT: uzp1 z0.h, z0.h, z0.h201; VBITS_GE_256-NEXT: mov z2.d, p1/z, #-1 // =0xffffffffffffffff202; VBITS_GE_256-NEXT: uzp1 z1.h, z1.h, z1.h203; VBITS_GE_256-NEXT: mov z3.d, p0/z, #-1 // =0xffffffffffffffff204; VBITS_GE_256-NEXT: ptrue p0.s, vl4205; VBITS_GE_256-NEXT: uzp1 z2.s, z2.s, z2.s206; VBITS_GE_256-NEXT: mov v1.d[1], v0.d[0]207; VBITS_GE_256-NEXT: uzp1 z3.s, z3.s, z3.s208; VBITS_GE_256-NEXT: splice z3.s, p0, z3.s, z2.s209; VBITS_GE_256-NEXT: ptrue p0.h, vl8210; VBITS_GE_256-NEXT: uzp1 z2.h, z3.h, z3.h211; VBITS_GE_256-NEXT: cmpne p0.h, p0/z, z2.h, #0212; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x2]213; VBITS_GE_256-NEXT: ret214;215; VBITS_GE_512-LABEL: masked_store_trunc_v8i64i16:216; VBITS_GE_512: // %bb.0:217; VBITS_GE_512-NEXT: ptrue p0.d, vl8218; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]219; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]220; VBITS_GE_512-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d221; VBITS_GE_512-NEXT: st1h { z0.d }, p0, [x2]222; VBITS_GE_512-NEXT: ret223 %a = load <8 x i64>, ptr %ap224 %b = load <8 x i64>, ptr %bp225 %mask = icmp eq <8 x i64> %a, %b226 %val = trunc <8 x i64> %a to <8 x i16>227 call void @llvm.masked.store.v8i16(<8 x i16> %val, ptr %dest, i32 8, <8 x i1> %mask)228 ret void229}230 231define void @masked_store_trunc_v8i64i32(ptr %ap, ptr %bp, ptr %dest) #0 {232; VBITS_GE_256-LABEL: masked_store_trunc_v8i64i32:233; VBITS_GE_256: // %bb.0:234; VBITS_GE_256-NEXT: ptrue p0.d, vl4235; VBITS_GE_256-NEXT: mov x8, #4 // =0x4236; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]237; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]238; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x1, x8, lsl #3]239; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]240; VBITS_GE_256-NEXT: cmpeq p1.d, p0/z, z0.d, z2.d241; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s242; VBITS_GE_256-NEXT: cmpeq p0.d, p0/z, z1.d, z3.d243; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s244; VBITS_GE_256-NEXT: mov z2.d, p1/z, #-1 // =0xffffffffffffffff245; VBITS_GE_256-NEXT: ptrue p1.s, vl8246; VBITS_GE_256-NEXT: mov z3.d, p0/z, #-1 // =0xffffffffffffffff247; VBITS_GE_256-NEXT: ptrue p0.s, vl4248; VBITS_GE_256-NEXT: uzp1 z2.s, z2.s, z2.s249; VBITS_GE_256-NEXT: splice z1.s, p0, z1.s, z0.s250; VBITS_GE_256-NEXT: uzp1 z3.s, z3.s, z3.s251; VBITS_GE_256-NEXT: splice z3.s, p0, z3.s, z2.s252; VBITS_GE_256-NEXT: cmpne p1.s, p1/z, z3.s, #0253; VBITS_GE_256-NEXT: st1w { z1.s }, p1, [x2]254; VBITS_GE_256-NEXT: ret255;256; VBITS_GE_512-LABEL: masked_store_trunc_v8i64i32:257; VBITS_GE_512: // %bb.0:258; VBITS_GE_512-NEXT: ptrue p0.d, vl8259; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]260; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]261; VBITS_GE_512-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d262; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [x2]263; VBITS_GE_512-NEXT: ret264 %a = load <8 x i64>, ptr %ap265 %b = load <8 x i64>, ptr %bp266 %mask = icmp eq <8 x i64> %a, %b267 %val = trunc <8 x i64> %a to <8 x i32>268 call void @llvm.masked.store.v8i32(<8 x i32> %val, ptr %dest, i32 8, <8 x i1> %mask)269 ret void270}271 272define void @masked_store_trunc_v16i32i8(ptr %ap, ptr %bp, ptr %dest) #0 {273; VBITS_GE_256-LABEL: masked_store_trunc_v16i32i8:274; VBITS_GE_256: // %bb.0:275; VBITS_GE_256-NEXT: ptrue p0.s, vl8276; VBITS_GE_256-NEXT: mov x8, #8 // =0x8277; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]278; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]279; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x1, x8, lsl #2]280; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]281; VBITS_GE_256-NEXT: cmpeq p1.s, p0/z, z0.s, z2.s282; VBITS_GE_256-NEXT: uzp1 z0.h, z0.h, z0.h283; VBITS_GE_256-NEXT: cmpeq p0.s, p0/z, z1.s, z3.s284; VBITS_GE_256-NEXT: uzp1 z1.h, z1.h, z1.h285; VBITS_GE_256-NEXT: uzp1 z0.b, z0.b, z0.b286; VBITS_GE_256-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff287; VBITS_GE_256-NEXT: uzp1 z1.b, z1.b, z1.b288; VBITS_GE_256-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff289; VBITS_GE_256-NEXT: ptrue p0.b, vl16290; VBITS_GE_256-NEXT: uzp1 z2.h, z2.h, z2.h291; VBITS_GE_256-NEXT: mov v1.d[1], v0.d[0]292; VBITS_GE_256-NEXT: uzp1 z3.h, z3.h, z3.h293; VBITS_GE_256-NEXT: uzp1 z2.b, z2.b, z2.b294; VBITS_GE_256-NEXT: uzp1 z3.b, z3.b, z3.b295; VBITS_GE_256-NEXT: mov v3.d[1], v2.d[0]296; VBITS_GE_256-NEXT: cmpne p0.b, p0/z, z3.b, #0297; VBITS_GE_256-NEXT: st1b { z1.b }, p0, [x2]298; VBITS_GE_256-NEXT: ret299;300; VBITS_GE_512-LABEL: masked_store_trunc_v16i32i8:301; VBITS_GE_512: // %bb.0:302; VBITS_GE_512-NEXT: ptrue p0.s, vl16303; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]304; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]305; VBITS_GE_512-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s306; VBITS_GE_512-NEXT: st1b { z0.s }, p0, [x2]307; VBITS_GE_512-NEXT: ret308 %a = load <16 x i32>, ptr %ap309 %b = load <16 x i32>, ptr %bp310 %mask = icmp eq <16 x i32> %a, %b311 %val = trunc <16 x i32> %a to <16 x i8>312 call void @llvm.masked.store.v16i8(<16 x i8> %val, ptr %dest, i32 8, <16 x i1> %mask)313 ret void314}315 316define void @masked_store_trunc_v16i32i16(ptr %ap, ptr %bp, ptr %dest) #0 {317; VBITS_GE_256-LABEL: masked_store_trunc_v16i32i16:318; VBITS_GE_256: // %bb.0:319; VBITS_GE_256-NEXT: ptrue p0.s, vl8320; VBITS_GE_256-NEXT: mov x8, #8 // =0x8321; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]322; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]323; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x1, x8, lsl #2]324; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]325; VBITS_GE_256-NEXT: cmpeq p1.s, p0/z, z0.s, z2.s326; VBITS_GE_256-NEXT: uzp1 z0.h, z0.h, z0.h327; VBITS_GE_256-NEXT: cmpeq p0.s, p0/z, z1.s, z3.s328; VBITS_GE_256-NEXT: uzp1 z1.h, z1.h, z1.h329; VBITS_GE_256-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff330; VBITS_GE_256-NEXT: ptrue p1.h, vl8331; VBITS_GE_256-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff332; VBITS_GE_256-NEXT: ptrue p0.h, vl16333; VBITS_GE_256-NEXT: splice z1.h, p1, z1.h, z0.h334; VBITS_GE_256-NEXT: uzp1 z2.h, z2.h, z2.h335; VBITS_GE_256-NEXT: uzp1 z3.h, z3.h, z3.h336; VBITS_GE_256-NEXT: uzp1 z2.b, z2.b, z2.b337; VBITS_GE_256-NEXT: uzp1 z3.b, z3.b, z3.b338; VBITS_GE_256-NEXT: mov v3.d[1], v2.d[0]339; VBITS_GE_256-NEXT: sunpklo z2.h, z3.b340; VBITS_GE_256-NEXT: cmpne p0.h, p0/z, z2.h, #0341; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x2]342; VBITS_GE_256-NEXT: ret343;344; VBITS_GE_512-LABEL: masked_store_trunc_v16i32i16:345; VBITS_GE_512: // %bb.0:346; VBITS_GE_512-NEXT: ptrue p0.s, vl16347; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]348; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]349; VBITS_GE_512-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s350; VBITS_GE_512-NEXT: st1h { z0.s }, p0, [x2]351; VBITS_GE_512-NEXT: ret352 %a = load <16 x i32>, ptr %ap353 %b = load <16 x i32>, ptr %bp354 %mask = icmp eq <16 x i32> %a, %b355 %val = trunc <16 x i32> %a to <16 x i16>356 call void @llvm.masked.store.v16i16(<16 x i16> %val, ptr %dest, i32 8, <16 x i1> %mask)357 ret void358}359 360define void @masked_store_trunc_v32i16i8(ptr %ap, ptr %bp, ptr %dest) #0 {361; VBITS_GE_256-LABEL: masked_store_trunc_v32i16i8:362; VBITS_GE_256: // %bb.0:363; VBITS_GE_256-NEXT: ptrue p0.h, vl16364; VBITS_GE_256-NEXT: mov x8, #16 // =0x10365; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]366; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]367; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x1, x8, lsl #1]368; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]369; VBITS_GE_256-NEXT: cmpeq p1.h, p0/z, z0.h, z2.h370; VBITS_GE_256-NEXT: uzp1 z0.b, z0.b, z0.b371; VBITS_GE_256-NEXT: cmpeq p0.h, p0/z, z1.h, z3.h372; VBITS_GE_256-NEXT: uzp1 z1.b, z1.b, z1.b373; VBITS_GE_256-NEXT: mov z2.h, p1/z, #-1 // =0xffffffffffffffff374; VBITS_GE_256-NEXT: ptrue p1.b, vl32375; VBITS_GE_256-NEXT: mov z3.h, p0/z, #-1 // =0xffffffffffffffff376; VBITS_GE_256-NEXT: ptrue p0.b, vl16377; VBITS_GE_256-NEXT: uzp1 z2.b, z2.b, z2.b378; VBITS_GE_256-NEXT: splice z1.b, p0, z1.b, z0.b379; VBITS_GE_256-NEXT: uzp1 z3.b, z3.b, z3.b380; VBITS_GE_256-NEXT: splice z3.b, p0, z3.b, z2.b381; VBITS_GE_256-NEXT: cmpne p1.b, p1/z, z3.b, #0382; VBITS_GE_256-NEXT: st1b { z1.b }, p1, [x2]383; VBITS_GE_256-NEXT: ret384;385; VBITS_GE_512-LABEL: masked_store_trunc_v32i16i8:386; VBITS_GE_512: // %bb.0:387; VBITS_GE_512-NEXT: ptrue p0.h, vl32388; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]389; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]390; VBITS_GE_512-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h391; VBITS_GE_512-NEXT: st1b { z0.h }, p0, [x2]392; VBITS_GE_512-NEXT: ret393 %a = load <32 x i16>, ptr %ap394 %b = load <32 x i16>, ptr %bp395 %mask = icmp eq <32 x i16> %a, %b396 %val = trunc <32 x i16> %a to <32 x i8>397 call void @llvm.masked.store.v32i8(<32 x i8> %val, ptr %dest, i32 8, <32 x i1> %mask)398 ret void399}400 401declare void @llvm.masked.store.v2f16(<2 x half>, ptr, i32, <2 x i1>)402declare void @llvm.masked.store.v2f32(<2 x float>, ptr, i32, <2 x i1>)403declare void @llvm.masked.store.v4f32(<4 x float>, ptr, i32, <4 x i1>)404declare void @llvm.masked.store.v8f32(<8 x float>, ptr, i32, <8 x i1>)405declare void @llvm.masked.store.v16f32(<16 x float>, ptr, i32, <16 x i1>)406declare void @llvm.masked.store.v32f32(<32 x float>, ptr, i32, <32 x i1>)407declare void @llvm.masked.store.v64f32(<64 x float>, ptr, i32, <64 x i1>)408 409declare void @llvm.masked.store.v8i8(<8 x i8>, ptr, i32, <8 x i1>)410declare void @llvm.masked.store.v8i16(<8 x i16>, ptr, i32, <8 x i1>)411declare void @llvm.masked.store.v8i32(<8 x i32>, ptr, i32, <8 x i1>)412declare void @llvm.masked.store.v16i8(<16 x i8>, ptr, i32, <16 x i1>)413declare void @llvm.masked.store.v16i16(<16 x i16>, ptr, i32, <16 x i1>)414declare void @llvm.masked.store.v32i8(<32 x i8>, ptr, i32, <32 x i1>)415 416attributes #0 = { "target-features"="+sve" }417