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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=512 -aarch64-sve-vector-bits-max=512 < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6define void @add_v64i8(ptr %a, ptr %b) #0 {7; CHECK-LABEL: add_v64i8:8; CHECK: // %bb.0:9; CHECK-NEXT: ldr z0, [x0]10; CHECK-NEXT: ldr z1, [x1]11; CHECK-NEXT: add z0.b, z0.b, z1.b12; CHECK-NEXT: str z0, [x0]13; CHECK-NEXT: ret14 %op1 = load <64 x i8>, ptr %a15 %op2 = load <64 x i8>, ptr %b16 %res = add <64 x i8> %op1, %op217 store <64 x i8> %res, ptr %a18 ret void19}20 21define void @add_v32i16(ptr %a, ptr %b, ptr %c) #0 {22; CHECK-LABEL: add_v32i16:23; CHECK: // %bb.0:24; CHECK-NEXT: ldr z0, [x0]25; CHECK-NEXT: ldr z1, [x1]26; CHECK-NEXT: add z0.h, z0.h, z1.h27; CHECK-NEXT: str z0, [x0]28; CHECK-NEXT: ret29 %op1 = load <32 x i16>, ptr %a30 %op2 = load <32 x i16>, ptr %b31 %res = add <32 x i16> %op1, %op232 store <32 x i16> %res, ptr %a33 ret void34}35 36define void @abs_v16i32(ptr %a) #0 {37; CHECK-LABEL: abs_v16i32:38; CHECK: // %bb.0:39; CHECK-NEXT: ldr z0, [x0]40; CHECK-NEXT: ptrue p0.s41; CHECK-NEXT: abs z0.s, p0/m, z0.s42; CHECK-NEXT: str z0, [x0]43; CHECK-NEXT: ret44 %op1 = load <16 x i32>, ptr %a45 %res = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %op1, i1 false)46 store <16 x i32> %res, ptr %a47 ret void48}49 50define void @abs_v8i64(ptr %a) #0 {51; CHECK-LABEL: abs_v8i64:52; CHECK: // %bb.0:53; CHECK-NEXT: ldr z0, [x0]54; CHECK-NEXT: ptrue p0.d55; CHECK-NEXT: abs z0.d, p0/m, z0.d56; CHECK-NEXT: str z0, [x0]57; CHECK-NEXT: ret58 %op1 = load <8 x i64>, ptr %a59 %res = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %op1, i1 false)60 store <8 x i64> %res, ptr %a61 ret void62}63 64define void @fadd_v32f16(ptr %a, ptr %b) #0 {65; CHECK-LABEL: fadd_v32f16:66; CHECK: // %bb.0:67; CHECK-NEXT: ldr z0, [x0]68; CHECK-NEXT: ldr z1, [x1]69; CHECK-NEXT: fadd z0.h, z0.h, z1.h70; CHECK-NEXT: str z0, [x0]71; CHECK-NEXT: ret72 %op1 = load <32 x half>, ptr %a73 %op2 = load <32 x half>, ptr %b74 %res = fadd <32 x half> %op1, %op275 store <32 x half> %res, ptr %a76 ret void77}78 79define void @fadd_v16f32(ptr %a, ptr %b) #0 {80; CHECK-LABEL: fadd_v16f32:81; CHECK: // %bb.0:82; CHECK-NEXT: ldr z0, [x0]83; CHECK-NEXT: ldr z1, [x1]84; CHECK-NEXT: fadd z0.s, z0.s, z1.s85; CHECK-NEXT: str z0, [x0]86; CHECK-NEXT: ret87 %op1 = load <16 x float>, ptr %a88 %op2 = load <16 x float>, ptr %b89 %res = fadd <16 x float> %op1, %op290 store <16 x float> %res, ptr %a91 ret void92}93 94define void @fadd_v8f64(ptr %a, ptr %b) #0 {95; CHECK-LABEL: fadd_v8f64:96; CHECK: // %bb.0:97; CHECK-NEXT: ldr z0, [x0]98; CHECK-NEXT: ldr z1, [x1]99; CHECK-NEXT: fadd z0.d, z0.d, z1.d100; CHECK-NEXT: str z0, [x0]101; CHECK-NEXT: ret102 %op1 = load <8 x double>, ptr %a103 %op2 = load <8 x double>, ptr %b104 %res = fadd <8 x double> %op1, %op2105 store <8 x double> %res, ptr %a106 ret void107}108 109declare <16 x i32> @llvm.abs.v16i32(<16 x i32>, i1)110declare <8 x i64> @llvm.abs.v8i64(<8 x i64>, i1)111 112attributes #0 = { "target-features"="+sve" }113