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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s3 4define i1 @ptest_v16i1_256bit_min_sve(ptr %a, ptr %b) vscale_range(2, 0) {5; CHECK-LABEL: ptest_v16i1_256bit_min_sve:6; CHECK: // %bb.0:7; CHECK-NEXT: ptrue p0.s, vl88; CHECK-NEXT: mov x8, #8 // =0x89; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]10; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0]11; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, #0.012; CHECK-NEXT: fcmne p0.s, p0/z, z1.s, #0.013; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff14; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff15; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h16; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h17; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b18; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b19; CHECK-NEXT: mov v1.d[1], v0.d[0]20; CHECK-NEXT: umaxv b0, v1.16b21; CHECK-NEXT: fmov w8, s022; CHECK-NEXT: and w0, w8, #0x123; CHECK-NEXT: ret24 %v1 = load <16 x float>, ptr %a, align 425 %v2 = fcmp une <16 x float> %v1, zeroinitializer26 %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)27 ret i1 %v328}29 30define i1 @ptest_v16i1_512bit_min_sve(ptr %a, ptr %b) vscale_range(4, 0) {31; CHECK-LABEL: ptest_v16i1_512bit_min_sve:32; CHECK: // %bb.0:33; CHECK-NEXT: ptrue p0.s, vl1634; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]35; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.036; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff37; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h38; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b39; CHECK-NEXT: umaxv b0, v0.16b40; CHECK-NEXT: fmov w8, s041; CHECK-NEXT: and w0, w8, #0x142; CHECK-NEXT: ret43 %v1 = load <16 x float>, ptr %a, align 444 %v2 = fcmp une <16 x float> %v1, zeroinitializer45 %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)46 ret i1 %v347}48 49define i1 @ptest_v16i1_512bit_sve(ptr %a, ptr %b) vscale_range(4, 4) {50; CHECK-LABEL: ptest_v16i1_512bit_sve:51; CHECK: // %bb.0:52; CHECK-NEXT: ldr z0, [x0]53; CHECK-NEXT: ptrue p0.s54; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.055; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff56; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h57; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b58; CHECK-NEXT: umaxv b0, v0.16b59; CHECK-NEXT: fmov w8, s060; CHECK-NEXT: and w0, w8, #0x161; CHECK-NEXT: ret62 %v1 = load <16 x float>, ptr %a, align 463 %v2 = fcmp une <16 x float> %v1, zeroinitializer64 %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)65 ret i1 %v366}67 68define i1 @ptest_or_v16i1_512bit_min_sve(ptr %a, ptr %b) vscale_range(4, 0) {69; CHECK-LABEL: ptest_or_v16i1_512bit_min_sve:70; CHECK: // %bb.0:71; CHECK-NEXT: ptrue p0.s, vl1672; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]73; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]74; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, #0.075; CHECK-NEXT: fcmne p0.s, p0/z, z1.s, #0.076; CHECK-NEXT: mov p0.b, p1/m, p1.b77; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff78; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h79; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b80; CHECK-NEXT: umaxv b0, v0.16b81; CHECK-NEXT: fmov w8, s082; CHECK-NEXT: and w0, w8, #0x183; CHECK-NEXT: ret84 %v1 = load <16 x float>, ptr %a, align 485 %v2 = fcmp une <16 x float> %v1, zeroinitializer86 %v4 = load <16 x float>, ptr %b, align 487 %v5 = fcmp une <16 x float> %v4, zeroinitializer88 %v6 = or <16 x i1> %v2, %v589 %v7 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v6)90 ret i1 %v791}92 93declare i1 @llvm.vector.reduce.or.i1.v16i1(<16 x i1>)94 95;96; AND reduction.97;98 99define i1 @ptest_and_v16i1_512bit_sve(ptr %a, ptr %b) vscale_range(4, 4) {100; CHECK-LABEL: ptest_and_v16i1_512bit_sve:101; CHECK: // %bb.0:102; CHECK-NEXT: ldr z0, [x0]103; CHECK-NEXT: ptrue p0.s104; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0105; CHECK-NEXT: ldr z0, [x1]106; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0107; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff108; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h109; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b110; CHECK-NEXT: uminv b0, v0.16b111; CHECK-NEXT: fmov w8, s0112; CHECK-NEXT: and w0, w8, #0x1113; CHECK-NEXT: ret114 %v1 = load <16 x float>, ptr %a, align 4115 %v2 = fcmp une <16 x float> %v1, zeroinitializer116 %v4 = load <16 x float>, ptr %b, align 4117 %v5 = fcmp une <16 x float> %v4, zeroinitializer118 %v6 = and <16 x i1> %v2, %v5119 %v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6)120 ret i1 %v7121}122 123define i1 @ptest_and_v16i1_512bit_min_sve(ptr %a, ptr %b) vscale_range(4, 0) {124; CHECK-LABEL: ptest_and_v16i1_512bit_min_sve:125; CHECK: // %bb.0:126; CHECK-NEXT: ptrue p0.s, vl16127; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]128; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]129; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, #0.0130; CHECK-NEXT: fcmne p0.s, p0/z, z1.s, #0.0131; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b132; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff133; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h134; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b135; CHECK-NEXT: uminv b0, v0.16b136; CHECK-NEXT: fmov w8, s0137; CHECK-NEXT: and w0, w8, #0x1138; CHECK-NEXT: ret139 %v1 = load <16 x float>, ptr %a, align 4140 %v2 = fcmp une <16 x float> %v1, zeroinitializer141 %v4 = load <16 x float>, ptr %b, align 4142 %v5 = fcmp une <16 x float> %v4, zeroinitializer143 %v6 = and <16 x i1> %v2, %v5144 %v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6)145 ret i1 %v7146}147 148declare i1 @llvm.vector.reduce.and.i1.v16i1(<16 x i1>)149