693 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6target triple = "aarch64-unknown-linux-gnu"7 8;9; RBIT10;11 12define <8 x i8> @bitreverse_v8i8(<8 x i8> %op) vscale_range(2,0) #0 {13; CHECK-LABEL: bitreverse_v8i8:14; CHECK: // %bb.0:15; CHECK-NEXT: ptrue p0.b, vl816; CHECK-NEXT: // kill: def $d0 killed $d0 def $z017; CHECK-NEXT: rbit z0.b, p0/m, z0.b18; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z019; CHECK-NEXT: ret20 %res = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %op)21 ret <8 x i8> %res22}23 24define <16 x i8> @bitreverse_v16i8(<16 x i8> %op) vscale_range(2,0) #0 {25; CHECK-LABEL: bitreverse_v16i8:26; CHECK: // %bb.0:27; CHECK-NEXT: ptrue p0.b, vl1628; CHECK-NEXT: // kill: def $q0 killed $q0 def $z029; CHECK-NEXT: rbit z0.b, p0/m, z0.b30; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z031; CHECK-NEXT: ret32 %res = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %op)33 ret <16 x i8> %res34}35 36define void @bitreverse_v32i8(ptr %a) vscale_range(2,0) #0 {37; CHECK-LABEL: bitreverse_v32i8:38; CHECK: // %bb.0:39; CHECK-NEXT: ptrue p0.b, vl3240; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]41; CHECK-NEXT: rbit z0.b, p0/m, z0.b42; CHECK-NEXT: st1b { z0.b }, p0, [x0]43; CHECK-NEXT: ret44 %op = load <32 x i8>, ptr %a45 %res = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %op)46 store <32 x i8> %res, ptr %a47 ret void48}49 50define void @bitreverse_v64i8(ptr %a) #0 {51; VBITS_GE_256-LABEL: bitreverse_v64i8:52; VBITS_GE_256: // %bb.0:53; VBITS_GE_256-NEXT: ptrue p0.b, vl3254; VBITS_GE_256-NEXT: mov w8, #32 // =0x2055; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]56; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0]57; VBITS_GE_256-NEXT: rbit z0.b, p0/m, z0.b58; VBITS_GE_256-NEXT: rbit z1.b, p0/m, z1.b59; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]60; VBITS_GE_256-NEXT: st1b { z1.b }, p0, [x0]61; VBITS_GE_256-NEXT: ret62;63; VBITS_GE_512-LABEL: bitreverse_v64i8:64; VBITS_GE_512: // %bb.0:65; VBITS_GE_512-NEXT: ptrue p0.b, vl6466; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]67; VBITS_GE_512-NEXT: rbit z0.b, p0/m, z0.b68; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]69; VBITS_GE_512-NEXT: ret70 %op = load <64 x i8>, ptr %a71 %res = call <64 x i8> @llvm.bitreverse.v64i8(<64 x i8> %op)72 store <64 x i8> %res, ptr %a73 ret void74}75 76define void @bitreverse_v128i8(ptr %a) vscale_range(8,0) #0 {77; CHECK-LABEL: bitreverse_v128i8:78; CHECK: // %bb.0:79; CHECK-NEXT: ptrue p0.b, vl12880; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]81; CHECK-NEXT: rbit z0.b, p0/m, z0.b82; CHECK-NEXT: st1b { z0.b }, p0, [x0]83; CHECK-NEXT: ret84 %op = load <128 x i8>, ptr %a85 %res = call <128 x i8> @llvm.bitreverse.v128i8(<128 x i8> %op)86 store <128 x i8> %res, ptr %a87 ret void88}89 90define void @bitreverse_v256i8(ptr %a) vscale_range(16,0) #0 {91; CHECK-LABEL: bitreverse_v256i8:92; CHECK: // %bb.0:93; CHECK-NEXT: ptrue p0.b, vl25694; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]95; CHECK-NEXT: rbit z0.b, p0/m, z0.b96; CHECK-NEXT: st1b { z0.b }, p0, [x0]97; CHECK-NEXT: ret98 %op = load <256 x i8>, ptr %a99 %res = call <256 x i8> @llvm.bitreverse.v256i8(<256 x i8> %op)100 store <256 x i8> %res, ptr %a101 ret void102}103 104define <4 x i16> @bitreverse_v4i16(<4 x i16> %op) vscale_range(2,0) #0 {105; CHECK-LABEL: bitreverse_v4i16:106; CHECK: // %bb.0:107; CHECK-NEXT: ptrue p0.h, vl4108; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0109; CHECK-NEXT: rbit z0.h, p0/m, z0.h110; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0111; CHECK-NEXT: ret112 %res = call <4 x i16> @llvm.bitreverse.v4i16(<4 x i16> %op)113 ret <4 x i16> %res114}115 116define <8 x i16> @bitreverse_v8i16(<8 x i16> %op) vscale_range(2,0) #0 {117; CHECK-LABEL: bitreverse_v8i16:118; CHECK: // %bb.0:119; CHECK-NEXT: ptrue p0.h, vl8120; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0121; CHECK-NEXT: rbit z0.h, p0/m, z0.h122; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0123; CHECK-NEXT: ret124 %res = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %op)125 ret <8 x i16> %res126}127 128define void @bitreverse_v16i16(ptr %a) vscale_range(2,0) #0 {129; CHECK-LABEL: bitreverse_v16i16:130; CHECK: // %bb.0:131; CHECK-NEXT: ptrue p0.h, vl16132; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]133; CHECK-NEXT: rbit z0.h, p0/m, z0.h134; CHECK-NEXT: st1h { z0.h }, p0, [x0]135; CHECK-NEXT: ret136 %op = load <16 x i16>, ptr %a137 %res = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %op)138 store <16 x i16> %res, ptr %a139 ret void140}141 142define void @bitreverse_v32i16(ptr %a) #0 {143; VBITS_GE_256-LABEL: bitreverse_v32i16:144; VBITS_GE_256: // %bb.0:145; VBITS_GE_256-NEXT: ptrue p0.h, vl16146; VBITS_GE_256-NEXT: mov x8, #16 // =0x10147; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]148; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]149; VBITS_GE_256-NEXT: rbit z0.h, p0/m, z0.h150; VBITS_GE_256-NEXT: rbit z1.h, p0/m, z1.h151; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]152; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x0]153; VBITS_GE_256-NEXT: ret154;155; VBITS_GE_512-LABEL: bitreverse_v32i16:156; VBITS_GE_512: // %bb.0:157; VBITS_GE_512-NEXT: ptrue p0.h, vl32158; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]159; VBITS_GE_512-NEXT: rbit z0.h, p0/m, z0.h160; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]161; VBITS_GE_512-NEXT: ret162 %op = load <32 x i16>, ptr %a163 %res = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %op)164 store <32 x i16> %res, ptr %a165 ret void166}167 168define void @bitreverse_v64i16(ptr %a) vscale_range(8,0) #0 {169; CHECK-LABEL: bitreverse_v64i16:170; CHECK: // %bb.0:171; CHECK-NEXT: ptrue p0.h, vl64172; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]173; CHECK-NEXT: rbit z0.h, p0/m, z0.h174; CHECK-NEXT: st1h { z0.h }, p0, [x0]175; CHECK-NEXT: ret176 %op = load <64 x i16>, ptr %a177 %res = call <64 x i16> @llvm.bitreverse.v64i16(<64 x i16> %op)178 store <64 x i16> %res, ptr %a179 ret void180}181 182define void @bitreverse_v128i16(ptr %a) vscale_range(16,0) #0 {183; CHECK-LABEL: bitreverse_v128i16:184; CHECK: // %bb.0:185; CHECK-NEXT: ptrue p0.h, vl128186; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]187; CHECK-NEXT: rbit z0.h, p0/m, z0.h188; CHECK-NEXT: st1h { z0.h }, p0, [x0]189; CHECK-NEXT: ret190 %op = load <128 x i16>, ptr %a191 %res = call <128 x i16> @llvm.bitreverse.v128i16(<128 x i16> %op)192 store <128 x i16> %res, ptr %a193 ret void194}195 196define <2 x i32> @bitreverse_v2i32(<2 x i32> %op) vscale_range(2,0) #0 {197; CHECK-LABEL: bitreverse_v2i32:198; CHECK: // %bb.0:199; CHECK-NEXT: ptrue p0.s, vl2200; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0201; CHECK-NEXT: rbit z0.s, p0/m, z0.s202; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0203; CHECK-NEXT: ret204 %res = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %op)205 ret <2 x i32> %res206}207 208define <4 x i32> @bitreverse_v4i32(<4 x i32> %op) vscale_range(2,0) #0 {209; CHECK-LABEL: bitreverse_v4i32:210; CHECK: // %bb.0:211; CHECK-NEXT: ptrue p0.s, vl4212; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0213; CHECK-NEXT: rbit z0.s, p0/m, z0.s214; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0215; CHECK-NEXT: ret216 %res = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %op)217 ret <4 x i32> %res218}219 220define void @bitreverse_v8i32(ptr %a) vscale_range(2,0) #0 {221; CHECK-LABEL: bitreverse_v8i32:222; CHECK: // %bb.0:223; CHECK-NEXT: ptrue p0.s, vl8224; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]225; CHECK-NEXT: rbit z0.s, p0/m, z0.s226; CHECK-NEXT: st1w { z0.s }, p0, [x0]227; CHECK-NEXT: ret228 %op = load <8 x i32>, ptr %a229 %res = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %op)230 store <8 x i32> %res, ptr %a231 ret void232}233 234define void @bitreverse_v16i32(ptr %a) #0 {235; VBITS_GE_256-LABEL: bitreverse_v16i32:236; VBITS_GE_256: // %bb.0:237; VBITS_GE_256-NEXT: ptrue p0.s, vl8238; VBITS_GE_256-NEXT: mov x8, #8 // =0x8239; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]240; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]241; VBITS_GE_256-NEXT: rbit z0.s, p0/m, z0.s242; VBITS_GE_256-NEXT: rbit z1.s, p0/m, z1.s243; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]244; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]245; VBITS_GE_256-NEXT: ret246;247; VBITS_GE_512-LABEL: bitreverse_v16i32:248; VBITS_GE_512: // %bb.0:249; VBITS_GE_512-NEXT: ptrue p0.s, vl16250; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]251; VBITS_GE_512-NEXT: rbit z0.s, p0/m, z0.s252; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]253; VBITS_GE_512-NEXT: ret254 %op = load <16 x i32>, ptr %a255 %res = call <16 x i32> @llvm.bitreverse.v16i32(<16 x i32> %op)256 store <16 x i32> %res, ptr %a257 ret void258}259 260define void @bitreverse_v32i32(ptr %a) vscale_range(8,0) #0 {261; CHECK-LABEL: bitreverse_v32i32:262; CHECK: // %bb.0:263; CHECK-NEXT: ptrue p0.s, vl32264; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]265; CHECK-NEXT: rbit z0.s, p0/m, z0.s266; CHECK-NEXT: st1w { z0.s }, p0, [x0]267; CHECK-NEXT: ret268 %op = load <32 x i32>, ptr %a269 %res = call <32 x i32> @llvm.bitreverse.v32i32(<32 x i32> %op)270 store <32 x i32> %res, ptr %a271 ret void272}273 274define void @bitreverse_v64i32(ptr %a) vscale_range(16,0) #0 {275; CHECK-LABEL: bitreverse_v64i32:276; CHECK: // %bb.0:277; CHECK-NEXT: ptrue p0.s, vl64278; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]279; CHECK-NEXT: rbit z0.s, p0/m, z0.s280; CHECK-NEXT: st1w { z0.s }, p0, [x0]281; CHECK-NEXT: ret282 %op = load <64 x i32>, ptr %a283 %res = call <64 x i32> @llvm.bitreverse.v64i32(<64 x i32> %op)284 store <64 x i32> %res, ptr %a285 ret void286}287 288define <1 x i64> @bitreverse_v1i64(<1 x i64> %op) vscale_range(2,0) #0 {289; CHECK-LABEL: bitreverse_v1i64:290; CHECK: // %bb.0:291; CHECK-NEXT: ptrue p0.d, vl1292; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0293; CHECK-NEXT: rbit z0.d, p0/m, z0.d294; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0295; CHECK-NEXT: ret296 %res = call <1 x i64> @llvm.bitreverse.v1i64(<1 x i64> %op)297 ret <1 x i64> %res298}299 300define <2 x i64> @bitreverse_v2i64(<2 x i64> %op) vscale_range(2,0) #0 {301; CHECK-LABEL: bitreverse_v2i64:302; CHECK: // %bb.0:303; CHECK-NEXT: ptrue p0.d, vl2304; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0305; CHECK-NEXT: rbit z0.d, p0/m, z0.d306; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0307; CHECK-NEXT: ret308 %res = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %op)309 ret <2 x i64> %res310}311 312define void @bitreverse_v4i64(ptr %a) vscale_range(2,0) #0 {313; CHECK-LABEL: bitreverse_v4i64:314; CHECK: // %bb.0:315; CHECK-NEXT: ptrue p0.d, vl4316; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]317; CHECK-NEXT: rbit z0.d, p0/m, z0.d318; CHECK-NEXT: st1d { z0.d }, p0, [x0]319; CHECK-NEXT: ret320 %op = load <4 x i64>, ptr %a321 %res = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %op)322 store <4 x i64> %res, ptr %a323 ret void324}325 326define void @bitreverse_v8i64(ptr %a) #0 {327; VBITS_GE_256-LABEL: bitreverse_v8i64:328; VBITS_GE_256: // %bb.0:329; VBITS_GE_256-NEXT: ptrue p0.d, vl4330; VBITS_GE_256-NEXT: mov x8, #4 // =0x4331; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]332; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]333; VBITS_GE_256-NEXT: rbit z0.d, p0/m, z0.d334; VBITS_GE_256-NEXT: rbit z1.d, p0/m, z1.d335; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]336; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]337; VBITS_GE_256-NEXT: ret338;339; VBITS_GE_512-LABEL: bitreverse_v8i64:340; VBITS_GE_512: // %bb.0:341; VBITS_GE_512-NEXT: ptrue p0.d, vl8342; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]343; VBITS_GE_512-NEXT: rbit z0.d, p0/m, z0.d344; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]345; VBITS_GE_512-NEXT: ret346 %op = load <8 x i64>, ptr %a347 %res = call <8 x i64> @llvm.bitreverse.v8i64(<8 x i64> %op)348 store <8 x i64> %res, ptr %a349 ret void350}351 352define void @bitreverse_v16i64(ptr %a) vscale_range(8,0) #0 {353; CHECK-LABEL: bitreverse_v16i64:354; CHECK: // %bb.0:355; CHECK-NEXT: ptrue p0.d, vl16356; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]357; CHECK-NEXT: rbit z0.d, p0/m, z0.d358; CHECK-NEXT: st1d { z0.d }, p0, [x0]359; CHECK-NEXT: ret360 %op = load <16 x i64>, ptr %a361 %res = call <16 x i64> @llvm.bitreverse.v16i64(<16 x i64> %op)362 store <16 x i64> %res, ptr %a363 ret void364}365 366define void @bitreverse_v32i64(ptr %a) vscale_range(16,0) #0 {367; CHECK-LABEL: bitreverse_v32i64:368; CHECK: // %bb.0:369; CHECK-NEXT: ptrue p0.d, vl32370; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]371; CHECK-NEXT: rbit z0.d, p0/m, z0.d372; CHECK-NEXT: st1d { z0.d }, p0, [x0]373; CHECK-NEXT: ret374 %op = load <32 x i64>, ptr %a375 %res = call <32 x i64> @llvm.bitreverse.v32i64(<32 x i64> %op)376 store <32 x i64> %res, ptr %a377 ret void378}379 380;381; REVB382;383 384; Don't use SVE for 64-bit vectors.385define <4 x i16> @bswap_v4i16(<4 x i16> %op) vscale_range(2,0) #0 {386; CHECK-LABEL: bswap_v4i16:387; CHECK: // %bb.0:388; CHECK-NEXT: rev16 v0.8b, v0.8b389; CHECK-NEXT: ret390 %res = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %op)391 ret <4 x i16> %res392}393 394; Don't use SVE for 128-bit vectors.395define <8 x i16> @bswap_v8i16(<8 x i16> %op) vscale_range(2,0) #0 {396; CHECK-LABEL: bswap_v8i16:397; CHECK: // %bb.0:398; CHECK-NEXT: rev16 v0.16b, v0.16b399; CHECK-NEXT: ret400 %res = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %op)401 ret <8 x i16> %res402}403 404define void @bswap_v16i16(ptr %a) vscale_range(2,0) #0 {405; CHECK-LABEL: bswap_v16i16:406; CHECK: // %bb.0:407; CHECK-NEXT: ptrue p0.h, vl16408; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]409; CHECK-NEXT: revb z0.h, p0/m, z0.h410; CHECK-NEXT: st1h { z0.h }, p0, [x0]411; CHECK-NEXT: ret412 %op = load <16 x i16>, ptr %a413 %res = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %op)414 store <16 x i16> %res, ptr %a415 ret void416}417 418define void @bswap_v32i16(ptr %a) #0 {419; VBITS_GE_256-LABEL: bswap_v32i16:420; VBITS_GE_256: // %bb.0:421; VBITS_GE_256-NEXT: ptrue p0.h, vl16422; VBITS_GE_256-NEXT: mov x8, #16 // =0x10423; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]424; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]425; VBITS_GE_256-NEXT: revb z0.h, p0/m, z0.h426; VBITS_GE_256-NEXT: revb z1.h, p0/m, z1.h427; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]428; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x0]429; VBITS_GE_256-NEXT: ret430;431; VBITS_GE_512-LABEL: bswap_v32i16:432; VBITS_GE_512: // %bb.0:433; VBITS_GE_512-NEXT: ptrue p0.h, vl32434; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]435; VBITS_GE_512-NEXT: revb z0.h, p0/m, z0.h436; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]437; VBITS_GE_512-NEXT: ret438 %op = load <32 x i16>, ptr %a439 %res = call <32 x i16> @llvm.bswap.v32i16(<32 x i16> %op)440 store <32 x i16> %res, ptr %a441 ret void442}443 444define void @bswap_v64i16(ptr %a) vscale_range(8,0) #0 {445; CHECK-LABEL: bswap_v64i16:446; CHECK: // %bb.0:447; CHECK-NEXT: ptrue p0.h, vl64448; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]449; CHECK-NEXT: revb z0.h, p0/m, z0.h450; CHECK-NEXT: st1h { z0.h }, p0, [x0]451; CHECK-NEXT: ret452 %op = load <64 x i16>, ptr %a453 %res = call <64 x i16> @llvm.bswap.v64i16(<64 x i16> %op)454 store <64 x i16> %res, ptr %a455 ret void456}457 458define void @bswap_v128i16(ptr %a) vscale_range(16,0) #0 {459; CHECK-LABEL: bswap_v128i16:460; CHECK: // %bb.0:461; CHECK-NEXT: ptrue p0.h, vl128462; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]463; CHECK-NEXT: revb z0.h, p0/m, z0.h464; CHECK-NEXT: st1h { z0.h }, p0, [x0]465; CHECK-NEXT: ret466 %op = load <128 x i16>, ptr %a467 %res = call <128 x i16> @llvm.bswap.v128i16(<128 x i16> %op)468 store <128 x i16> %res, ptr %a469 ret void470}471 472; Don't use SVE for 64-bit vectors.473define <2 x i32> @bswap_v2i32(<2 x i32> %op) vscale_range(2,0) #0 {474; CHECK-LABEL: bswap_v2i32:475; CHECK: // %bb.0:476; CHECK-NEXT: rev32 v0.8b, v0.8b477; CHECK-NEXT: ret478 %res = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %op)479 ret <2 x i32> %res480}481 482; Don't use SVE for 128-bit vectors.483define <4 x i32> @bswap_v4i32(<4 x i32> %op) vscale_range(2,0) #0 {484; CHECK-LABEL: bswap_v4i32:485; CHECK: // %bb.0:486; CHECK-NEXT: rev32 v0.16b, v0.16b487; CHECK-NEXT: ret488 %res = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %op)489 ret <4 x i32> %res490}491 492define void @bswap_v8i32(ptr %a) vscale_range(2,0) #0 {493; CHECK-LABEL: bswap_v8i32:494; CHECK: // %bb.0:495; CHECK-NEXT: ptrue p0.s, vl8496; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]497; CHECK-NEXT: revb z0.s, p0/m, z0.s498; CHECK-NEXT: st1w { z0.s }, p0, [x0]499; CHECK-NEXT: ret500 %op = load <8 x i32>, ptr %a501 %res = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %op)502 store <8 x i32> %res, ptr %a503 ret void504}505 506define void @bswap_v16i32(ptr %a) #0 {507; VBITS_GE_256-LABEL: bswap_v16i32:508; VBITS_GE_256: // %bb.0:509; VBITS_GE_256-NEXT: ptrue p0.s, vl8510; VBITS_GE_256-NEXT: mov x8, #8 // =0x8511; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]512; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]513; VBITS_GE_256-NEXT: revb z0.s, p0/m, z0.s514; VBITS_GE_256-NEXT: revb z1.s, p0/m, z1.s515; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]516; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]517; VBITS_GE_256-NEXT: ret518;519; VBITS_GE_512-LABEL: bswap_v16i32:520; VBITS_GE_512: // %bb.0:521; VBITS_GE_512-NEXT: ptrue p0.s, vl16522; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]523; VBITS_GE_512-NEXT: revb z0.s, p0/m, z0.s524; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]525; VBITS_GE_512-NEXT: ret526 %op = load <16 x i32>, ptr %a527 %res = call <16 x i32> @llvm.bswap.v16i32(<16 x i32> %op)528 store <16 x i32> %res, ptr %a529 ret void530}531 532define void @bswap_v32i32(ptr %a) vscale_range(8,0) #0 {533; CHECK-LABEL: bswap_v32i32:534; CHECK: // %bb.0:535; CHECK-NEXT: ptrue p0.s, vl32536; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]537; CHECK-NEXT: revb z0.s, p0/m, z0.s538; CHECK-NEXT: st1w { z0.s }, p0, [x0]539; CHECK-NEXT: ret540 %op = load <32 x i32>, ptr %a541 %res = call <32 x i32> @llvm.bswap.v32i32(<32 x i32> %op)542 store <32 x i32> %res, ptr %a543 ret void544}545 546define void @bswap_v64i32(ptr %a) vscale_range(16,0) #0 {547; CHECK-LABEL: bswap_v64i32:548; CHECK: // %bb.0:549; CHECK-NEXT: ptrue p0.s, vl64550; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]551; CHECK-NEXT: revb z0.s, p0/m, z0.s552; CHECK-NEXT: st1w { z0.s }, p0, [x0]553; CHECK-NEXT: ret554 %op = load <64 x i32>, ptr %a555 %res = call <64 x i32> @llvm.bswap.v64i32(<64 x i32> %op)556 store <64 x i32> %res, ptr %a557 ret void558}559 560; Don't use SVE for 64-bit vectors.561define <1 x i64> @bswap_v1i64(<1 x i64> %op) vscale_range(2,0) #0 {562; CHECK-LABEL: bswap_v1i64:563; CHECK: // %bb.0:564; CHECK-NEXT: rev64 v0.8b, v0.8b565; CHECK-NEXT: ret566 %res = call <1 x i64> @llvm.bswap.v1i64(<1 x i64> %op)567 ret <1 x i64> %res568}569 570; Don't use SVE for 128-bit vectors.571define <2 x i64> @bswap_v2i64(<2 x i64> %op) vscale_range(2,0) #0 {572; CHECK-LABEL: bswap_v2i64:573; CHECK: // %bb.0:574; CHECK-NEXT: rev64 v0.16b, v0.16b575; CHECK-NEXT: ret576 %res = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %op)577 ret <2 x i64> %res578}579 580define void @bswap_v4i64(ptr %a) vscale_range(2,0) #0 {581; CHECK-LABEL: bswap_v4i64:582; CHECK: // %bb.0:583; CHECK-NEXT: ptrue p0.d, vl4584; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]585; CHECK-NEXT: revb z0.d, p0/m, z0.d586; CHECK-NEXT: st1d { z0.d }, p0, [x0]587; CHECK-NEXT: ret588 %op = load <4 x i64>, ptr %a589 %res = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %op)590 store <4 x i64> %res, ptr %a591 ret void592}593 594define void @bswap_v8i64(ptr %a) #0 {595; VBITS_GE_256-LABEL: bswap_v8i64:596; VBITS_GE_256: // %bb.0:597; VBITS_GE_256-NEXT: ptrue p0.d, vl4598; VBITS_GE_256-NEXT: mov x8, #4 // =0x4599; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]600; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]601; VBITS_GE_256-NEXT: revb z0.d, p0/m, z0.d602; VBITS_GE_256-NEXT: revb z1.d, p0/m, z1.d603; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]604; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]605; VBITS_GE_256-NEXT: ret606;607; VBITS_GE_512-LABEL: bswap_v8i64:608; VBITS_GE_512: // %bb.0:609; VBITS_GE_512-NEXT: ptrue p0.d, vl8610; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]611; VBITS_GE_512-NEXT: revb z0.d, p0/m, z0.d612; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]613; VBITS_GE_512-NEXT: ret614 %op = load <8 x i64>, ptr %a615 %res = call <8 x i64> @llvm.bswap.v8i64(<8 x i64> %op)616 store <8 x i64> %res, ptr %a617 ret void618}619 620define void @bswap_v16i64(ptr %a) vscale_range(8,0) #0 {621; CHECK-LABEL: bswap_v16i64:622; CHECK: // %bb.0:623; CHECK-NEXT: ptrue p0.d, vl16624; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]625; CHECK-NEXT: revb z0.d, p0/m, z0.d626; CHECK-NEXT: st1d { z0.d }, p0, [x0]627; CHECK-NEXT: ret628 %op = load <16 x i64>, ptr %a629 %res = call <16 x i64> @llvm.bswap.v16i64(<16 x i64> %op)630 store <16 x i64> %res, ptr %a631 ret void632}633 634define void @bswap_v32i64(ptr %a) vscale_range(16,0) #0 {635; CHECK-LABEL: bswap_v32i64:636; CHECK: // %bb.0:637; CHECK-NEXT: ptrue p0.d, vl32638; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]639; CHECK-NEXT: revb z0.d, p0/m, z0.d640; CHECK-NEXT: st1d { z0.d }, p0, [x0]641; CHECK-NEXT: ret642 %op = load <32 x i64>, ptr %a643 %res = call <32 x i64> @llvm.bswap.v32i64(<32 x i64> %op)644 store <32 x i64> %res, ptr %a645 ret void646}647 648attributes #0 = { "target-features"="+sve" }649 650declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>)651declare <16 x i8> @llvm.bitreverse.v16i8(<16 x i8>)652declare <32 x i8> @llvm.bitreverse.v32i8(<32 x i8>)653declare <64 x i8> @llvm.bitreverse.v64i8(<64 x i8>)654declare <128 x i8> @llvm.bitreverse.v128i8(<128 x i8>)655declare <256 x i8> @llvm.bitreverse.v256i8(<256 x i8>)656declare <4 x i16> @llvm.bitreverse.v4i16(<4 x i16>)657declare <8 x i16> @llvm.bitreverse.v8i16(<8 x i16>)658declare <16 x i16> @llvm.bitreverse.v16i16(<16 x i16>)659declare <32 x i16> @llvm.bitreverse.v32i16(<32 x i16>)660declare <64 x i16> @llvm.bitreverse.v64i16(<64 x i16>)661declare <128 x i16> @llvm.bitreverse.v128i16(<128 x i16>)662declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>)663declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>)664declare <8 x i32> @llvm.bitreverse.v8i32(<8 x i32>)665declare <16 x i32> @llvm.bitreverse.v16i32(<16 x i32>)666declare <32 x i32> @llvm.bitreverse.v32i32(<32 x i32>)667declare <64 x i32> @llvm.bitreverse.v64i32(<64 x i32>)668declare <1 x i64> @llvm.bitreverse.v1i64(<1 x i64>)669declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>)670declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>)671declare <8 x i64> @llvm.bitreverse.v8i64(<8 x i64>)672declare <16 x i64> @llvm.bitreverse.v16i64(<16 x i64>)673declare <32 x i64> @llvm.bitreverse.v32i64(<32 x i64>)674 675declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)676declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)677declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)678declare <32 x i16> @llvm.bswap.v32i16(<32 x i16>)679declare <64 x i16> @llvm.bswap.v64i16(<64 x i16>)680declare <128 x i16> @llvm.bswap.v128i16(<128 x i16>)681declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>)682declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)683declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)684declare <16 x i32> @llvm.bswap.v16i32(<16 x i32>)685declare <32 x i32> @llvm.bswap.v32i32(<32 x i32>)686declare <64 x i32> @llvm.bswap.v64i32(<64 x i32>)687declare <1 x i64> @llvm.bswap.v1i64(<1 x i64>)688declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)689declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)690declare <8 x i64> @llvm.bswap.v8i64(<8 x i64>)691declare <16 x i64> @llvm.bswap.v16i64(<16 x i64>)692declare <32 x i64> @llvm.bswap.v32i64(<32 x i64>)693