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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=128 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_1283; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2564; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5126; RUN: llc -aarch64-sve-vector-bits-min=128 -use-constant-int-for-fixed-length-splat < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_1287 8target triple = "aarch64-unknown-linux-gnu"9 10define <4 x i32> @sdiv_v4i32_negative_pow2_divisor_packed(<4 x i32> %op1) vscale_range(1,0) #0 {11; CHECK-LABEL: sdiv_v4i32_negative_pow2_divisor_packed:12; CHECK: // %bb.0:13; CHECK-NEXT: ptrue p0.s, vl414; CHECK-NEXT: // kill: def $q0 killed $q0 def $z015; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #316; CHECK-NEXT: subr z0.s, z0.s, #0 // =0x017; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z018; CHECK-NEXT: ret19 %res = sdiv <4 x i32> %op1, splat (i32 -8)20 ret <4 x i32> %res21}22 23define <2 x i32> @sdiv_v2i32_negative_pow2_divisor_unpacked(<2 x i32> %op1) vscale_range(1,0) #0 {24; CHECK-LABEL: sdiv_v2i32_negative_pow2_divisor_unpacked:25; CHECK: // %bb.0:26; CHECK-NEXT: ptrue p0.s, vl227; CHECK-NEXT: // kill: def $d0 killed $d0 def $z028; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #329; CHECK-NEXT: subr z0.s, z0.s, #0 // =0x030; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z031; CHECK-NEXT: ret32 %res = sdiv <2 x i32> %op1, splat (i32 -8)33 ret <2 x i32> %res34}35 36define <4 x i32> @sdiv_v4i32_positive_pow2_divisor_packed(<4 x i32> %op1) vscale_range(1,0) #0 {37; CHECK-LABEL: sdiv_v4i32_positive_pow2_divisor_packed:38; CHECK: // %bb.0:39; CHECK-NEXT: ptrue p0.s, vl440; CHECK-NEXT: // kill: def $q0 killed $q0 def $z041; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #342; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z043; CHECK-NEXT: ret44 %res = sdiv <4 x i32> %op1, splat (i32 8)45 ret <4 x i32> %res46}47 48define <2 x i32> @sdiv_v2i32_positive_pow2_divisor_unpacked(<2 x i32> %op1) vscale_range(1,0) #0 {49; CHECK-LABEL: sdiv_v2i32_positive_pow2_divisor_unpacked:50; CHECK: // %bb.0:51; CHECK-NEXT: ptrue p0.s, vl252; CHECK-NEXT: // kill: def $d0 killed $d0 def $z053; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #354; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z055; CHECK-NEXT: ret56 %res = sdiv <2 x i32> %op1, splat (i32 8)57 ret <2 x i32> %res58}59 60define <8 x i8> @sdiv_v8i8(<8 x i8> %op1) vscale_range(2,0) #0 {61; CHECK-LABEL: sdiv_v8i8:62; CHECK: // %bb.0:63; CHECK-NEXT: ptrue p0.b, vl864; CHECK-NEXT: // kill: def $d0 killed $d0 def $z065; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #166; CHECK-NEXT: subr z0.b, z0.b, #0 // =0x067; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z068; CHECK-NEXT: ret69 %res = sdiv <8 x i8> %op1, shufflevector (<8 x i8> insertelement (<8 x i8> poison, i8 -2, i32 0), <8 x i8> poison, <8 x i32> zeroinitializer)70 ret <8 x i8> %res71}72 73define <16 x i8> @sdiv_v16i8(<16 x i8> %op1) vscale_range(2,0) #0 {74; CHECK-LABEL: sdiv_v16i8:75; CHECK: // %bb.0:76; CHECK-NEXT: ptrue p0.b, vl1677; CHECK-NEXT: // kill: def $q0 killed $q0 def $z078; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #579; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z080; CHECK-NEXT: ret81 %res = sdiv <16 x i8> %op1, shufflevector (<16 x i8> insertelement (<16 x i8> poison, i8 32, i32 0), <16 x i8> poison, <16 x i32> zeroinitializer)82 ret <16 x i8> %res83}84 85define void @sdiv_v32i8(ptr %a) vscale_range(2,0) #0 {86; CHECK-LABEL: sdiv_v32i8:87; CHECK: // %bb.0:88; CHECK-NEXT: ptrue p0.b, vl3289; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]90; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #591; CHECK-NEXT: st1b { z0.b }, p0, [x0]92; CHECK-NEXT: ret93 %op1 = load <32 x i8>, ptr %a94 %res = sdiv <32 x i8> %op1, shufflevector (<32 x i8> insertelement (<32 x i8> poison, i8 32, i32 0), <32 x i8> poison, <32 x i32> zeroinitializer)95 store <32 x i8> %res, ptr %a96 ret void97}98 99define void @sdiv_v64i8(ptr %a) #0 {100; VBITS_GE_128-LABEL: sdiv_v64i8:101; VBITS_GE_128: // %bb.0:102; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32]103; VBITS_GE_128-NEXT: ptrue p0.b, vl16104; VBITS_GE_128-NEXT: ldp q2, q3, [x0]105; VBITS_GE_128-NEXT: asrd z0.b, p0/m, z0.b, #5106; VBITS_GE_128-NEXT: asrd z1.b, p0/m, z1.b, #5107; VBITS_GE_128-NEXT: asrd z2.b, p0/m, z2.b, #5108; VBITS_GE_128-NEXT: asrd z3.b, p0/m, z3.b, #5109; VBITS_GE_128-NEXT: stp q0, q1, [x0, #32]110; VBITS_GE_128-NEXT: stp q2, q3, [x0]111; VBITS_GE_128-NEXT: ret112;113; VBITS_GE_256-LABEL: sdiv_v64i8:114; VBITS_GE_256: // %bb.0:115; VBITS_GE_256-NEXT: ptrue p0.b, vl32116; VBITS_GE_256-NEXT: mov w8, #32 // =0x20117; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]118; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0]119; VBITS_GE_256-NEXT: asrd z0.b, p0/m, z0.b, #5120; VBITS_GE_256-NEXT: asrd z1.b, p0/m, z1.b, #5121; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]122; VBITS_GE_256-NEXT: st1b { z1.b }, p0, [x0]123; VBITS_GE_256-NEXT: ret124;125; VBITS_GE_512-LABEL: sdiv_v64i8:126; VBITS_GE_512: // %bb.0:127; VBITS_GE_512-NEXT: ptrue p0.b, vl64128; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]129; VBITS_GE_512-NEXT: asrd z0.b, p0/m, z0.b, #5130; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]131; VBITS_GE_512-NEXT: ret132 %op1 = load <64 x i8>, ptr %a133 %res = sdiv <64 x i8> %op1, shufflevector (<64 x i8> insertelement (<64 x i8> poison, i8 32, i32 0), <64 x i8> poison, <64 x i32> zeroinitializer)134 store <64 x i8> %res, ptr %a135 ret void136}137 138define void @sdiv_v128i8(ptr %a) vscale_range(8,0) #0 {139; CHECK-LABEL: sdiv_v128i8:140; CHECK: // %bb.0:141; CHECK-NEXT: ptrue p0.b, vl128142; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]143; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #2144; CHECK-NEXT: subr z0.b, z0.b, #0 // =0x0145; CHECK-NEXT: st1b { z0.b }, p0, [x0]146; CHECK-NEXT: ret147 %op1 = load <128 x i8>, ptr %a148 %res = sdiv <128 x i8> %op1, shufflevector (<128 x i8> insertelement (<128 x i8> poison, i8 -4, i32 0), <128 x i8> poison, <128 x i32> zeroinitializer)149 store <128 x i8> %res, ptr %a150 ret void151}152 153define void @sdiv_v256i8(ptr %a) vscale_range(16,0) #0 {154; CHECK-LABEL: sdiv_v256i8:155; CHECK: // %bb.0:156; CHECK-NEXT: ptrue p0.b, vl256157; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]158; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #5159; CHECK-NEXT: st1b { z0.b }, p0, [x0]160; CHECK-NEXT: ret161 %op1 = load <256 x i8>, ptr %a162 %res = sdiv <256 x i8> %op1, shufflevector (<256 x i8> insertelement (<256 x i8> poison, i8 32, i32 0), <256 x i8> poison, <256 x i32> zeroinitializer)163 store <256 x i8> %res, ptr %a164 ret void165}166 167define <4 x i16> @sdiv_v4i16(<4 x i16> %op1) vscale_range(2,0) #0 {168; CHECK-LABEL: sdiv_v4i16:169; CHECK: // %bb.0:170; CHECK-NEXT: ptrue p0.h, vl4171; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0172; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5173; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0174; CHECK-NEXT: ret175 %res = sdiv <4 x i16> %op1, shufflevector (<4 x i16> insertelement (<4 x i16> poison, i16 32, i32 0), <4 x i16> poison, <4 x i32> zeroinitializer)176 ret <4 x i16> %res177}178 179define <8 x i16> @sdiv_v8i16(<8 x i16> %op1) vscale_range(2,0) #0 {180; CHECK-LABEL: sdiv_v8i16:181; CHECK: // %bb.0:182; CHECK-NEXT: ptrue p0.h, vl8183; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0184; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #3185; CHECK-NEXT: subr z0.h, z0.h, #0 // =0x0186; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0187; CHECK-NEXT: ret188 %res = sdiv <8 x i16> %op1, shufflevector (<8 x i16> insertelement (<8 x i16> poison, i16 -8, i32 0), <8 x i16> poison, <8 x i32> zeroinitializer)189 ret <8 x i16> %res190}191 192define void @sdiv_v16i16(ptr %a) vscale_range(2,0) #0 {193; CHECK-LABEL: sdiv_v16i16:194; CHECK: // %bb.0:195; CHECK-NEXT: ptrue p0.h, vl16196; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]197; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5198; CHECK-NEXT: st1h { z0.h }, p0, [x0]199; CHECK-NEXT: ret200 %op1 = load <16 x i16>, ptr %a201 %res = sdiv <16 x i16> %op1, shufflevector (<16 x i16> insertelement (<16 x i16> poison, i16 32, i32 0), <16 x i16> poison, <16 x i32> zeroinitializer)202 store <16 x i16> %res, ptr %a203 ret void204}205 206define void @sdiv_v32i16(ptr %a) #0 {207; VBITS_GE_128-LABEL: sdiv_v32i16:208; VBITS_GE_128: // %bb.0:209; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32]210; VBITS_GE_128-NEXT: ptrue p0.h, vl8211; VBITS_GE_128-NEXT: ldp q2, q3, [x0]212; VBITS_GE_128-NEXT: asrd z0.h, p0/m, z0.h, #5213; VBITS_GE_128-NEXT: asrd z1.h, p0/m, z1.h, #5214; VBITS_GE_128-NEXT: asrd z2.h, p0/m, z2.h, #5215; VBITS_GE_128-NEXT: asrd z3.h, p0/m, z3.h, #5216; VBITS_GE_128-NEXT: stp q0, q1, [x0, #32]217; VBITS_GE_128-NEXT: stp q2, q3, [x0]218; VBITS_GE_128-NEXT: ret219;220; VBITS_GE_256-LABEL: sdiv_v32i16:221; VBITS_GE_256: // %bb.0:222; VBITS_GE_256-NEXT: ptrue p0.h, vl16223; VBITS_GE_256-NEXT: mov x8, #16 // =0x10224; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]225; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]226; VBITS_GE_256-NEXT: asrd z0.h, p0/m, z0.h, #5227; VBITS_GE_256-NEXT: asrd z1.h, p0/m, z1.h, #5228; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]229; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x0]230; VBITS_GE_256-NEXT: ret231;232; VBITS_GE_512-LABEL: sdiv_v32i16:233; VBITS_GE_512: // %bb.0:234; VBITS_GE_512-NEXT: ptrue p0.h, vl32235; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]236; VBITS_GE_512-NEXT: asrd z0.h, p0/m, z0.h, #5237; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]238; VBITS_GE_512-NEXT: ret239 %op1 = load <32 x i16>, ptr %a240 %res = sdiv <32 x i16> %op1, shufflevector (<32 x i16> insertelement (<32 x i16> poison, i16 32, i32 0), <32 x i16> poison, <32 x i32> zeroinitializer)241 store <32 x i16> %res, ptr %a242 ret void243}244 245define void @sdiv_v64i16(ptr %a) vscale_range(8,0) #0 {246; CHECK-LABEL: sdiv_v64i16:247; CHECK: // %bb.0:248; CHECK-NEXT: ptrue p0.h, vl64249; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]250; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #4251; CHECK-NEXT: subr z0.h, z0.h, #0 // =0x0252; CHECK-NEXT: st1h { z0.h }, p0, [x0]253; CHECK-NEXT: ret254 %op1 = load <64 x i16>, ptr %a255 %res = sdiv <64 x i16> %op1, shufflevector (<64 x i16> insertelement (<64 x i16> poison, i16 -16, i32 0), <64 x i16> poison, <64 x i32> zeroinitializer)256 store <64 x i16> %res, ptr %a257 ret void258}259 260define void @sdiv_v128i16(ptr %a) vscale_range(16,0) #0 {261; CHECK-LABEL: sdiv_v128i16:262; CHECK: // %bb.0:263; CHECK-NEXT: ptrue p0.h, vl128264; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]265; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5266; CHECK-NEXT: st1h { z0.h }, p0, [x0]267; CHECK-NEXT: ret268 %op1 = load <128 x i16>, ptr %a269 %res = sdiv <128 x i16> %op1, shufflevector (<128 x i16> insertelement (<128 x i16> poison, i16 32, i32 0), <128 x i16> poison, <128 x i32> zeroinitializer)270 store <128 x i16> %res, ptr %a271 ret void272}273 274define <2 x i32> @sdiv_v2i32(<2 x i32> %op1) vscale_range(2,0) #0 {275; CHECK-LABEL: sdiv_v2i32:276; CHECK: // %bb.0:277; CHECK-NEXT: ptrue p0.s, vl2278; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0279; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5280; CHECK-NEXT: subr z0.s, z0.s, #0 // =0x0281; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0282; CHECK-NEXT: ret283 %res = sdiv <2 x i32> %op1, shufflevector (<2 x i32> insertelement (<2 x i32> poison, i32 -32, i32 0), <2 x i32> poison, <2 x i32> zeroinitializer)284 ret <2 x i32> %res285}286 287define <4 x i32> @sdiv_v4i32(<4 x i32> %op1) vscale_range(2,0) #0 {288; CHECK-LABEL: sdiv_v4i32:289; CHECK: // %bb.0:290; CHECK-NEXT: ptrue p0.s, vl4291; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0292; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5293; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0294; CHECK-NEXT: ret295 %res = sdiv <4 x i32> %op1, shufflevector (<4 x i32> insertelement (<4 x i32> poison, i32 32, i32 0), <4 x i32> poison, <4 x i32> zeroinitializer)296 ret <4 x i32> %res297}298 299define void @sdiv_v8i32(ptr %a) vscale_range(2,0) #0 {300; CHECK-LABEL: sdiv_v8i32:301; CHECK: // %bb.0:302; CHECK-NEXT: ptrue p0.s, vl8303; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]304; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #6305; CHECK-NEXT: subr z0.s, z0.s, #0 // =0x0306; CHECK-NEXT: st1w { z0.s }, p0, [x0]307; CHECK-NEXT: ret308 %op1 = load <8 x i32>, ptr %a309 %res = sdiv <8 x i32> %op1, shufflevector (<8 x i32> insertelement (<8 x i32> poison, i32 -64, i32 0), <8 x i32> poison, <8 x i32> zeroinitializer)310 store <8 x i32> %res, ptr %a311 ret void312}313 314define void @sdiv_v16i32(ptr %a) #0 {315; VBITS_GE_128-LABEL: sdiv_v16i32:316; VBITS_GE_128: // %bb.0:317; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32]318; VBITS_GE_128-NEXT: ptrue p0.s, vl4319; VBITS_GE_128-NEXT: ldp q2, q3, [x0]320; VBITS_GE_128-NEXT: asrd z0.s, p0/m, z0.s, #5321; VBITS_GE_128-NEXT: asrd z1.s, p0/m, z1.s, #5322; VBITS_GE_128-NEXT: asrd z2.s, p0/m, z2.s, #5323; VBITS_GE_128-NEXT: asrd z3.s, p0/m, z3.s, #5324; VBITS_GE_128-NEXT: stp q0, q1, [x0, #32]325; VBITS_GE_128-NEXT: stp q2, q3, [x0]326; VBITS_GE_128-NEXT: ret327;328; VBITS_GE_256-LABEL: sdiv_v16i32:329; VBITS_GE_256: // %bb.0:330; VBITS_GE_256-NEXT: ptrue p0.s, vl8331; VBITS_GE_256-NEXT: mov x8, #8 // =0x8332; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]333; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]334; VBITS_GE_256-NEXT: asrd z0.s, p0/m, z0.s, #5335; VBITS_GE_256-NEXT: asrd z1.s, p0/m, z1.s, #5336; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]337; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]338; VBITS_GE_256-NEXT: ret339;340; VBITS_GE_512-LABEL: sdiv_v16i32:341; VBITS_GE_512: // %bb.0:342; VBITS_GE_512-NEXT: ptrue p0.s, vl16343; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]344; VBITS_GE_512-NEXT: asrd z0.s, p0/m, z0.s, #5345; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]346; VBITS_GE_512-NEXT: ret347 %op1 = load <16 x i32>, ptr %a348 %res = sdiv <16 x i32> %op1, shufflevector (<16 x i32> insertelement (<16 x i32> poison, i32 32, i32 0), <16 x i32> poison, <16 x i32> zeroinitializer)349 store <16 x i32> %res, ptr %a350 ret void351}352 353define void @sdiv_v32i32(ptr %a) vscale_range(8,0) #0 {354; CHECK-LABEL: sdiv_v32i32:355; CHECK: // %bb.0:356; CHECK-NEXT: ptrue p0.s, vl32357; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]358; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5359; CHECK-NEXT: st1w { z0.s }, p0, [x0]360; CHECK-NEXT: ret361 %op1 = load <32 x i32>, ptr %a362 %res = sdiv <32 x i32> %op1, shufflevector (<32 x i32> insertelement (<32 x i32> poison, i32 32, i32 0), <32 x i32> poison, <32 x i32> zeroinitializer)363 store <32 x i32> %res, ptr %a364 ret void365}366 367define void @sdiv_v64i32(ptr %a) vscale_range(16,0) #0 {368; CHECK-LABEL: sdiv_v64i32:369; CHECK: // %bb.0:370; CHECK-NEXT: ptrue p0.s, vl64371; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]372; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5373; CHECK-NEXT: st1w { z0.s }, p0, [x0]374; CHECK-NEXT: ret375 %op1 = load <64 x i32>, ptr %a376 %res = sdiv <64 x i32> %op1, shufflevector (<64 x i32> insertelement (<64 x i32> poison, i32 32, i32 0), <64 x i32> poison, <64 x i32> zeroinitializer)377 store <64 x i32> %res, ptr %a378 ret void379}380 381define <1 x i64> @sdiv_v1i64(<1 x i64> %op1) vscale_range(2,0) #0 {382; CHECK-LABEL: sdiv_v1i64:383; CHECK: // %bb.0:384; CHECK-NEXT: ptrue p0.d, vl1385; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0386; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #7387; CHECK-NEXT: subr z0.d, z0.d, #0 // =0x0388; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0389; CHECK-NEXT: ret390 %res = sdiv <1 x i64> %op1, shufflevector (<1 x i64> insertelement (<1 x i64> poison, i64 -128, i32 0), <1 x i64> poison, <1 x i32> zeroinitializer)391 ret <1 x i64> %res392}393 394; Vector i64 sdiv are not legal for NEON so use SVE when available.395define <2 x i64> @sdiv_v2i64(<2 x i64> %op1) vscale_range(2,0) #0 {396; CHECK-LABEL: sdiv_v2i64:397; CHECK: // %bb.0:398; CHECK-NEXT: ptrue p0.d, vl2399; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0400; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5401; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0402; CHECK-NEXT: ret403 %res = sdiv <2 x i64> %op1, shufflevector (<2 x i64> insertelement (<2 x i64> poison, i64 32, i32 0), <2 x i64> poison, <2 x i32> zeroinitializer)404 ret <2 x i64> %res405}406 407define void @sdiv_v4i64(ptr %a) vscale_range(2,0) #0 {408; CHECK-LABEL: sdiv_v4i64:409; CHECK: // %bb.0:410; CHECK-NEXT: ptrue p0.d, vl4411; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]412; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #8413; CHECK-NEXT: subr z0.d, z0.d, #0 // =0x0414; CHECK-NEXT: st1d { z0.d }, p0, [x0]415; CHECK-NEXT: ret416 %op1 = load <4 x i64>, ptr %a417 %res = sdiv <4 x i64> %op1, shufflevector (<4 x i64> insertelement (<4 x i64> poison, i64 -256, i32 0), <4 x i64> poison, <4 x i32> zeroinitializer)418 store <4 x i64> %res, ptr %a419 ret void420}421 422define void @sdiv_v8i64(ptr %a) #0 {423; VBITS_GE_128-LABEL: sdiv_v8i64:424; VBITS_GE_128: // %bb.0:425; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32]426; VBITS_GE_128-NEXT: ptrue p0.d, vl2427; VBITS_GE_128-NEXT: ldp q2, q3, [x0]428; VBITS_GE_128-NEXT: asrd z0.d, p0/m, z0.d, #5429; VBITS_GE_128-NEXT: asrd z1.d, p0/m, z1.d, #5430; VBITS_GE_128-NEXT: asrd z2.d, p0/m, z2.d, #5431; VBITS_GE_128-NEXT: asrd z3.d, p0/m, z3.d, #5432; VBITS_GE_128-NEXT: stp q0, q1, [x0, #32]433; VBITS_GE_128-NEXT: stp q2, q3, [x0]434; VBITS_GE_128-NEXT: ret435;436; VBITS_GE_256-LABEL: sdiv_v8i64:437; VBITS_GE_256: // %bb.0:438; VBITS_GE_256-NEXT: ptrue p0.d, vl4439; VBITS_GE_256-NEXT: mov x8, #4 // =0x4440; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]441; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]442; VBITS_GE_256-NEXT: asrd z0.d, p0/m, z0.d, #5443; VBITS_GE_256-NEXT: asrd z1.d, p0/m, z1.d, #5444; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]445; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]446; VBITS_GE_256-NEXT: ret447;448; VBITS_GE_512-LABEL: sdiv_v8i64:449; VBITS_GE_512: // %bb.0:450; VBITS_GE_512-NEXT: ptrue p0.d, vl8451; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]452; VBITS_GE_512-NEXT: asrd z0.d, p0/m, z0.d, #5453; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]454; VBITS_GE_512-NEXT: ret455 %op1 = load <8 x i64>, ptr %a456 %res = sdiv <8 x i64> %op1, shufflevector (<8 x i64> insertelement (<8 x i64> poison, i64 32, i32 0), <8 x i64> poison, <8 x i32> zeroinitializer)457 store <8 x i64> %res, ptr %a458 ret void459}460 461define void @sdiv_v16i64(ptr %a) vscale_range(8,0) #0 {462; CHECK-LABEL: sdiv_v16i64:463; CHECK: // %bb.0:464; CHECK-NEXT: ptrue p0.d, vl16465; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]466; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5467; CHECK-NEXT: st1d { z0.d }, p0, [x0]468; CHECK-NEXT: ret469 %op1 = load <16 x i64>, ptr %a470 %res = sdiv <16 x i64> %op1, shufflevector (<16 x i64> insertelement (<16 x i64> poison, i64 32, i32 0), <16 x i64> poison, <16 x i32> zeroinitializer)471 store <16 x i64> %res, ptr %a472 ret void473}474 475define void @sdiv_v32i64(ptr %a) vscale_range(16,0) #0 {476; CHECK-LABEL: sdiv_v32i64:477; CHECK: // %bb.0:478; CHECK-NEXT: ptrue p0.d, vl32479; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]480; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #9481; CHECK-NEXT: subr z0.d, z0.d, #0 // =0x0482; CHECK-NEXT: st1d { z0.d }, p0, [x0]483; CHECK-NEXT: ret484 %op1 = load <32 x i64>, ptr %a485 %res = sdiv <32 x i64> %op1, shufflevector (<32 x i64> insertelement (<32 x i64> poison, i64 -512, i32 0), <32 x i64> poison, <32 x i32> zeroinitializer)486 store <32 x i64> %res, ptr %a487 ret void488}489 490attributes #0 = { "target-features"="+sve" }491