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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s3 4;; Patterns that lower to concat_vectors where all incoming operands are the same.5 6define void @concat_i8q_256(<16 x i8> %data, ptr %addr) #0 {7; CHECK-LABEL: concat_i8q_256:8; CHECK: // %bb.0:9; CHECK-NEXT: // kill: def $q0 killed $q0 def $z010; CHECK-NEXT: mov z0.q, q011; CHECK-NEXT: str z0, [x0]12; CHECK-NEXT: ret13 %splat = shufflevector <16 x i8> %data, <16 x i8> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15,14 i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>15 store <32 x i8> %splat, ptr %addr, align 116 ret void17}18 19define void @concat_i16q_256(<8 x i16> %data, ptr %addr) #0 {20; CHECK-LABEL: concat_i16q_256:21; CHECK: // %bb.0:22; CHECK-NEXT: // kill: def $q0 killed $q0 def $z023; CHECK-NEXT: mov z0.q, q024; CHECK-NEXT: str z0, [x0]25; CHECK-NEXT: ret26 %splat = shufflevector <8 x i16> %data, <8 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,27 i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>28 store <16 x i16> %splat, ptr %addr, align 129 ret void30}31 32define void @concat_i32q_256(<4 x i32> %data, ptr %addr) #0 {33; CHECK-LABEL: concat_i32q_256:34; CHECK: // %bb.0:35; CHECK-NEXT: // kill: def $q0 killed $q0 def $z036; CHECK-NEXT: mov z0.q, q037; CHECK-NEXT: str z0, [x0]38; CHECK-NEXT: ret39 %splat = shufflevector <4 x i32> %data, <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3,40 i32 0, i32 1, i32 2, i32 3>41 store <8 x i32> %splat, ptr %addr, align 142 ret void43}44 45define void @concat_i64q_256(<2 x i64> %data, ptr %addr) #0 {46; CHECK-LABEL: concat_i64q_256:47; CHECK: // %bb.0:48; CHECK-NEXT: // kill: def $q0 killed $q0 def $z049; CHECK-NEXT: mov z0.q, q050; CHECK-NEXT: str z0, [x0]51; CHECK-NEXT: ret52 %splat = shufflevector <2 x i64> %data, <2 x i64> poison, <4 x i32> <i32 0, i32 1,53 i32 0, i32 1>54 store <4 x i64> %splat, ptr %addr, align 155 ret void56}57 58define void @concat_f16q_256(<8 x half> %data, ptr %addr) #0 {59; CHECK-LABEL: concat_f16q_256:60; CHECK: // %bb.0:61; CHECK-NEXT: // kill: def $q0 killed $q0 def $z062; CHECK-NEXT: mov z0.q, q063; CHECK-NEXT: str z0, [x0]64; CHECK-NEXT: ret65 %splat = shufflevector <8 x half> %data, <8 x half> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,66 i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>67 store <16 x half> %splat, ptr %addr, align 168 ret void69}70 71define void @concat_bf16q_256(<8 x bfloat> %data, ptr %addr) #0 {72; CHECK-LABEL: concat_bf16q_256:73; CHECK: // %bb.0:74; CHECK-NEXT: stp q0, q0, [x0]75; CHECK-NEXT: ret76 %splat = shufflevector <8 x bfloat> %data, <8 x bfloat> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,77 i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>78 store <16 x bfloat> %splat, ptr %addr, align 179 ret void80}81 82define void @concat_f32q_256(<4 x float> %data, ptr %addr) #0 {83; CHECK-LABEL: concat_f32q_256:84; CHECK: // %bb.0:85; CHECK-NEXT: // kill: def $q0 killed $q0 def $z086; CHECK-NEXT: mov z0.q, q087; CHECK-NEXT: str z0, [x0]88; CHECK-NEXT: ret89 %splat = shufflevector <4 x float> %data, <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3,90 i32 0, i32 1, i32 2, i32 3>91 store <8 x float> %splat, ptr %addr, align 192 ret void93}94 95define void @concat_f64q_256(<2 x double> %data, ptr %addr) #0 {96; CHECK-LABEL: concat_f64q_256:97; CHECK: // %bb.0:98; CHECK-NEXT: // kill: def $q0 killed $q0 def $z099; CHECK-NEXT: mov z0.q, q0100; CHECK-NEXT: str z0, [x0]101; CHECK-NEXT: ret102 %splat = shufflevector <2 x double> %data, <2 x double> poison, <4 x i32> <i32 0, i32 1,103 i32 0, i32 1>104 store <4 x double> %splat, ptr %addr, align 1105 ret void106}107 108;; Test a wider vector109 110define void @concat_i32q_512_with_256_vectors(<4 x i32> %data, ptr %addr) #0 {111; CHECK-LABEL: concat_i32q_512_with_256_vectors:112; CHECK: // %bb.0:113; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0114; CHECK-NEXT: mov z0.q, q0115; CHECK-NEXT: str z0, [x0, #1, mul vl]116; CHECK-NEXT: str z0, [x0]117; CHECK-NEXT: ret118 %splat = shufflevector <4 x i32> %data, <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3,119 i32 0, i32 1, i32 2, i32 3,120 i32 0, i32 1, i32 2, i32 3,121 i32 0, i32 1, i32 2, i32 3>122 store <16 x i32> %splat, ptr %addr, align 1123 ret void124}125 126define void @concat_i32q_512_with_512_vectors(<4 x i32> %data, ptr %addr) #1 {127; CHECK-LABEL: concat_i32q_512_with_512_vectors:128; CHECK: // %bb.0:129; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0130; CHECK-NEXT: mov z0.q, q0131; CHECK-NEXT: str z0, [x0]132; CHECK-NEXT: ret133 %splat = shufflevector <4 x i32> %data, <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3,134 i32 0, i32 1, i32 2, i32 3,135 i32 0, i32 1, i32 2, i32 3,136 i32 0, i32 1, i32 2, i32 3>137 store <16 x i32> %splat, ptr %addr, align 1138 ret void139}140 141attributes #0 = { vscale_range(2,2) "target-features"="+sve,+bf16" }142attributes #1 = { vscale_range(4,4) "target-features"="+sve,+bf16" }143