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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 -mattr=+sve -aarch64-sve-vector-bits-min=256 | FileCheck %s3 4define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) nounwind {5; CHECK-LABEL: llrint_v1i64_v1f16:6; CHECK: // %bb.0:7; CHECK-NEXT: frintx h0, h08; CHECK-NEXT: fcvtzs x8, h09; CHECK-NEXT: fmov d0, x810; CHECK-NEXT: ret11 %a = call <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half> %x)12 ret <1 x i64> %a13}14declare <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half>)15 16define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) nounwind {17; CHECK-LABEL: llrint_v1i64_v2f16:18; CHECK: // %bb.0:19; CHECK-NEXT: // kill: def $d0 killed $d0 def $q020; CHECK-NEXT: mov h1, v0.h[1]21; CHECK-NEXT: frintx h0, h022; CHECK-NEXT: frintx h1, h123; CHECK-NEXT: fcvtzs x8, h024; CHECK-NEXT: fcvtzs x9, h125; CHECK-NEXT: fmov d0, x826; CHECK-NEXT: mov v0.d[1], x927; CHECK-NEXT: ret28 %a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x)29 ret <2 x i64> %a30}31declare <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half>)32 33define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) nounwind {34; CHECK-LABEL: llrint_v4i64_v4f16:35; CHECK: // %bb.0:36; CHECK-NEXT: frintx v0.4h, v0.4h37; CHECK-NEXT: mov h1, v0.h[2]38; CHECK-NEXT: mov h2, v0.h[3]39; CHECK-NEXT: mov h3, v0.h[1]40; CHECK-NEXT: fcvtzs x9, h041; CHECK-NEXT: fcvtzs x8, h142; CHECK-NEXT: fcvtzs x10, h243; CHECK-NEXT: fcvtzs x11, h344; CHECK-NEXT: fmov d0, x945; CHECK-NEXT: fmov d1, x846; CHECK-NEXT: mov v0.d[1], x1147; CHECK-NEXT: mov v1.d[1], x1048; CHECK-NEXT: ret49 %a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x)50 ret <4 x i64> %a51}52declare <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half>)53 54define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) nounwind {55; CHECK-LABEL: llrint_v8i64_v8f16:56; CHECK: // %bb.0:57; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #858; CHECK-NEXT: frintx v0.4h, v0.4h59; CHECK-NEXT: frintx v1.4h, v1.4h60; CHECK-NEXT: mov h4, v0.h[2]61; CHECK-NEXT: mov h2, v0.h[1]62; CHECK-NEXT: mov h7, v0.h[3]63; CHECK-NEXT: fcvtzs x8, h064; CHECK-NEXT: mov h3, v1.h[2]65; CHECK-NEXT: mov h5, v1.h[3]66; CHECK-NEXT: mov h6, v1.h[1]67; CHECK-NEXT: fcvtzs x11, h168; CHECK-NEXT: fcvtzs x12, h469; CHECK-NEXT: fcvtzs x9, h270; CHECK-NEXT: fcvtzs x15, h771; CHECK-NEXT: fmov d0, x872; CHECK-NEXT: fcvtzs x10, h373; CHECK-NEXT: fcvtzs x13, h574; CHECK-NEXT: fcvtzs x14, h675; CHECK-NEXT: fmov d1, x1276; CHECK-NEXT: fmov d2, x1177; CHECK-NEXT: mov v0.d[1], x978; CHECK-NEXT: fmov d3, x1079; CHECK-NEXT: mov v1.d[1], x1580; CHECK-NEXT: mov v2.d[1], x1481; CHECK-NEXT: mov v3.d[1], x1382; CHECK-NEXT: ret83 %a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x)84 ret <8 x i64> %a85}86declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)87 88define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) nounwind {89; CHECK-LABEL: llrint_v16i64_v16f16:90; CHECK: // %bb.0:91; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #892; CHECK-NEXT: frintx v1.4h, v1.4h93; CHECK-NEXT: frintx v3.4h, v0.4h94; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #895; CHECK-NEXT: frintx v2.4h, v2.4h96; CHECK-NEXT: mov h4, v1.h[2]97; CHECK-NEXT: mov h5, v3.h[2]98; CHECK-NEXT: frintx v0.4h, v0.4h99; CHECK-NEXT: mov h6, v3.h[1]100; CHECK-NEXT: fcvtzs x9, h3101; CHECK-NEXT: mov h16, v1.h[1]102; CHECK-NEXT: fcvtzs x12, h1103; CHECK-NEXT: mov h3, v3.h[3]104; CHECK-NEXT: mov h17, v1.h[3]105; CHECK-NEXT: mov h7, v2.h[3]106; CHECK-NEXT: fcvtzs x8, h4107; CHECK-NEXT: fcvtzs x10, h5108; CHECK-NEXT: mov h4, v2.h[2]109; CHECK-NEXT: mov h5, v0.h[2]110; CHECK-NEXT: fcvtzs x11, h6111; CHECK-NEXT: mov h6, v0.h[3]112; CHECK-NEXT: fcvtzs x15, h2113; CHECK-NEXT: mov h2, v2.h[1]114; CHECK-NEXT: fcvtzs x14, h0115; CHECK-NEXT: fcvtzs x17, h3116; CHECK-NEXT: fcvtzs x0, h17117; CHECK-NEXT: fcvtzs x13, h7118; CHECK-NEXT: mov h7, v0.h[1]119; CHECK-NEXT: fmov d0, x9120; CHECK-NEXT: fcvtzs x16, h4121; CHECK-NEXT: fcvtzs x9, h5122; CHECK-NEXT: fmov d4, x12123; CHECK-NEXT: fcvtzs x12, h16124; CHECK-NEXT: fmov d1, x10125; CHECK-NEXT: fcvtzs x10, h6126; CHECK-NEXT: fmov d5, x8127; CHECK-NEXT: fcvtzs x8, h2128; CHECK-NEXT: fmov d2, x14129; CHECK-NEXT: fcvtzs x18, h7130; CHECK-NEXT: fmov d6, x15131; CHECK-NEXT: mov v0.d[1], x11132; CHECK-NEXT: fmov d3, x9133; CHECK-NEXT: fmov d7, x16134; CHECK-NEXT: mov v1.d[1], x17135; CHECK-NEXT: mov v4.d[1], x12136; CHECK-NEXT: mov v5.d[1], x0137; CHECK-NEXT: mov v6.d[1], x8138; CHECK-NEXT: mov v2.d[1], x18139; CHECK-NEXT: mov v3.d[1], x10140; CHECK-NEXT: mov v7.d[1], x13141; CHECK-NEXT: ret142 %a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)143 ret <16 x i64> %a144}145declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>)146 147define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) nounwind {148; CHECK-LABEL: llrint_v32i64_v32f16:149; CHECK: // %bb.0:150; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill151; CHECK-NEXT: sub x9, sp, #272152; CHECK-NEXT: mov x29, sp153; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0154; CHECK-NEXT: frintx v5.4h, v0.4h155; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8156; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8157; CHECK-NEXT: ext v17.16b, v2.16b, v2.16b, #8158; CHECK-NEXT: frintx v1.4h, v1.4h159; CHECK-NEXT: frintx v2.4h, v2.4h160; CHECK-NEXT: ptrue p0.d, vl4161; CHECK-NEXT: mov h6, v5.h[3]162; CHECK-NEXT: frintx v0.4h, v0.4h163; CHECK-NEXT: mov h7, v5.h[2]164; CHECK-NEXT: mov h16, v5.h[1]165; CHECK-NEXT: frintx v4.4h, v4.4h166; CHECK-NEXT: fcvtzs x12, h5167; CHECK-NEXT: ext v5.16b, v3.16b, v3.16b, #8168; CHECK-NEXT: frintx v17.4h, v17.4h169; CHECK-NEXT: frintx v3.4h, v3.4h170; CHECK-NEXT: fcvtzs x9, h6171; CHECK-NEXT: mov h6, v0.h[3]172; CHECK-NEXT: fcvtzs x10, h7173; CHECK-NEXT: mov h7, v0.h[2]174; CHECK-NEXT: fcvtzs x11, h16175; CHECK-NEXT: mov h16, v0.h[1]176; CHECK-NEXT: fcvtzs x13, h6177; CHECK-NEXT: mov h6, v4.h[3]178; CHECK-NEXT: stp x10, x9, [sp, #48]179; CHECK-NEXT: fcvtzs x9, h7180; CHECK-NEXT: mov h7, v4.h[2]181; CHECK-NEXT: fcvtzs x10, h16182; CHECK-NEXT: mov h16, v4.h[1]183; CHECK-NEXT: stp x12, x11, [sp, #32]184; CHECK-NEXT: fcvtzs x11, h0185; CHECK-NEXT: frintx v0.4h, v5.4h186; CHECK-NEXT: mov h5, v17.h[3]187; CHECK-NEXT: fcvtzs x12, h6188; CHECK-NEXT: mov h6, v17.h[2]189; CHECK-NEXT: stp x9, x13, [sp, #16]190; CHECK-NEXT: fcvtzs x13, h7191; CHECK-NEXT: mov h7, v17.h[1]192; CHECK-NEXT: fcvtzs x9, h16193; CHECK-NEXT: stp x11, x10, [sp]194; CHECK-NEXT: fcvtzs x10, h4195; CHECK-NEXT: fcvtzs x11, h5196; CHECK-NEXT: mov h4, v0.h[3]197; CHECK-NEXT: mov h5, v0.h[2]198; CHECK-NEXT: stp x13, x12, [sp, #80]199; CHECK-NEXT: fcvtzs x12, h6200; CHECK-NEXT: fcvtzs x13, h7201; CHECK-NEXT: mov h6, v0.h[1]202; CHECK-NEXT: stp x10, x9, [sp, #64]203; CHECK-NEXT: fcvtzs x9, h17204; CHECK-NEXT: mov h7, v1.h[3]205; CHECK-NEXT: fcvtzs x10, h4206; CHECK-NEXT: mov h4, v1.h[2]207; CHECK-NEXT: stp x12, x11, [sp, #144]208; CHECK-NEXT: fcvtzs x11, h5209; CHECK-NEXT: mov h5, v1.h[1]210; CHECK-NEXT: fcvtzs x12, h6211; CHECK-NEXT: stp x9, x13, [sp, #128]212; CHECK-NEXT: fcvtzs x9, h0213; CHECK-NEXT: fcvtzs x13, h7214; CHECK-NEXT: mov h0, v2.h[3]215; CHECK-NEXT: stp x11, x10, [sp, #208]216; CHECK-NEXT: fcvtzs x10, h4217; CHECK-NEXT: mov h4, v2.h[2]218; CHECK-NEXT: fcvtzs x11, h5219; CHECK-NEXT: mov h5, v2.h[1]220; CHECK-NEXT: stp x9, x12, [sp, #192]221; CHECK-NEXT: fcvtzs x9, h1222; CHECK-NEXT: fcvtzs x12, h0223; CHECK-NEXT: mov h0, v3.h[3]224; CHECK-NEXT: mov h1, v3.h[2]225; CHECK-NEXT: stp x10, x13, [sp, #112]226; CHECK-NEXT: fcvtzs x10, h4227; CHECK-NEXT: mov h4, v3.h[1]228; CHECK-NEXT: fcvtzs x13, h5229; CHECK-NEXT: stp x9, x11, [sp, #96]230; CHECK-NEXT: fcvtzs x9, h2231; CHECK-NEXT: fcvtzs x11, h0232; CHECK-NEXT: stp x10, x12, [sp, #176]233; CHECK-NEXT: fcvtzs x10, h1234; CHECK-NEXT: fcvtzs x12, h4235; CHECK-NEXT: stp x9, x13, [sp, #160]236; CHECK-NEXT: fcvtzs x9, h3237; CHECK-NEXT: stp x10, x11, [sp, #240]238; CHECK-NEXT: add x10, sp, #64239; CHECK-NEXT: stp x9, x12, [sp, #224]240; CHECK-NEXT: add x9, sp, #32241; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9]242; CHECK-NEXT: mov x9, sp243; CHECK-NEXT: ld1d { z2.d }, p0/z, [x10]244; CHECK-NEXT: ld1d { z1.d }, p0/z, [x9]245; CHECK-NEXT: add x9, sp, #224246; CHECK-NEXT: add x10, sp, #128247; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]248; CHECK-NEXT: add x9, sp, #160249; CHECK-NEXT: ld1d { z4.d }, p0/z, [x10]250; CHECK-NEXT: add x10, sp, #96251; CHECK-NEXT: ld1d { z5.d }, p0/z, [x9]252; CHECK-NEXT: add x9, sp, #192253; CHECK-NEXT: ld1d { z6.d }, p0/z, [x10]254; CHECK-NEXT: mov x10, #24 // =0x18255; CHECK-NEXT: ld1d { z7.d }, p0/z, [x9]256; CHECK-NEXT: mov x9, #16 // =0x10257; CHECK-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]258; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]259; CHECK-NEXT: mov x9, #8 // =0x8260; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]261; CHECK-NEXT: mov x9, #28 // =0x1c262; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]263; CHECK-NEXT: mov x9, #20 // =0x14264; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]265; CHECK-NEXT: mov x9, #12 // =0xc266; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]267; CHECK-NEXT: mov x9, #4 // =0x4268; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]269; CHECK-NEXT: st1d { z0.d }, p0, [x8]270; CHECK-NEXT: mov sp, x29271; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload272; CHECK-NEXT: ret273 %a = call <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half> %x)274 ret <32 x i64> %a275}276declare <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half>)277 278define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) nounwind {279; CHECK-LABEL: llrint_v1i64_v1f32:280; CHECK: // %bb.0:281; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0282; CHECK-NEXT: frintx s0, s0283; CHECK-NEXT: fcvtzs x8, s0284; CHECK-NEXT: fmov d0, x8285; CHECK-NEXT: ret286 %a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x)287 ret <1 x i64> %a288}289declare <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float>)290 291define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) nounwind {292; CHECK-LABEL: llrint_v2i64_v2f32:293; CHECK: // %bb.0:294; CHECK-NEXT: frintx v0.2s, v0.2s295; CHECK-NEXT: fcvtl v0.2d, v0.2s296; CHECK-NEXT: fcvtzs v0.2d, v0.2d297; CHECK-NEXT: ret298 %a = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> %x)299 ret <2 x i64> %a300}301declare <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float>)302 303define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) nounwind {304; CHECK-LABEL: llrint_v4i64_v4f32:305; CHECK: // %bb.0:306; CHECK-NEXT: frintx v0.4s, v0.4s307; CHECK-NEXT: mov s1, v0.s[2]308; CHECK-NEXT: mov s2, v0.s[3]309; CHECK-NEXT: mov s3, v0.s[1]310; CHECK-NEXT: fcvtzs x9, s0311; CHECK-NEXT: fcvtzs x8, s1312; CHECK-NEXT: fcvtzs x10, s2313; CHECK-NEXT: fcvtzs x11, s3314; CHECK-NEXT: fmov d0, x9315; CHECK-NEXT: fmov d1, x8316; CHECK-NEXT: mov v0.d[1], x11317; CHECK-NEXT: mov v1.d[1], x10318; CHECK-NEXT: ret319 %a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x)320 ret <4 x i64> %a321}322declare <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float>)323 324define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) nounwind {325; CHECK-LABEL: llrint_v8i64_v8f32:326; CHECK: // %bb.0:327; CHECK-NEXT: frintx v0.4s, v0.4s328; CHECK-NEXT: frintx v1.4s, v1.4s329; CHECK-NEXT: mov s3, v1.s[2]330; CHECK-NEXT: mov s4, v0.s[2]331; CHECK-NEXT: mov s2, v0.s[1]332; CHECK-NEXT: mov s5, v1.s[3]333; CHECK-NEXT: mov s6, v1.s[1]334; CHECK-NEXT: mov s7, v0.s[3]335; CHECK-NEXT: fcvtzs x8, s0336; CHECK-NEXT: fcvtzs x10, s1337; CHECK-NEXT: fcvtzs x11, s3338; CHECK-NEXT: fcvtzs x12, s4339; CHECK-NEXT: fcvtzs x9, s2340; CHECK-NEXT: fcvtzs x13, s5341; CHECK-NEXT: fcvtzs x14, s6342; CHECK-NEXT: fcvtzs x15, s7343; CHECK-NEXT: fmov d0, x8344; CHECK-NEXT: fmov d2, x10345; CHECK-NEXT: fmov d1, x12346; CHECK-NEXT: fmov d3, x11347; CHECK-NEXT: mov v0.d[1], x9348; CHECK-NEXT: mov v2.d[1], x14349; CHECK-NEXT: mov v1.d[1], x15350; CHECK-NEXT: mov v3.d[1], x13351; CHECK-NEXT: ret352 %a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x)353 ret <8 x i64> %a354}355declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)356 357define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) nounwind {358; CHECK-LABEL: llrint_v16i64_v16f32:359; CHECK: // %bb.0:360; CHECK-NEXT: frintx v3.4s, v3.4s361; CHECK-NEXT: frintx v2.4s, v2.4s362; CHECK-NEXT: frintx v1.4s, v1.4s363; CHECK-NEXT: frintx v0.4s, v0.4s364; CHECK-NEXT: mov s4, v3.s[2]365; CHECK-NEXT: mov s5, v2.s[2]366; CHECK-NEXT: mov s6, v1.s[2]367; CHECK-NEXT: mov s7, v0.s[2]368; CHECK-NEXT: fcvtzs x10, s1369; CHECK-NEXT: fcvtzs x11, s0370; CHECK-NEXT: mov s16, v0.s[1]371; CHECK-NEXT: mov s17, v1.s[1]372; CHECK-NEXT: mov s18, v3.s[1]373; CHECK-NEXT: fcvtzs x14, s3374; CHECK-NEXT: fcvtzs x16, s2375; CHECK-NEXT: fcvtzs x8, s4376; CHECK-NEXT: mov s4, v2.s[1]377; CHECK-NEXT: fcvtzs x9, s5378; CHECK-NEXT: mov s5, v1.s[3]379; CHECK-NEXT: fcvtzs x12, s6380; CHECK-NEXT: mov s6, v0.s[3]381; CHECK-NEXT: fcvtzs x13, s7382; CHECK-NEXT: mov s7, v3.s[3]383; CHECK-NEXT: fmov d0, x11384; CHECK-NEXT: fcvtzs x17, s16385; CHECK-NEXT: fcvtzs x18, s18386; CHECK-NEXT: fcvtzs x15, s4387; CHECK-NEXT: mov s4, v2.s[3]388; CHECK-NEXT: fmov d2, x10389; CHECK-NEXT: fcvtzs x11, s5390; CHECK-NEXT: fcvtzs x10, s6391; CHECK-NEXT: fmov d3, x12392; CHECK-NEXT: fmov d1, x13393; CHECK-NEXT: fcvtzs x12, s17394; CHECK-NEXT: fcvtzs x13, s7395; CHECK-NEXT: fmov d5, x9396; CHECK-NEXT: fmov d6, x14397; CHECK-NEXT: fmov d7, x8398; CHECK-NEXT: fcvtzs x0, s4399; CHECK-NEXT: fmov d4, x16400; CHECK-NEXT: mov v0.d[1], x17401; CHECK-NEXT: mov v1.d[1], x10402; CHECK-NEXT: mov v3.d[1], x11403; CHECK-NEXT: mov v2.d[1], x12404; CHECK-NEXT: mov v6.d[1], x18405; CHECK-NEXT: mov v7.d[1], x13406; CHECK-NEXT: mov v4.d[1], x15407; CHECK-NEXT: mov v5.d[1], x0408; CHECK-NEXT: ret409 %a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x)410 ret <16 x i64> %a411}412declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)413 414define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) nounwind {415; CHECK-LABEL: llrint_v32i64_v32f32:416; CHECK: // %bb.0:417; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill418; CHECK-NEXT: sub x9, sp, #272419; CHECK-NEXT: mov x29, sp420; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0421; CHECK-NEXT: frintx v0.4s, v0.4s422; CHECK-NEXT: frintx v1.4s, v1.4s423; CHECK-NEXT: frintx v2.4s, v2.4s424; CHECK-NEXT: ptrue p0.d, vl4425; CHECK-NEXT: mov s16, v0.s[3]426; CHECK-NEXT: mov s17, v0.s[2]427; CHECK-NEXT: mov s18, v0.s[1]428; CHECK-NEXT: fcvtzs x12, s0429; CHECK-NEXT: frintx v0.4s, v3.4s430; CHECK-NEXT: mov s3, v2.s[3]431; CHECK-NEXT: fcvtzs x9, s16432; CHECK-NEXT: mov s16, v1.s[3]433; CHECK-NEXT: fcvtzs x10, s17434; CHECK-NEXT: mov s17, v1.s[2]435; CHECK-NEXT: fcvtzs x11, s18436; CHECK-NEXT: mov s18, v1.s[1]437; CHECK-NEXT: fcvtzs x13, s16438; CHECK-NEXT: stp x10, x9, [sp, #16]439; CHECK-NEXT: mov s16, v2.s[2]440; CHECK-NEXT: fcvtzs x9, s17441; CHECK-NEXT: fcvtzs x10, s18442; CHECK-NEXT: mov s17, v2.s[1]443; CHECK-NEXT: stp x12, x11, [sp]444; CHECK-NEXT: fcvtzs x11, s1445; CHECK-NEXT: frintx v1.4s, v4.4s446; CHECK-NEXT: fcvtzs x12, s3447; CHECK-NEXT: mov s3, v0.s[3]448; CHECK-NEXT: mov s4, v0.s[2]449; CHECK-NEXT: stp x9, x13, [sp, #48]450; CHECK-NEXT: fcvtzs x13, s16451; CHECK-NEXT: fcvtzs x9, s17452; CHECK-NEXT: mov s16, v0.s[1]453; CHECK-NEXT: stp x11, x10, [sp, #32]454; CHECK-NEXT: fcvtzs x10, s2455; CHECK-NEXT: frintx v2.4s, v5.4s456; CHECK-NEXT: fcvtzs x11, s3457; CHECK-NEXT: mov s3, v1.s[3]458; CHECK-NEXT: mov s5, v1.s[1]459; CHECK-NEXT: stp x13, x12, [sp, #80]460; CHECK-NEXT: fcvtzs x12, s4461; CHECK-NEXT: mov s4, v1.s[2]462; CHECK-NEXT: fcvtzs x13, s16463; CHECK-NEXT: stp x10, x9, [sp, #64]464; CHECK-NEXT: fcvtzs x9, s0465; CHECK-NEXT: mov s0, v2.s[3]466; CHECK-NEXT: fcvtzs x10, s3467; CHECK-NEXT: frintx v3.4s, v6.4s468; CHECK-NEXT: stp x12, x11, [sp, #112]469; CHECK-NEXT: fcvtzs x11, s4470; CHECK-NEXT: mov s4, v2.s[2]471; CHECK-NEXT: fcvtzs x12, s5472; CHECK-NEXT: mov s5, v2.s[1]473; CHECK-NEXT: stp x9, x13, [sp, #96]474; CHECK-NEXT: fcvtzs x9, s1475; CHECK-NEXT: fcvtzs x13, s0476; CHECK-NEXT: mov s0, v3.s[3]477; CHECK-NEXT: frintx v1.4s, v7.4s478; CHECK-NEXT: stp x11, x10, [sp, #144]479; CHECK-NEXT: fcvtzs x10, s4480; CHECK-NEXT: mov s4, v3.s[2]481; CHECK-NEXT: fcvtzs x11, s5482; CHECK-NEXT: mov s5, v3.s[1]483; CHECK-NEXT: stp x9, x12, [sp, #128]484; CHECK-NEXT: fcvtzs x9, s2485; CHECK-NEXT: fcvtzs x12, s0486; CHECK-NEXT: mov s0, v1.s[3]487; CHECK-NEXT: mov s2, v1.s[2]488; CHECK-NEXT: stp x10, x13, [sp, #176]489; CHECK-NEXT: fcvtzs x10, s4490; CHECK-NEXT: mov s4, v1.s[1]491; CHECK-NEXT: fcvtzs x13, s5492; CHECK-NEXT: stp x9, x11, [sp, #160]493; CHECK-NEXT: fcvtzs x9, s3494; CHECK-NEXT: fcvtzs x11, s0495; CHECK-NEXT: stp x10, x12, [sp, #208]496; CHECK-NEXT: fcvtzs x10, s2497; CHECK-NEXT: fcvtzs x12, s4498; CHECK-NEXT: stp x9, x13, [sp, #192]499; CHECK-NEXT: fcvtzs x9, s1500; CHECK-NEXT: stp x10, x11, [sp, #240]501; CHECK-NEXT: add x10, sp, #64502; CHECK-NEXT: stp x9, x12, [sp, #224]503; CHECK-NEXT: mov x9, sp504; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9]505; CHECK-NEXT: add x9, sp, #32506; CHECK-NEXT: ld1d { z2.d }, p0/z, [x10]507; CHECK-NEXT: ld1d { z1.d }, p0/z, [x9]508; CHECK-NEXT: add x9, sp, #224509; CHECK-NEXT: add x10, sp, #96510; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]511; CHECK-NEXT: add x9, sp, #192512; CHECK-NEXT: ld1d { z4.d }, p0/z, [x10]513; CHECK-NEXT: add x10, sp, #160514; CHECK-NEXT: ld1d { z5.d }, p0/z, [x9]515; CHECK-NEXT: add x9, sp, #128516; CHECK-NEXT: ld1d { z6.d }, p0/z, [x10]517; CHECK-NEXT: mov x10, #28 // =0x1c518; CHECK-NEXT: ld1d { z7.d }, p0/z, [x9]519; CHECK-NEXT: mov x9, #24 // =0x18520; CHECK-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]521; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]522; CHECK-NEXT: mov x9, #20 // =0x14523; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]524; CHECK-NEXT: mov x9, #16 // =0x10525; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]526; CHECK-NEXT: mov x9, #12 // =0xc527; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]528; CHECK-NEXT: mov x9, #8 // =0x8529; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]530; CHECK-NEXT: mov x9, #4 // =0x4531; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]532; CHECK-NEXT: st1d { z0.d }, p0, [x8]533; CHECK-NEXT: mov sp, x29534; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload535; CHECK-NEXT: ret536 %a = call <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float> %x)537 ret <32 x i64> %a538}539declare <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float>)540 541define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) nounwind {542; CHECK-LABEL: llrint_v1i64_v1f64:543; CHECK: // %bb.0:544; CHECK-NEXT: frintx d0, d0545; CHECK-NEXT: fcvtzs x8, d0546; CHECK-NEXT: fmov d0, x8547; CHECK-NEXT: ret548 %a = call <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double> %x)549 ret <1 x i64> %a550}551declare <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double>)552 553define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) nounwind {554; CHECK-LABEL: llrint_v2i64_v2f64:555; CHECK: // %bb.0:556; CHECK-NEXT: frintx v0.2d, v0.2d557; CHECK-NEXT: fcvtzs v0.2d, v0.2d558; CHECK-NEXT: ret559 %a = call <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double> %x)560 ret <2 x i64> %a561}562declare <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double>)563 564define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) nounwind {565; CHECK-LABEL: llrint_v4i64_v4f64:566; CHECK: // %bb.0:567; CHECK-NEXT: ptrue p0.d, vl2568; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0569; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1570; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d571; CHECK-NEXT: ptrue p0.d, vl4572; CHECK-NEXT: frintx z0.d, p0/m, z0.d573; CHECK-NEXT: mov z1.d, z0.d[2]574; CHECK-NEXT: mov z2.d, z0.d[3]575; CHECK-NEXT: mov z3.d, z0.d[1]576; CHECK-NEXT: fcvtzs x9, d0577; CHECK-NEXT: fcvtzs x8, d1578; CHECK-NEXT: fcvtzs x10, d2579; CHECK-NEXT: fcvtzs x11, d3580; CHECK-NEXT: fmov d0, x9581; CHECK-NEXT: fmov d1, x8582; CHECK-NEXT: mov v0.d[1], x11583; CHECK-NEXT: mov v1.d[1], x10584; CHECK-NEXT: ret585 %a = call <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double> %x)586 ret <4 x i64> %a587}588declare <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double>)589 590define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) nounwind {591; CHECK-LABEL: llrint_v8i64_v8f64:592; CHECK: // %bb.0:593; CHECK-NEXT: ptrue p0.d, vl2594; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2595; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0596; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3597; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1598; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d599; CHECK-NEXT: splice z2.d, p0, z2.d, z3.d600; CHECK-NEXT: ptrue p0.d, vl4601; CHECK-NEXT: frintx z0.d, p0/m, z0.d602; CHECK-NEXT: movprfx z1, z2603; CHECK-NEXT: frintx z1.d, p0/m, z2.d604; CHECK-NEXT: mov z4.d, z1.d[2]605; CHECK-NEXT: mov z5.d, z0.d[2]606; CHECK-NEXT: mov z2.d, z0.d[1]607; CHECK-NEXT: mov z3.d, z1.d[3]608; CHECK-NEXT: mov z6.d, z0.d[3]609; CHECK-NEXT: fcvtzs x8, d0610; CHECK-NEXT: mov z0.d, z1.d[1]611; CHECK-NEXT: fcvtzs x10, d1612; CHECK-NEXT: fcvtzs x11, d4613; CHECK-NEXT: fcvtzs x12, d5614; CHECK-NEXT: fcvtzs x9, d2615; CHECK-NEXT: fcvtzs x13, d3616; CHECK-NEXT: fcvtzs x14, d6617; CHECK-NEXT: fcvtzs x15, d0618; CHECK-NEXT: fmov d0, x8619; CHECK-NEXT: fmov d2, x10620; CHECK-NEXT: fmov d1, x12621; CHECK-NEXT: fmov d3, x11622; CHECK-NEXT: mov v0.d[1], x9623; CHECK-NEXT: mov v2.d[1], x15624; CHECK-NEXT: mov v1.d[1], x14625; CHECK-NEXT: mov v3.d[1], x13626; CHECK-NEXT: ret627 %a = call <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double> %x)628 ret <8 x i64> %a629}630declare <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double>)631 632define <16 x i64> @llrint_v16f64(<16 x double> %x) nounwind {633; CHECK-LABEL: llrint_v16f64:634; CHECK: // %bb.0:635; CHECK-NEXT: ptrue p1.d, vl2636; CHECK-NEXT: // kill: def $q6 killed $q6 def $z6637; CHECK-NEXT: // kill: def $q4 killed $q4 def $z4638; CHECK-NEXT: // kill: def $q7 killed $q7 def $z7639; CHECK-NEXT: // kill: def $q5 killed $q5 def $z5640; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2641; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0642; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3643; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1644; CHECK-NEXT: ptrue p0.d, vl4645; CHECK-NEXT: splice z6.d, p1, z6.d, z7.d646; CHECK-NEXT: splice z4.d, p1, z4.d, z5.d647; CHECK-NEXT: splice z2.d, p1, z2.d, z3.d648; CHECK-NEXT: splice z0.d, p1, z0.d, z1.d649; CHECK-NEXT: movprfx z3, z6650; CHECK-NEXT: frintx z3.d, p0/m, z6.d651; CHECK-NEXT: movprfx z1, z4652; CHECK-NEXT: frintx z1.d, p0/m, z4.d653; CHECK-NEXT: frintx z2.d, p0/m, z2.d654; CHECK-NEXT: frintx z0.d, p0/m, z0.d655; CHECK-NEXT: mov z4.d, z3.d[2]656; CHECK-NEXT: mov z5.d, z1.d[2]657; CHECK-NEXT: mov z6.d, z2.d[3]658; CHECK-NEXT: fcvtzs x11, d0659; CHECK-NEXT: fcvtzs x12, d1660; CHECK-NEXT: fcvtzs x13, d2661; CHECK-NEXT: fcvtzs x14, d3662; CHECK-NEXT: mov z7.d, z3.d[3]663; CHECK-NEXT: mov z16.d, z1.d[3]664; CHECK-NEXT: fcvtzs x9, d4665; CHECK-NEXT: fcvtzs x10, d5666; CHECK-NEXT: mov z4.d, z2.d[2]667; CHECK-NEXT: mov z5.d, z0.d[2]668; CHECK-NEXT: fcvtzs x8, d6669; CHECK-NEXT: mov z2.d, z2.d[1]670; CHECK-NEXT: mov z6.d, z0.d[3]671; CHECK-NEXT: mov z1.d, z1.d[1]672; CHECK-NEXT: mov z3.d, z3.d[1]673; CHECK-NEXT: fcvtzs x15, d4674; CHECK-NEXT: mov z4.d, z0.d[1]675; CHECK-NEXT: fmov d0, x11676; CHECK-NEXT: fcvtzs x16, d5677; CHECK-NEXT: fcvtzs x11, d2678; CHECK-NEXT: fmov d2, x13679; CHECK-NEXT: fcvtzs x17, d7680; CHECK-NEXT: fcvtzs x18, d16681; CHECK-NEXT: fcvtzs x0, d3682; CHECK-NEXT: fcvtzs x13, d4683; CHECK-NEXT: fmov d4, x12684; CHECK-NEXT: fcvtzs x12, d6685; CHECK-NEXT: fmov d6, x14686; CHECK-NEXT: fcvtzs x14, d1687; CHECK-NEXT: fmov d3, x15688; CHECK-NEXT: fmov d1, x16689; CHECK-NEXT: fmov d5, x10690; CHECK-NEXT: fmov d7, x9691; CHECK-NEXT: mov v2.d[1], x11692; CHECK-NEXT: mov v0.d[1], x13693; CHECK-NEXT: mov v3.d[1], x8694; CHECK-NEXT: mov v6.d[1], x0695; CHECK-NEXT: mov v4.d[1], x14696; CHECK-NEXT: mov v1.d[1], x12697; CHECK-NEXT: mov v5.d[1], x18698; CHECK-NEXT: mov v7.d[1], x17699; CHECK-NEXT: ret700 %a = call <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double> %x)701 ret <16 x i64> %a702}703declare <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double>)704 705define <32 x i64> @llrint_v32f64(<32 x double> %x) nounwind {706; CHECK-LABEL: llrint_v32f64:707; CHECK: // %bb.0:708; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill709; CHECK-NEXT: sub x9, sp, #272710; CHECK-NEXT: mov x29, sp711; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0712; CHECK-NEXT: ptrue p1.d, vl2713; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0714; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1715; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3716; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2717; CHECK-NEXT: // kill: def $q7 killed $q7 def $z7718; CHECK-NEXT: // kill: def $q6 killed $q6 def $z6719; CHECK-NEXT: // kill: def $q4 killed $q4 def $z4720; CHECK-NEXT: // kill: def $q5 killed $q5 def $z5721; CHECK-NEXT: ptrue p0.d, vl4722; CHECK-NEXT: splice z0.d, p1, z0.d, z1.d723; CHECK-NEXT: splice z2.d, p1, z2.d, z3.d724; CHECK-NEXT: splice z4.d, p1, z4.d, z5.d725; CHECK-NEXT: splice z6.d, p1, z6.d, z7.d726; CHECK-NEXT: ldp q5, q19, [x29, #16]727; CHECK-NEXT: movprfx z3, z0728; CHECK-NEXT: frintx z3.d, p0/m, z0.d729; CHECK-NEXT: movprfx z16, z2730; CHECK-NEXT: frintx z16.d, p0/m, z2.d731; CHECK-NEXT: frintx z4.d, p0/m, z4.d732; CHECK-NEXT: splice z5.d, p1, z5.d, z19.d733; CHECK-NEXT: frintx z6.d, p0/m, z6.d734; CHECK-NEXT: ldp q2, q17, [x29, #48]735; CHECK-NEXT: ldp q0, q1, [x29, #112]736; CHECK-NEXT: mov z18.d, z3.d[3]737; CHECK-NEXT: mov z7.d, z3.d[2]738; CHECK-NEXT: fcvtzs x9, d3739; CHECK-NEXT: mov z3.d, z3.d[1]740; CHECK-NEXT: mov z20.d, z16.d[3]741; CHECK-NEXT: fcvtzs x12, d16742; CHECK-NEXT: splice z2.d, p1, z2.d, z17.d743; CHECK-NEXT: frintx z5.d, p0/m, z5.d744; CHECK-NEXT: splice z0.d, p1, z0.d, z1.d745; CHECK-NEXT: fcvtzs x10, d18746; CHECK-NEXT: fcvtzs x11, d7747; CHECK-NEXT: mov z18.d, z16.d[2]748; CHECK-NEXT: mov z7.d, z16.d[1]749; CHECK-NEXT: fcvtzs x13, d3750; CHECK-NEXT: str x9, [sp, #128]751; CHECK-NEXT: fcvtzs x9, d20752; CHECK-NEXT: mov z16.d, z4.d[3]753; CHECK-NEXT: ldp q3, q19, [x29, #80]754; CHECK-NEXT: frintx z2.d, p0/m, z2.d755; CHECK-NEXT: stp x11, x10, [sp, #144]756; CHECK-NEXT: fcvtzs x10, d18757; CHECK-NEXT: fcvtzs x11, d7758; CHECK-NEXT: mov z18.d, z4.d[2]759; CHECK-NEXT: mov z7.d, z4.d[1]760; CHECK-NEXT: str x13, [sp, #136]761; CHECK-NEXT: fcvtzs x13, d16762; CHECK-NEXT: mov z16.d, z6.d[3]763; CHECK-NEXT: splice z3.d, p1, z3.d, z19.d764; CHECK-NEXT: mov z1.d, z5.d[1]765; CHECK-NEXT: frintx z0.d, p0/m, z0.d766; CHECK-NEXT: stp x10, x9, [sp, #176]767; CHECK-NEXT: fcvtzs x9, d18768; CHECK-NEXT: fcvtzs x10, d4769; CHECK-NEXT: stp x12, x11, [sp, #160]770; CHECK-NEXT: fcvtzs x11, d7771; CHECK-NEXT: mov z4.d, z6.d[2]772; CHECK-NEXT: mov z7.d, z6.d[1]773; CHECK-NEXT: fcvtzs x12, d6774; CHECK-NEXT: mov z6.d, z5.d[2]775; CHECK-NEXT: frintx z3.d, p0/m, z3.d776; CHECK-NEXT: stp x9, x13, [sp, #208]777; CHECK-NEXT: fcvtzs x9, d16778; CHECK-NEXT: fcvtzs x13, d4779; CHECK-NEXT: stp x10, x11, [sp, #192]780; CHECK-NEXT: fcvtzs x10, d7781; CHECK-NEXT: mov z4.d, z5.d[3]782; CHECK-NEXT: fcvtzs x11, d4783; CHECK-NEXT: stp x13, x9, [sp, #240]784; CHECK-NEXT: fcvtzs x9, d6785; CHECK-NEXT: stp x12, x10, [sp, #224]786; CHECK-NEXT: fcvtzs x10, d5787; CHECK-NEXT: fcvtzs x12, d1788; CHECK-NEXT: mov z4.d, z2.d[3]789; CHECK-NEXT: mov z5.d, z2.d[2]790; CHECK-NEXT: mov z1.d, z2.d[1]791; CHECK-NEXT: fcvtzs x13, d2792; CHECK-NEXT: mov z2.d, z3.d[2]793; CHECK-NEXT: stp x9, x11, [sp, #16]794; CHECK-NEXT: fcvtzs x9, d4795; CHECK-NEXT: fcvtzs x11, d5796; CHECK-NEXT: stp x10, x12, [sp]797; CHECK-NEXT: fcvtzs x10, d1798; CHECK-NEXT: mov z4.d, z3.d[3]799; CHECK-NEXT: mov z1.d, z3.d[1]800; CHECK-NEXT: fcvtzs x12, d4801; CHECK-NEXT: stp x11, x9, [sp, #48]802; CHECK-NEXT: fcvtzs x9, d2803; CHECK-NEXT: fcvtzs x11, d3804; CHECK-NEXT: stp x13, x10, [sp, #32]805; CHECK-NEXT: fcvtzs x10, d1806; CHECK-NEXT: mov z2.d, z0.d[3]807; CHECK-NEXT: mov z3.d, z0.d[2]808; CHECK-NEXT: mov z1.d, z0.d[1]809; CHECK-NEXT: stp x9, x12, [sp, #80]810; CHECK-NEXT: fcvtzs x12, d0811; CHECK-NEXT: fcvtzs x13, d2812; CHECK-NEXT: fcvtzs x9, d3813; CHECK-NEXT: stp x11, x10, [sp, #64]814; CHECK-NEXT: fcvtzs x10, d1815; CHECK-NEXT: stp x9, x13, [sp, #112]816; CHECK-NEXT: add x9, sp, #128817; CHECK-NEXT: stp x12, x10, [sp, #96]818; CHECK-NEXT: add x10, sp, #192819; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9]820; CHECK-NEXT: add x9, sp, #160821; CHECK-NEXT: ld1d { z2.d }, p0/z, [x10]822; CHECK-NEXT: ld1d { z1.d }, p0/z, [x9]823; CHECK-NEXT: add x9, sp, #96824; CHECK-NEXT: add x10, sp, #224825; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]826; CHECK-NEXT: add x9, sp, #64827; CHECK-NEXT: ld1d { z4.d }, p0/z, [x10]828; CHECK-NEXT: add x10, sp, #32829; CHECK-NEXT: ld1d { z5.d }, p0/z, [x9]830; CHECK-NEXT: mov x9, sp831; CHECK-NEXT: ld1d { z6.d }, p0/z, [x10]832; CHECK-NEXT: mov x10, #28 // =0x1c833; CHECK-NEXT: ld1d { z7.d }, p0/z, [x9]834; CHECK-NEXT: mov x9, #24 // =0x18835; CHECK-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]836; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]837; CHECK-NEXT: mov x9, #20 // =0x14838; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]839; CHECK-NEXT: mov x9, #16 // =0x10840; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]841; CHECK-NEXT: mov x9, #12 // =0xc842; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]843; CHECK-NEXT: mov x9, #8 // =0x8844; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]845; CHECK-NEXT: mov x9, #4 // =0x4846; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]847; CHECK-NEXT: st1d { z0.d }, p0, [x8]848; CHECK-NEXT: mov sp, x29849; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload850; CHECK-NEXT: ret851 %a = call <32 x i64> @llvm.llrint.v32i64.v16f64(<32 x double> %x)852 ret <32 x i64> %a853}854declare <32 x i64> @llvm.llrint.v32i64.v32f64(<32 x double>)855 856define <1 x i64> @llrint_v1i64_v1fp128(<1 x fp128> %x) nounwind {857; CHECK-LABEL: llrint_v1i64_v1fp128:858; CHECK: // %bb.0:859; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill860; CHECK-NEXT: bl llrintl861; CHECK-NEXT: fmov d0, x0862; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload863; CHECK-NEXT: ret864 %a = call <1 x i64> @llvm.llrint.v1i64.v1fp128(<1 x fp128> %x)865 ret <1 x i64> %a866}867declare <1 x i64> @llvm.llrint.v1i64.v1fp128(<1 x fp128>)868 869define <2 x i64> @llrint_v2i64_v2fp128(<2 x fp128> %x) nounwind {870; CHECK-LABEL: llrint_v2i64_v2fp128:871; CHECK: // %bb.0:872; CHECK-NEXT: sub sp, sp, #48873; CHECK-NEXT: str q0, [sp] // 16-byte Spill874; CHECK-NEXT: mov v0.16b, v1.16b875; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill876; CHECK-NEXT: bl llrintl877; CHECK-NEXT: fmov d0, x0878; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill879; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload880; CHECK-NEXT: bl llrintl881; CHECK-NEXT: fmov d0, x0882; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload883; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload884; CHECK-NEXT: mov v0.d[1], v1.d[0]885; CHECK-NEXT: add sp, sp, #48886; CHECK-NEXT: ret887 %a = call <2 x i64> @llvm.llrint.v2i64.v2fp128(<2 x fp128> %x)888 ret <2 x i64> %a889}890declare <2 x i64> @llvm.llrint.v2i64.v2fp128(<2 x fp128>)891 892define <4 x i64> @llrint_v4i64_v4fp128(<4 x fp128> %x) nounwind {893; CHECK-LABEL: llrint_v4i64_v4fp128:894; CHECK: // %bb.0:895; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill896; CHECK-NEXT: sub sp, sp, #64897; CHECK-NEXT: addvl sp, sp, #-1898; CHECK-NEXT: str q0, [sp, #48] // 16-byte Spill899; CHECK-NEXT: mov v0.16b, v3.16b900; CHECK-NEXT: stp q2, q1, [sp, #16] // 32-byte Folded Spill901; CHECK-NEXT: bl llrintl902; CHECK-NEXT: fmov d0, x0903; CHECK-NEXT: str q0, [sp] // 16-byte Spill904; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload905; CHECK-NEXT: bl llrintl906; CHECK-NEXT: fmov d0, x0907; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload908; CHECK-NEXT: add x8, sp, #64909; CHECK-NEXT: mov v0.d[1], v1.d[0]910; CHECK-NEXT: str z0, [x8] // 16-byte Folded Spill911; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Reload912; CHECK-NEXT: bl llrintl913; CHECK-NEXT: fmov d0, x0914; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill915; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Reload916; CHECK-NEXT: bl llrintl917; CHECK-NEXT: fmov d0, x0918; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Reload919; CHECK-NEXT: add x8, sp, #64920; CHECK-NEXT: ptrue p0.d, vl2921; CHECK-NEXT: mov v0.d[1], v1.d[0]922; CHECK-NEXT: ldr z1, [x8] // 16-byte Folded Reload923; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d924; CHECK-NEXT: movprfx z1, z0925; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16926; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0927; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1928; CHECK-NEXT: addvl sp, sp, #1929; CHECK-NEXT: add sp, sp, #64930; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload931; CHECK-NEXT: ret932 %a = call <4 x i64> @llvm.llrint.v4i64.v4fp128(<4 x fp128> %x)933 ret <4 x i64> %a934}935declare <4 x i64> @llvm.llrint.v4i64.v4fp128(<4 x fp128>)936 937define <8 x i64> @llrint_v8i64_v8fp128(<8 x fp128> %x) nounwind {938; CHECK-LABEL: llrint_v8i64_v8fp128:939; CHECK: // %bb.0:940; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill941; CHECK-NEXT: sub sp, sp, #128942; CHECK-NEXT: addvl sp, sp, #-2943; CHECK-NEXT: str q0, [sp, #112] // 16-byte Spill944; CHECK-NEXT: mov v0.16b, v7.16b945; CHECK-NEXT: stp q6, q5, [sp, #16] // 32-byte Folded Spill946; CHECK-NEXT: stp q4, q3, [sp, #48] // 32-byte Folded Spill947; CHECK-NEXT: stp q2, q1, [sp, #80] // 32-byte Folded Spill948; CHECK-NEXT: bl llrintl949; CHECK-NEXT: fmov d0, x0950; CHECK-NEXT: str q0, [sp] // 16-byte Spill951; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload952; CHECK-NEXT: bl llrintl953; CHECK-NEXT: fmov d0, x0954; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload955; CHECK-NEXT: add x8, sp, #128956; CHECK-NEXT: mov v0.d[1], v1.d[0]957; CHECK-NEXT: str z0, [x8, #1, mul vl] // 16-byte Folded Spill958; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Reload959; CHECK-NEXT: bl llrintl960; CHECK-NEXT: fmov d0, x0961; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill962; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Reload963; CHECK-NEXT: bl llrintl964; CHECK-NEXT: fmov d0, x0965; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Reload966; CHECK-NEXT: add x8, sp, #128967; CHECK-NEXT: ptrue p0.d, vl2968; CHECK-NEXT: mov v0.d[1], v1.d[0]969; CHECK-NEXT: ldr z1, [x8, #1, mul vl] // 16-byte Folded Reload970; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d971; CHECK-NEXT: str z0, [x8, #1, mul vl] // 16-byte Folded Spill972; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Reload973; CHECK-NEXT: bl llrintl974; CHECK-NEXT: fmov d0, x0975; CHECK-NEXT: str q0, [sp, #64] // 16-byte Spill976; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Reload977; CHECK-NEXT: bl llrintl978; CHECK-NEXT: fmov d0, x0979; CHECK-NEXT: ldr q1, [sp, #64] // 16-byte Reload980; CHECK-NEXT: add x8, sp, #128981; CHECK-NEXT: mov v0.d[1], v1.d[0]982; CHECK-NEXT: str z0, [x8] // 16-byte Folded Spill983; CHECK-NEXT: ldr q0, [sp, #96] // 16-byte Reload984; CHECK-NEXT: bl llrintl985; CHECK-NEXT: fmov d0, x0986; CHECK-NEXT: str q0, [sp, #96] // 16-byte Spill987; CHECK-NEXT: ldr q0, [sp, #112] // 16-byte Reload988; CHECK-NEXT: bl llrintl989; CHECK-NEXT: fmov d0, x0990; CHECK-NEXT: ldr q1, [sp, #96] // 16-byte Reload991; CHECK-NEXT: add x8, sp, #128992; CHECK-NEXT: ptrue p0.d, vl2993; CHECK-NEXT: ldr z2, [x8, #1, mul vl] // 16-byte Folded Reload994; CHECK-NEXT: mov v0.d[1], v1.d[0]995; CHECK-NEXT: ldr z1, [x8] // 16-byte Folded Reload996; CHECK-NEXT: movprfx z3, z2997; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16998; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2999; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d1000; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z31001; CHECK-NEXT: movprfx z1, z01002; CHECK-NEXT: ext z1.b, z1.b, z0.b, #161003; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z01004; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z11005; CHECK-NEXT: addvl sp, sp, #21006; CHECK-NEXT: add sp, sp, #1281007; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload1008; CHECK-NEXT: ret1009 %a = call <8 x i64> @llvm.llrint.v8i64.v8fp128(<8 x fp128> %x)1010 ret <8 x i64> %a1011}1012declare <8 x i64> @llvm.llrint.v8i64.v8fp128(<8 x fp128>)1013 1014define <16 x i64> @llrint_v16fp128(<16 x fp128> %x) nounwind {1015; CHECK-LABEL: llrint_v16fp128:1016; CHECK: // %bb.0:1017; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill1018; CHECK-NEXT: sub sp, sp, #2561019; CHECK-NEXT: addvl sp, sp, #-41020; CHECK-NEXT: addvl x8, sp, #41021; CHECK-NEXT: str q1, [sp, #240] // 16-byte Spill1022; CHECK-NEXT: ldr q1, [x8, #272]1023; CHECK-NEXT: addvl x8, sp, #41024; CHECK-NEXT: str q0, [sp, #224] // 16-byte Spill1025; CHECK-NEXT: stp q7, q6, [sp, #128] // 32-byte Folded Spill1026; CHECK-NEXT: str q1, [sp, #112] // 16-byte Spill1027; CHECK-NEXT: ldr q1, [x8, #288]1028; CHECK-NEXT: addvl x8, sp, #41029; CHECK-NEXT: stp q5, q4, [sp, #160] // 32-byte Folded Spill1030; CHECK-NEXT: str q1, [sp, #96] // 16-byte Spill1031; CHECK-NEXT: ldr q1, [x8, #304]1032; CHECK-NEXT: addvl x8, sp, #41033; CHECK-NEXT: stp q3, q2, [sp, #192] // 32-byte Folded Spill1034; CHECK-NEXT: str q1, [sp, #80] // 16-byte Spill1035; CHECK-NEXT: ldr q1, [x8, #320]1036; CHECK-NEXT: addvl x8, sp, #41037; CHECK-NEXT: str q1, [sp, #64] // 16-byte Spill1038; CHECK-NEXT: ldr q1, [x8, #336]1039; CHECK-NEXT: addvl x8, sp, #41040; CHECK-NEXT: str q1, [sp, #48] // 16-byte Spill1041; CHECK-NEXT: ldr q1, [x8, #352]1042; CHECK-NEXT: addvl x8, sp, #41043; CHECK-NEXT: str q1, [sp, #32] // 16-byte Spill1044; CHECK-NEXT: ldr q1, [x8, #368]1045; CHECK-NEXT: addvl x8, sp, #41046; CHECK-NEXT: str q1, [sp, #16] // 16-byte Spill1047; CHECK-NEXT: ldr q1, [x8, #384]1048; CHECK-NEXT: mov v0.16b, v1.16b1049; CHECK-NEXT: bl llrintl1050; CHECK-NEXT: fmov d0, x01051; CHECK-NEXT: str q0, [sp] // 16-byte Spill1052; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload1053; CHECK-NEXT: bl llrintl1054; CHECK-NEXT: fmov d0, x01055; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload1056; CHECK-NEXT: add x8, sp, #2561057; CHECK-NEXT: mov v0.d[1], v1.d[0]1058; CHECK-NEXT: str z0, [x8, #3, mul vl] // 16-byte Folded Spill1059; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Reload1060; CHECK-NEXT: bl llrintl1061; CHECK-NEXT: fmov d0, x01062; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill1063; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Reload1064; CHECK-NEXT: bl llrintl1065; CHECK-NEXT: fmov d0, x01066; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Reload1067; CHECK-NEXT: add x8, sp, #2561068; CHECK-NEXT: ptrue p0.d, vl21069; CHECK-NEXT: mov v0.d[1], v1.d[0]1070; CHECK-NEXT: ldr z1, [x8, #3, mul vl] // 16-byte Folded Reload1071; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d1072; CHECK-NEXT: str z0, [x8, #3, mul vl] // 16-byte Folded Spill1073; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Reload1074; CHECK-NEXT: bl llrintl1075; CHECK-NEXT: fmov d0, x01076; CHECK-NEXT: str q0, [sp, #64] // 16-byte Spill1077; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Reload1078; CHECK-NEXT: bl llrintl1079; CHECK-NEXT: fmov d0, x01080; CHECK-NEXT: ldr q1, [sp, #64] // 16-byte Reload1081; CHECK-NEXT: add x8, sp, #2561082; CHECK-NEXT: mov v0.d[1], v1.d[0]1083; CHECK-NEXT: str z0, [x8, #2, mul vl] // 16-byte Folded Spill1084; CHECK-NEXT: ldr q0, [sp, #96] // 16-byte Reload1085; CHECK-NEXT: bl llrintl1086; CHECK-NEXT: fmov d0, x01087; CHECK-NEXT: str q0, [sp, #96] // 16-byte Spill1088; CHECK-NEXT: ldr q0, [sp, #112] // 16-byte Reload1089; CHECK-NEXT: bl llrintl1090; CHECK-NEXT: fmov d0, x01091; CHECK-NEXT: ldr q1, [sp, #96] // 16-byte Reload1092; CHECK-NEXT: add x8, sp, #2561093; CHECK-NEXT: ptrue p0.d, vl21094; CHECK-NEXT: mov v0.d[1], v1.d[0]1095; CHECK-NEXT: ldr z1, [x8, #2, mul vl] // 16-byte Folded Reload1096; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d1097; CHECK-NEXT: str z0, [x8, #2, mul vl] // 16-byte Folded Spill1098; CHECK-NEXT: ldr q0, [sp, #128] // 16-byte Reload1099; CHECK-NEXT: bl llrintl1100; CHECK-NEXT: fmov d0, x01101; CHECK-NEXT: str q0, [sp, #128] // 16-byte Spill1102; CHECK-NEXT: ldr q0, [sp, #144] // 16-byte Reload1103; CHECK-NEXT: bl llrintl1104; CHECK-NEXT: fmov d0, x01105; CHECK-NEXT: ldr q1, [sp, #128] // 16-byte Reload1106; CHECK-NEXT: add x8, sp, #2561107; CHECK-NEXT: mov v0.d[1], v1.d[0]1108; CHECK-NEXT: str z0, [x8, #1, mul vl] // 16-byte Folded Spill1109; CHECK-NEXT: ldr q0, [sp, #160] // 16-byte Reload1110; CHECK-NEXT: bl llrintl1111; CHECK-NEXT: fmov d0, x01112; CHECK-NEXT: str q0, [sp, #160] // 16-byte Spill1113; CHECK-NEXT: ldr q0, [sp, #176] // 16-byte Reload1114; CHECK-NEXT: bl llrintl1115; CHECK-NEXT: fmov d0, x01116; CHECK-NEXT: ldr q1, [sp, #160] // 16-byte Reload1117; CHECK-NEXT: add x8, sp, #2561118; CHECK-NEXT: ptrue p0.d, vl21119; CHECK-NEXT: mov v0.d[1], v1.d[0]1120; CHECK-NEXT: ldr z1, [x8, #1, mul vl] // 16-byte Folded Reload1121; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d1122; CHECK-NEXT: str z0, [x8, #1, mul vl] // 16-byte Folded Spill1123; CHECK-NEXT: ldr q0, [sp, #192] // 16-byte Reload1124; CHECK-NEXT: bl llrintl1125; CHECK-NEXT: fmov d0, x01126; CHECK-NEXT: str q0, [sp, #192] // 16-byte Spill1127; CHECK-NEXT: ldr q0, [sp, #208] // 16-byte Reload1128; CHECK-NEXT: bl llrintl1129; CHECK-NEXT: fmov d0, x01130; CHECK-NEXT: ldr q1, [sp, #192] // 16-byte Reload1131; CHECK-NEXT: add x8, sp, #2561132; CHECK-NEXT: mov v0.d[1], v1.d[0]1133; CHECK-NEXT: str z0, [x8] // 16-byte Folded Spill1134; CHECK-NEXT: ldr q0, [sp, #240] // 16-byte Reload1135; CHECK-NEXT: bl llrintl1136; CHECK-NEXT: fmov d0, x01137; CHECK-NEXT: str q0, [sp, #240] // 16-byte Spill1138; CHECK-NEXT: ldr q0, [sp, #224] // 16-byte Reload1139; CHECK-NEXT: bl llrintl1140; CHECK-NEXT: fmov d0, x01141; CHECK-NEXT: ldr q1, [sp, #240] // 16-byte Reload1142; CHECK-NEXT: add x8, sp, #2561143; CHECK-NEXT: ptrue p0.d, vl21144; CHECK-NEXT: ldr z2, [x8, #1, mul vl] // 16-byte Folded Reload1145; CHECK-NEXT: ldr z4, [x8, #2, mul vl] // 16-byte Folded Reload1146; CHECK-NEXT: ldr z6, [x8, #3, mul vl] // 16-byte Folded Reload1147; CHECK-NEXT: mov v0.d[1], v1.d[0]1148; CHECK-NEXT: ldr z1, [x8] // 16-byte Folded Reload1149; CHECK-NEXT: movprfx z3, z21150; CHECK-NEXT: ext z3.b, z3.b, z2.b, #161151; CHECK-NEXT: movprfx z5, z41152; CHECK-NEXT: ext z5.b, z5.b, z4.b, #161153; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z21154; CHECK-NEXT: // kill: def $q4 killed $q4 killed $z41155; CHECK-NEXT: movprfx z7, z61156; CHECK-NEXT: ext z7.b, z7.b, z6.b, #161157; CHECK-NEXT: // kill: def $q6 killed $q6 killed $z61158; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d1159; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z31160; CHECK-NEXT: // kill: def $q5 killed $q5 killed $z51161; CHECK-NEXT: // kill: def $q7 killed $q7 killed $z71162; CHECK-NEXT: movprfx z1, z01163; CHECK-NEXT: ext z1.b, z1.b, z0.b, #161164; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z01165; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z11166; CHECK-NEXT: addvl sp, sp, #41167; CHECK-NEXT: add sp, sp, #2561168; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload1169; CHECK-NEXT: ret1170 %a = call <16 x i64> @llvm.llrint.v16i64.v16fp128(<16 x fp128> %x)1171 ret <16 x i64> %a1172}1173declare <16 x i64> @llvm.llrint.v16i64.v16fp128(<16 x fp128>)1174