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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; Ensure that a no-op 'and' after an extending load gets removed when the and is7; constructed via a splat_vector node.8define <vscale x 2 x i64> @fold_loadext_and(ptr %ptr, i32 %needle, <vscale x 2 x i64> %b) #0 {9; CHECK-LABEL: fold_loadext_and:10; CHECK: // %bb.0:11; CHECK-NEXT: ptrue p0.d12; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]13; CHECK-NEXT: ret14 %load = load <vscale x 2 x i32>, ptr %ptr, align 415 %ext = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>16 %and = and <vscale x 2 x i64> %ext, splat(i64 4294967295)17 ret <vscale x 2 x i64> %and18}19 20; Same as above but testing the case we care about. Here the vscale x 2 x i3221; types get legalized into vscale x 2 x i64 types which introduces the extending22; load and 'and' nodes similar to the above case.23define <vscale x 2 x i1> @fold_loadext_and_legalize(ptr %ptr, <vscale x 2 x i32> %a) #0 {24; CHECK-LABEL: fold_loadext_and_legalize:25; CHECK: // %bb.0:26; CHECK-NEXT: ptrue p0.d27; CHECK-NEXT: and z0.d, z0.d, #0xffffffff28; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0]29; CHECK-NEXT: cmpeq p0.d, p0/z, z1.d, z0.d30; CHECK-NEXT: ret31 %load = load <vscale x 2 x i32>, ptr %ptr32 %cmp = icmp eq <vscale x 2 x i32> %load, %a33 ret <vscale x 2 x i1> %cmp34}35 36attributes #0 = { "target-features"="+sve" }37