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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4; Check that vscale call is recognised by load/store reg/reg pattern and5; partially folded, with the rest pulled out of the loop.6 7define void @ld1w_reg_loop(ptr %addr) {8; CHECK-LABEL: ld1w_reg_loop:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: ptrue p0.s11; CHECK-NEXT: mov x8, xzr12; CHECK-NEXT: cntw x913; CHECK-NEXT: .LBB0_1: // %vector.body14; CHECK-NEXT: // =>This Inner Loop Header: Depth=115; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]16; CHECK-NEXT: adds x8, x8, x917; CHECK-NEXT: b.ne .LBB0_118; CHECK-NEXT: // %bb.2: // %for.cond.cleanup19; CHECK-NEXT: ret20entry:21 %0 = call i64 @llvm.vscale.i64()22 %1 = shl i64 %0, 223 br label %vector.body24 25vector.body:26 %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]27 %2 = getelementptr inbounds [32000 x i32], ptr %addr, i64 0, i64 %index28 %load = load volatile <vscale x 4 x i32>, ptr %2, align 1629 %index.next = add i64 %index, %130 %3 = icmp eq i64 %index.next, 031 br i1 %3, label %for.cond.cleanup, label %vector.body32 33for.cond.cleanup:34 ret void35}36 37define void @st1w_reg_loop(ptr %addr, <vscale x 4 x i32> %val) {38; CHECK-LABEL: st1w_reg_loop:39; CHECK: // %bb.0: // %entry40; CHECK-NEXT: ptrue p0.s41; CHECK-NEXT: mov x8, xzr42; CHECK-NEXT: cntw x943; CHECK-NEXT: .LBB1_1: // %vector.body44; CHECK-NEXT: // =>This Inner Loop Header: Depth=145; CHECK-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]46; CHECK-NEXT: adds x8, x8, x947; CHECK-NEXT: b.ne .LBB1_148; CHECK-NEXT: // %bb.2: // %for.cond.cleanup49; CHECK-NEXT: ret50entry:51 %0 = call i64 @llvm.vscale.i64()52 %1 = shl i64 %0, 253 br label %vector.body54 55vector.body:56 %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]57 %2 = getelementptr inbounds [32000 x i32], ptr %addr, i64 0, i64 %index58 store volatile <vscale x 4 x i32> %val, ptr %2, align 1659 %index.next = add i64 %index, %160 %3 = icmp eq i64 %index.next, 061 br i1 %3, label %for.cond.cleanup, label %vector.body62 63for.cond.cleanup:64 ret void65}66 67declare i64 @llvm.vscale.i64()68