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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4define <vscale x 8 x half> @vselect_fmul_f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {5; CHECK-LABEL: vselect_fmul_f16:6; CHECK: // %bb.0:7; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h8; CHECK-NEXT: ret9 %mul = fmul <vscale x 8 x half> %a, %b10 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> %mul, <vscale x 8 x half> %a11 ret <vscale x 8 x half> %sel12}13 14define <vscale x 4 x float> @vselect_fmul_f32(<vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {15; CHECK-LABEL: vselect_fmul_f32:16; CHECK: // %bb.0:17; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s18; CHECK-NEXT: ret19 %mul = fmul <vscale x 4 x float> %a, %b20 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %mul, <vscale x 4 x float> %a21 ret <vscale x 4 x float> %sel22}23 24define <vscale x 2 x double> @vselect_fmul_f64(<vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {25; CHECK-LABEL: vselect_fmul_f64:26; CHECK: // %bb.0:27; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z1.d28; CHECK-NEXT: ret29 %mul = fmul <vscale x 2 x double> %a, %b30 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %mul, <vscale x 2 x double> %a31 ret <vscale x 2 x double> %sel32}33 34define <vscale x 8 x half> @vselect_fadd_f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {35; CHECK-LABEL: vselect_fadd_f16:36; CHECK: // %bb.0:37; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h38; CHECK-NEXT: ret39 %add = fadd <vscale x 8 x half> %a, %b40 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> %add, <vscale x 8 x half> %a41 ret <vscale x 8 x half> %sel42}43 44define <vscale x 4 x float> @vselect_fadd_f32(<vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {45; CHECK-LABEL: vselect_fadd_f32:46; CHECK: // %bb.0:47; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s48; CHECK-NEXT: ret49 %add = fadd <vscale x 4 x float> %a, %b50 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %add, <vscale x 4 x float> %a51 ret <vscale x 4 x float> %sel52}53 54define <vscale x 2 x double> @vselect_fadd_f64(<vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {55; CHECK-LABEL: vselect_fadd_f64:56; CHECK: // %bb.0:57; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d58; CHECK-NEXT: ret59 %add = fadd <vscale x 2 x double> %a, %b60 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %add, <vscale x 2 x double> %a61 ret <vscale x 2 x double> %sel62}63 64define <vscale x 8 x half> @vselect_fsub_f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {65; CHECK-LABEL: vselect_fsub_f16:66; CHECK: // %bb.0:67; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h68; CHECK-NEXT: ret69 %sub = fsub <vscale x 8 x half> %a, %b70 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> %sub, <vscale x 8 x half> %a71 ret <vscale x 8 x half> %sel72}73 74define <vscale x 4 x float> @vselect_fsub_f32(<vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {75; CHECK-LABEL: vselect_fsub_f32:76; CHECK: // %bb.0:77; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s78; CHECK-NEXT: ret79 %sub = fsub <vscale x 4 x float> %a, %b80 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %sub, <vscale x 4 x float> %a81 ret <vscale x 4 x float> %sel82}83 84define <vscale x 2 x double> @vselect_fsub_f64(<vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {85; CHECK-LABEL: vselect_fsub_f64:86; CHECK: // %bb.0:87; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d88; CHECK-NEXT: ret89 %sub = fsub <vscale x 2 x double> %a, %b90 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %sub, <vscale x 2 x double> %a91 ret <vscale x 2 x double> %sel92}93