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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s3 4; Float5 6declare <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f32.nxv2i32(<vscale x 2 x float>)7declare <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f32.nxv4i32(<vscale x 4 x float>)8declare <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f32.nxv8i32(<vscale x 8 x float>)9declare <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f32.nxv4i16(<vscale x 4 x float>)10declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f32.nxv8i16(<vscale x 8 x float>)11declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f32.nxv2i64(<vscale x 2 x float>)12declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float>)13 14define <vscale x 2 x i32> @test_signed_v2f32_v2i32(<vscale x 2 x float> %f) {15; CHECK-LABEL: test_signed_v2f32_v2i32:16; CHECK: // %bb.0:17; CHECK-NEXT: mov w8, #-822083584 // =0xcf00000018; CHECK-NEXT: ptrue p0.d19; CHECK-NEXT: mov z1.s, w820; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff21; CHECK-NEXT: mov z2.s, w822; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s23; CHECK-NEXT: mov z1.d, #0xffffffff8000000024; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s25; CHECK-NEXT: mov z2.d, #0x7fffffff26; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s27; CHECK-NEXT: fcvtzs z1.d, p1/m, z0.s28; CHECK-NEXT: sel z0.d, p2, z2.d, z1.d29; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x030; CHECK-NEXT: ret31 %x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f32.nxv2i32(<vscale x 2 x float> %f)32 ret <vscale x 2 x i32> %x33}34 35define <vscale x 4 x i32> @test_signed_v4f32_v4i32(<vscale x 4 x float> %f) {36; CHECK-LABEL: test_signed_v4f32_v4i32:37; CHECK: // %bb.0:38; CHECK-NEXT: mov w8, #-822083584 // =0xcf00000039; CHECK-NEXT: ptrue p0.s40; CHECK-NEXT: mov z1.s, w841; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff42; CHECK-NEXT: mov z2.s, w843; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s44; CHECK-NEXT: mov z1.s, #0x8000000045; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s46; CHECK-NEXT: mov z2.s, #0x7fffffff47; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s48; CHECK-NEXT: fcvtzs z1.s, p1/m, z0.s49; CHECK-NEXT: sel z0.s, p2, z2.s, z1.s50; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x051; CHECK-NEXT: ret52 %x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f32.nxv4i32(<vscale x 4 x float> %f)53 ret <vscale x 4 x i32> %x54}55 56define <vscale x 8 x i32> @test_signed_v8f32_v8i32(<vscale x 8 x float> %f) {57; CHECK-LABEL: test_signed_v8f32_v8i32:58; CHECK: // %bb.0:59; CHECK-NEXT: mov w8, #-822083584 // =0xcf00000060; CHECK-NEXT: ptrue p0.s61; CHECK-NEXT: mov z3.s, #0x8000000062; CHECK-NEXT: mov z2.s, w863; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff64; CHECK-NEXT: mov z4.s, #0x8000000065; CHECK-NEXT: mov z5.s, w866; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z2.s67; CHECK-NEXT: fcmge p2.s, p0/z, z1.s, z2.s68; CHECK-NEXT: mov z2.s, #0x7fffffff69; CHECK-NEXT: fcmgt p3.s, p0/z, z1.s, z5.s70; CHECK-NEXT: fcvtzs z3.s, p1/m, z0.s71; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z5.s72; CHECK-NEXT: fcvtzs z4.s, p2/m, z1.s73; CHECK-NEXT: fcmuo p2.s, p0/z, z0.s, z0.s74; CHECK-NEXT: fcmuo p0.s, p0/z, z1.s, z1.s75; CHECK-NEXT: sel z0.s, p1, z2.s, z3.s76; CHECK-NEXT: sel z1.s, p3, z2.s, z4.s77; CHECK-NEXT: mov z0.s, p2/m, #0 // =0x078; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x079; CHECK-NEXT: ret80 %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)81 ret <vscale x 8 x i32> %x82}83 84define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {85; CHECK-LABEL: test_signed_v4f32_v4i16:86; CHECK: // %bb.0:87; CHECK-NEXT: mov w8, #-956301312 // =0xc700000088; CHECK-NEXT: ptrue p0.s89; CHECK-NEXT: mov z2.s, #-32768 // =0xffffffffffff800090; CHECK-NEXT: mov z1.s, w891; CHECK-NEXT: mov w8, #65024 // =0xfe0092; CHECK-NEXT: movk w8, #18175, lsl #1693; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s94; CHECK-NEXT: mov z1.s, w895; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z1.s96; CHECK-NEXT: mov z1.s, #32767 // =0x7fff97; CHECK-NEXT: fcvtzs z2.s, p1/m, z0.s98; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s99; CHECK-NEXT: sel z0.s, p2, z1.s, z2.s100; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0101; CHECK-NEXT: ret102 %x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)103 ret <vscale x 4 x i16> %x104}105 106define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {107; CHECK-LABEL: test_signed_v8f32_v8i16:108; CHECK: // %bb.0:109; CHECK-NEXT: mov w8, #-956301312 // =0xc7000000110; CHECK-NEXT: ptrue p0.s111; CHECK-NEXT: mov z3.s, #-32768 // =0xffffffffffff8000112; CHECK-NEXT: mov z2.s, w8113; CHECK-NEXT: mov w8, #65024 // =0xfe00114; CHECK-NEXT: mov z5.s, #32767 // =0x7fff115; CHECK-NEXT: movk w8, #18175, lsl #16116; CHECK-NEXT: mov z4.s, w8117; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z2.s118; CHECK-NEXT: fcmge p2.s, p0/z, z0.s, z2.s119; CHECK-NEXT: mov z2.s, #-32768 // =0xffffffffffff8000120; CHECK-NEXT: fcmgt p3.s, p0/z, z0.s, z4.s121; CHECK-NEXT: fcvtzs z3.s, p1/m, z1.s122; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z4.s123; CHECK-NEXT: fcvtzs z2.s, p2/m, z0.s124; CHECK-NEXT: fcmuo p2.s, p0/z, z1.s, z1.s125; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s126; CHECK-NEXT: sel z0.s, p1, z5.s, z3.s127; CHECK-NEXT: sel z1.s, p3, z5.s, z2.s128; CHECK-NEXT: mov z0.s, p2/m, #0 // =0x0129; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0130; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h131; CHECK-NEXT: ret132 %x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)133 ret <vscale x 8 x i16> %x134}135 136define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {137; CHECK-LABEL: test_signed_v2f32_v2i64:138; CHECK: // %bb.0:139; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000140; CHECK-NEXT: ptrue p0.d141; CHECK-NEXT: mov z1.s, w8142; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff143; CHECK-NEXT: mov z2.s, w8144; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s145; CHECK-NEXT: mov z1.d, #0x8000000000000000146; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s147; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff148; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s149; CHECK-NEXT: fcvtzs z1.d, p1/m, z0.s150; CHECK-NEXT: sel z0.d, p2, z2.d, z1.d151; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0152; CHECK-NEXT: ret153 %x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)154 ret <vscale x 2 x i64> %x155}156 157define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {158; CHECK-LABEL: test_signed_v4f32_v4i64:159; CHECK: // %bb.0:160; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000161; CHECK-NEXT: uunpklo z1.d, z0.s162; CHECK-NEXT: uunpkhi z0.d, z0.s163; CHECK-NEXT: mov z2.s, w8164; CHECK-NEXT: ptrue p0.d165; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff166; CHECK-NEXT: mov z3.d, #0x8000000000000000167; CHECK-NEXT: mov z4.d, #0x8000000000000000168; CHECK-NEXT: mov z5.s, w8169; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z2.s170; CHECK-NEXT: fcmge p2.s, p0/z, z0.s, z2.s171; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff172; CHECK-NEXT: fcmgt p3.s, p0/z, z0.s, z5.s173; CHECK-NEXT: fcvtzs z3.d, p1/m, z1.s174; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z5.s175; CHECK-NEXT: fcvtzs z4.d, p2/m, z0.s176; CHECK-NEXT: fcmuo p2.s, p0/z, z1.s, z1.s177; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s178; CHECK-NEXT: sel z0.d, p1, z2.d, z3.d179; CHECK-NEXT: sel z1.d, p3, z2.d, z4.d180; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0181; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0182; CHECK-NEXT: ret183 %x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)184 ret <vscale x 4 x i64> %x185}186 187; Double188 189declare <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double>)190declare <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double>)191declare <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double>)192declare <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f64.nxv4i16(<vscale x 4 x double>)193declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f64.nxv8i16(<vscale x 8 x double>)194declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f64.nxv2i64(<vscale x 2 x double>)195declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double>)196 197define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {198; CHECK-LABEL: test_signed_v2f64_v2i32:199; CHECK: // %bb.0:200; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000201; CHECK-NEXT: ptrue p0.d202; CHECK-NEXT: mov z1.d, x8203; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000204; CHECK-NEXT: movk x8, #16863, lsl #48205; CHECK-NEXT: mov z2.d, x8206; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d207; CHECK-NEXT: mov z1.d, #0xffffffff80000000208; CHECK-NEXT: fcmgt p2.d, p0/z, z0.d, z2.d209; CHECK-NEXT: mov z2.d, #0x7fffffff210; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d211; CHECK-NEXT: fcvtzs z1.d, p1/m, z0.d212; CHECK-NEXT: sel z0.d, p2, z2.d, z1.d213; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0214; CHECK-NEXT: ret215 %x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)216 ret <vscale x 2 x i32> %x217}218 219define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {220; CHECK-LABEL: test_signed_v4f64_v4i32:221; CHECK: // %bb.0:222; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000223; CHECK-NEXT: ptrue p0.d224; CHECK-NEXT: mov z3.d, #0xffffffff80000000225; CHECK-NEXT: mov z2.d, x8226; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000227; CHECK-NEXT: mov z4.d, #0xffffffff80000000228; CHECK-NEXT: movk x8, #16863, lsl #48229; CHECK-NEXT: mov z5.d, x8230; CHECK-NEXT: fcmge p1.d, p0/z, z1.d, z2.d231; CHECK-NEXT: fcmge p2.d, p0/z, z0.d, z2.d232; CHECK-NEXT: mov z2.d, #0x7fffffff233; CHECK-NEXT: fcmgt p3.d, p0/z, z0.d, z5.d234; CHECK-NEXT: fcvtzs z3.d, p1/m, z1.d235; CHECK-NEXT: fcmgt p1.d, p0/z, z1.d, z5.d236; CHECK-NEXT: fcvtzs z4.d, p2/m, z0.d237; CHECK-NEXT: fcmuo p2.d, p0/z, z1.d, z1.d238; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d239; CHECK-NEXT: sel z0.d, p1, z2.d, z3.d240; CHECK-NEXT: sel z1.d, p3, z2.d, z4.d241; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0242; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0243; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s244; CHECK-NEXT: ret245 %x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)246 ret <vscale x 4 x i32> %x247}248 249define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {250; CHECK-LABEL: test_signed_v8f64_v8i32:251; CHECK: // %bb.0:252; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill253; CHECK-NEXT: addvl sp, sp, #-1254; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill255; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill256; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill257; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG258; CHECK-NEXT: .cfi_offset w29, -16259; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000260; CHECK-NEXT: ptrue p0.d261; CHECK-NEXT: mov z5.d, #0xffffffff80000000262; CHECK-NEXT: mov z4.d, x8263; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000264; CHECK-NEXT: mov z6.d, #0xffffffff80000000265; CHECK-NEXT: movk x8, #16863, lsl #48266; CHECK-NEXT: mov z7.d, #0xffffffff80000000267; CHECK-NEXT: mov z25.d, #0x7fffffff268; CHECK-NEXT: mov z24.d, x8269; CHECK-NEXT: fcmge p1.d, p0/z, z1.d, z4.d270; CHECK-NEXT: fcmge p2.d, p0/z, z0.d, z4.d271; CHECK-NEXT: fcmge p3.d, p0/z, z3.d, z4.d272; CHECK-NEXT: fcmgt p4.d, p0/z, z0.d, z24.d273; CHECK-NEXT: fcvtzs z5.d, p1/m, z1.d274; CHECK-NEXT: fcmgt p1.d, p0/z, z1.d, z24.d275; CHECK-NEXT: fcvtzs z6.d, p2/m, z0.d276; CHECK-NEXT: fcmge p2.d, p0/z, z2.d, z4.d277; CHECK-NEXT: mov z4.d, #0xffffffff80000000278; CHECK-NEXT: fcvtzs z7.d, p3/m, z3.d279; CHECK-NEXT: fcmuo p3.d, p0/z, z1.d, z1.d280; CHECK-NEXT: fcmgt p5.d, p0/z, z2.d, z24.d281; CHECK-NEXT: sel z1.d, p1, z25.d, z5.d282; CHECK-NEXT: fcmgt p1.d, p0/z, z3.d, z24.d283; CHECK-NEXT: fcvtzs z4.d, p2/m, z2.d284; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d285; CHECK-NEXT: sel z0.d, p4, z25.d, z6.d286; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload287; CHECK-NEXT: mov z1.d, p3/m, #0 // =0x0288; CHECK-NEXT: fcmuo p6.d, p0/z, z3.d, z3.d289; CHECK-NEXT: fcmuo p0.d, p0/z, z2.d, z2.d290; CHECK-NEXT: sel z2.d, p1, z25.d, z7.d291; CHECK-NEXT: sel z3.d, p5, z25.d, z4.d292; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload293; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0294; CHECK-NEXT: mov z2.d, p6/m, #0 // =0x0295; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload296; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0297; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s298; CHECK-NEXT: uzp1 z1.s, z3.s, z2.s299; CHECK-NEXT: addvl sp, sp, #1300; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload301; CHECK-NEXT: ret302 %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)303 ret <vscale x 8 x i32> %x304}305 306define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {307; CHECK-LABEL: test_signed_v4f64_v4i16:308; CHECK: // %bb.0:309; CHECK-NEXT: mov x8, #-4548635623644200960 // =0xc0e0000000000000310; CHECK-NEXT: ptrue p0.d311; CHECK-NEXT: mov z3.d, #-32768 // =0xffffffffffff8000312; CHECK-NEXT: mov z2.d, x8313; CHECK-NEXT: mov x8, #281200098803712 // =0xffc000000000314; CHECK-NEXT: mov z5.d, #32767 // =0x7fff315; CHECK-NEXT: movk x8, #16607, lsl #48316; CHECK-NEXT: mov z4.d, x8317; CHECK-NEXT: fcmge p1.d, p0/z, z1.d, z2.d318; CHECK-NEXT: fcmge p2.d, p0/z, z0.d, z2.d319; CHECK-NEXT: mov z2.d, #-32768 // =0xffffffffffff8000320; CHECK-NEXT: fcmgt p3.d, p0/z, z0.d, z4.d321; CHECK-NEXT: fcvtzs z3.d, p1/m, z1.d322; CHECK-NEXT: fcmgt p1.d, p0/z, z1.d, z4.d323; CHECK-NEXT: fcvtzs z2.d, p2/m, z0.d324; CHECK-NEXT: fcmuo p2.d, p0/z, z1.d, z1.d325; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d326; CHECK-NEXT: sel z0.d, p1, z5.d, z3.d327; CHECK-NEXT: sel z1.d, p3, z5.d, z2.d328; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0329; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0330; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s331; CHECK-NEXT: ret332 %x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f64.nxv4i16(<vscale x 4 x double> %f)333 ret <vscale x 4 x i16> %x334}335 336define <vscale x 8 x i16> @test_signed_v8f64_v8i16(<vscale x 8 x double> %f) {337; CHECK-LABEL: test_signed_v8f64_v8i16:338; CHECK: // %bb.0:339; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill340; CHECK-NEXT: addvl sp, sp, #-1341; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill342; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill343; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill344; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG345; CHECK-NEXT: .cfi_offset w29, -16346; CHECK-NEXT: mov x8, #-4548635623644200960 // =0xc0e0000000000000347; CHECK-NEXT: ptrue p0.d348; CHECK-NEXT: mov z5.d, #-32768 // =0xffffffffffff8000349; CHECK-NEXT: mov z4.d, x8350; CHECK-NEXT: mov x8, #281200098803712 // =0xffc000000000351; CHECK-NEXT: mov z7.d, #-32768 // =0xffffffffffff8000352; CHECK-NEXT: movk x8, #16607, lsl #48353; CHECK-NEXT: mov z24.d, #-32768 // =0xffffffffffff8000354; CHECK-NEXT: mov z25.d, #32767 // =0x7fff355; CHECK-NEXT: mov z6.d, x8356; CHECK-NEXT: fcmge p1.d, p0/z, z3.d, z4.d357; CHECK-NEXT: fcmge p2.d, p0/z, z2.d, z4.d358; CHECK-NEXT: fcmge p3.d, p0/z, z1.d, z4.d359; CHECK-NEXT: fcmgt p4.d, p0/z, z2.d, z6.d360; CHECK-NEXT: fcvtzs z5.d, p1/m, z3.d361; CHECK-NEXT: fcmgt p1.d, p0/z, z3.d, z6.d362; CHECK-NEXT: fcvtzs z7.d, p2/m, z2.d363; CHECK-NEXT: fcmge p2.d, p0/z, z0.d, z4.d364; CHECK-NEXT: fcvtzs z24.d, p3/m, z1.d365; CHECK-NEXT: fcmuo p3.d, p0/z, z3.d, z3.d366; CHECK-NEXT: mov z3.d, #-32768 // =0xffffffffffff8000367; CHECK-NEXT: fcmgt p5.d, p0/z, z0.d, z6.d368; CHECK-NEXT: sel z4.d, p1, z25.d, z5.d369; CHECK-NEXT: fcmgt p1.d, p0/z, z1.d, z6.d370; CHECK-NEXT: fcvtzs z3.d, p2/m, z0.d371; CHECK-NEXT: fcmuo p2.d, p0/z, z2.d, z2.d372; CHECK-NEXT: fcmuo p6.d, p0/z, z1.d, z1.d373; CHECK-NEXT: mov z4.d, p3/m, #0 // =0x0374; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d375; CHECK-NEXT: sel z0.d, p4, z25.d, z7.d376; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload377; CHECK-NEXT: sel z1.d, p1, z25.d, z24.d378; CHECK-NEXT: sel z2.d, p5, z25.d, z3.d379; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload380; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0381; CHECK-NEXT: mov z1.d, p6/m, #0 // =0x0382; CHECK-NEXT: mov z2.d, p0/m, #0 // =0x0383; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload384; CHECK-NEXT: uzp1 z0.s, z0.s, z4.s385; CHECK-NEXT: uzp1 z1.s, z2.s, z1.s386; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h387; CHECK-NEXT: addvl sp, sp, #1388; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload389; CHECK-NEXT: ret390 %x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f64.nxv8i16(<vscale x 8 x double> %f)391 ret <vscale x 8 x i16> %x392}393 394define <vscale x 2 x i64> @test_signed_v2f64_v2i64(<vscale x 2 x double> %f) {395; CHECK-LABEL: test_signed_v2f64_v2i64:396; CHECK: // %bb.0:397; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000398; CHECK-NEXT: ptrue p0.d399; CHECK-NEXT: mov z1.d, x8400; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff401; CHECK-NEXT: mov z2.d, x8402; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d403; CHECK-NEXT: mov z1.d, #0x8000000000000000404; CHECK-NEXT: fcmgt p2.d, p0/z, z0.d, z2.d405; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff406; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d407; CHECK-NEXT: fcvtzs z1.d, p1/m, z0.d408; CHECK-NEXT: sel z0.d, p2, z2.d, z1.d409; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0410; CHECK-NEXT: ret411 %x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f64.nxv2i64(<vscale x 2 x double> %f)412 ret <vscale x 2 x i64> %x413}414 415define <vscale x 4 x i64> @test_signed_v4f64_v4i64(<vscale x 4 x double> %f) {416; CHECK-LABEL: test_signed_v4f64_v4i64:417; CHECK: // %bb.0:418; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000419; CHECK-NEXT: ptrue p0.d420; CHECK-NEXT: mov z3.d, #0x8000000000000000421; CHECK-NEXT: mov z2.d, x8422; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff423; CHECK-NEXT: mov z4.d, #0x8000000000000000424; CHECK-NEXT: mov z5.d, x8425; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z2.d426; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z2.d427; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff428; CHECK-NEXT: fcmgt p3.d, p0/z, z1.d, z5.d429; CHECK-NEXT: fcvtzs z3.d, p1/m, z0.d430; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z5.d431; CHECK-NEXT: fcvtzs z4.d, p2/m, z1.d432; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d433; CHECK-NEXT: fcmuo p0.d, p0/z, z1.d, z1.d434; CHECK-NEXT: sel z0.d, p1, z2.d, z3.d435; CHECK-NEXT: sel z1.d, p3, z2.d, z4.d436; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0437; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0438; CHECK-NEXT: ret439 %x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double> %f)440 ret <vscale x 4 x i64> %x441}442 443 444; half445 446declare <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f16.nxv2i32(<vscale x 2 x half>)447declare <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f16.nxv4i32(<vscale x 4 x half>)448declare <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f16.nxv8i32(<vscale x 8 x half>)449declare <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f16.nxv4i16(<vscale x 4 x half>)450declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half>)451declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half>)452declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)453 454define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {455; CHECK-LABEL: test_signed_v2f16_v2i32:456; CHECK: // %bb.0:457; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff458; CHECK-NEXT: ptrue p0.d459; CHECK-NEXT: mov w8, #31743 // =0x7bff460; CHECK-NEXT: mov z2.d, #0xffffffff80000000461; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h462; CHECK-NEXT: mov z1.h, w8463; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h464; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h465; CHECK-NEXT: mov z1.d, #0x7fffffff466; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h467; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d468; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0469; CHECK-NEXT: ret470 %x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)471 ret <vscale x 2 x i32> %x472}473 474define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {475; CHECK-LABEL: test_signed_v4f16_v4i32:476; CHECK: // %bb.0:477; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff478; CHECK-NEXT: ptrue p0.s479; CHECK-NEXT: mov w8, #31743 // =0x7bff480; CHECK-NEXT: mov z2.s, #0x80000000481; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h482; CHECK-NEXT: mov z1.h, w8483; CHECK-NEXT: fcvtzs z2.s, p1/m, z0.h484; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h485; CHECK-NEXT: mov z1.s, #0x7fffffff486; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h487; CHECK-NEXT: sel z0.s, p1, z1.s, z2.s488; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0489; CHECK-NEXT: ret490 %x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)491 ret <vscale x 4 x i32> %x492}493 494define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {495; CHECK-LABEL: test_signed_v8f16_v8i32:496; CHECK: // %bb.0:497; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff498; CHECK-NEXT: uunpklo z2.s, z0.h499; CHECK-NEXT: mov w8, #31743 // =0x7bff500; CHECK-NEXT: uunpkhi z0.s, z0.h501; CHECK-NEXT: ptrue p0.s502; CHECK-NEXT: mov z3.s, #0x80000000503; CHECK-NEXT: mov z4.s, #0x80000000504; CHECK-NEXT: mov z5.h, w8505; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, z1.h506; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z1.h507; CHECK-NEXT: mov z1.s, #0x7fffffff508; CHECK-NEXT: fcmgt p3.h, p0/z, z0.h, z5.h509; CHECK-NEXT: fcvtzs z3.s, p1/m, z2.h510; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z5.h511; CHECK-NEXT: fcvtzs z4.s, p2/m, z0.h512; CHECK-NEXT: fcmuo p2.h, p0/z, z2.h, z2.h513; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h514; CHECK-NEXT: sel z0.s, p1, z1.s, z3.s515; CHECK-NEXT: sel z1.s, p3, z1.s, z4.s516; CHECK-NEXT: mov z0.s, p2/m, #0 // =0x0517; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0518; CHECK-NEXT: ret519 %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)520 ret <vscale x 8 x i32> %x521}522 523define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {524; CHECK-LABEL: test_signed_v4f16_v4i16:525; CHECK: // %bb.0:526; CHECK-NEXT: dupm z1.h, #0xf800527; CHECK-NEXT: ptrue p0.s528; CHECK-NEXT: mov w8, #30719 // =0x77ff529; CHECK-NEXT: mov z2.h, w8530; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h531; CHECK-NEXT: mov z1.s, #-32768 // =0xffffffffffff8000532; CHECK-NEXT: fcvtzs z1.s, p1/m, z0.h533; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z2.h534; CHECK-NEXT: mov z2.s, #32767 // =0x7fff535; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h536; CHECK-NEXT: sel z0.s, p1, z2.s, z1.s537; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0538; CHECK-NEXT: ret539 %x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f16.nxv4i16(<vscale x 4 x half> %f)540 ret <vscale x 4 x i16> %x541}542 543define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {544; CHECK-LABEL: test_signed_v8f16_v8i16:545; CHECK: // %bb.0:546; CHECK-NEXT: dupm z1.h, #0xf800547; CHECK-NEXT: ptrue p0.h548; CHECK-NEXT: mov w8, #30719 // =0x77ff549; CHECK-NEXT: mov z2.h, w8550; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h551; CHECK-NEXT: mov z1.h, #-32768 // =0xffffffffffff8000552; CHECK-NEXT: fcvtzs z1.h, p1/m, z0.h553; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z2.h554; CHECK-NEXT: mov z2.h, #32767 // =0x7fff555; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h556; CHECK-NEXT: sel z0.h, p1, z2.h, z1.h557; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x0558; CHECK-NEXT: ret559 %x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)560 ret <vscale x 8 x i16> %x561}562 563define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {564; CHECK-LABEL: test_signed_v2f16_v2i64:565; CHECK: // %bb.0:566; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff567; CHECK-NEXT: ptrue p0.d568; CHECK-NEXT: mov w8, #31743 // =0x7bff569; CHECK-NEXT: mov z2.d, #0x8000000000000000570; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h571; CHECK-NEXT: mov z1.h, w8572; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h573; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h574; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff575; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h576; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d577; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0578; CHECK-NEXT: ret579 %x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)580 ret <vscale x 2 x i64> %x581}582 583define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {584; CHECK-LABEL: test_signed_v4f16_v4i64:585; CHECK: // %bb.0:586; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff587; CHECK-NEXT: uunpklo z2.d, z0.s588; CHECK-NEXT: mov w8, #31743 // =0x7bff589; CHECK-NEXT: uunpkhi z0.d, z0.s590; CHECK-NEXT: ptrue p0.d591; CHECK-NEXT: mov z3.d, #0x8000000000000000592; CHECK-NEXT: mov z4.d, #0x8000000000000000593; CHECK-NEXT: mov z5.h, w8594; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, z1.h595; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z1.h596; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff597; CHECK-NEXT: fcmgt p3.h, p0/z, z0.h, z5.h598; CHECK-NEXT: fcvtzs z3.d, p1/m, z2.h599; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z5.h600; CHECK-NEXT: fcvtzs z4.d, p2/m, z0.h601; CHECK-NEXT: fcmuo p2.h, p0/z, z2.h, z2.h602; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h603; CHECK-NEXT: sel z0.d, p1, z1.d, z3.d604; CHECK-NEXT: sel z1.d, p3, z1.d, z4.d605; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0606; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0607; CHECK-NEXT: ret608 %x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)609 ret <vscale x 4 x i64> %x610}611 612