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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s3 4; Float5 6declare <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f32.nxv2i32(<vscale x 2 x float>)7declare <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f32.nxv4i32(<vscale x 4 x float>)8declare <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f32.nxv8i32(<vscale x 8 x float>)9declare <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f32.nxv4i16(<vscale x 4 x float>)10declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f32.nxv8i16(<vscale x 8 x float>)11declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f32.nxv2i64(<vscale x 2 x float>)12declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f32.nxv4i64(<vscale x 4 x float>)13 14define <vscale x 2 x i32> @test_signed_v2f32_v2i32(<vscale x 2 x float> %f) {15; CHECK-LABEL: test_signed_v2f32_v2i32:16; CHECK: // %bb.0:17; CHECK-NEXT: ptrue p0.d18; CHECK-NEXT: mov w8, #1333788671 // =0x4f7fffff19; CHECK-NEXT: movi v1.2d, #000000000000000020; CHECK-NEXT: mov z2.s, w821; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.022; CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s23; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.s24; CHECK-NEXT: mov z0.d, #0xffffffff25; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d26; CHECK-NEXT: ret27 %x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f32.nxv2i32(<vscale x 2 x float> %f)28 ret <vscale x 2 x i32> %x29}30 31define <vscale x 4 x i32> @test_signed_v4f32_v4i32(<vscale x 4 x float> %f) {32; CHECK-LABEL: test_signed_v4f32_v4i32:33; CHECK: // %bb.0:34; CHECK-NEXT: ptrue p0.s35; CHECK-NEXT: mov w8, #1333788671 // =0x4f7fffff36; CHECK-NEXT: movi v1.2d, #000000000000000037; CHECK-NEXT: mov z2.s, w838; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.039; CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s40; CHECK-NEXT: fcvtzu z1.s, p1/m, z0.s41; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff42; CHECK-NEXT: mov z0.d, z1.d43; CHECK-NEXT: ret44 %x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f32.nxv4i32(<vscale x 4 x float> %f)45 ret <vscale x 4 x i32> %x46}47 48define <vscale x 8 x i32> @test_signed_v8f32_v8i32(<vscale x 8 x float> %f) {49; CHECK-LABEL: test_signed_v8f32_v8i32:50; CHECK: // %bb.0:51; CHECK-NEXT: ptrue p0.s52; CHECK-NEXT: mov w8, #1333788671 // =0x4f7fffff53; CHECK-NEXT: movi v2.2d, #000000000000000054; CHECK-NEXT: movi v3.2d, #000000000000000055; CHECK-NEXT: mov z4.s, w856; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.057; CHECK-NEXT: fcmge p2.s, p0/z, z1.s, #0.058; CHECK-NEXT: fcvtzu z2.s, p1/m, z0.s59; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z4.s60; CHECK-NEXT: fcvtzu z3.s, p2/m, z1.s61; CHECK-NEXT: fcmgt p0.s, p0/z, z1.s, z4.s62; CHECK-NEXT: mov z2.s, p1/m, #-1 // =0xffffffffffffffff63; CHECK-NEXT: mov z3.s, p0/m, #-1 // =0xffffffffffffffff64; CHECK-NEXT: mov z0.d, z2.d65; CHECK-NEXT: mov z1.d, z3.d66; CHECK-NEXT: ret67 %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)68 ret <vscale x 8 x i32> %x69}70 71define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {72; CHECK-LABEL: test_signed_v4f32_v4i16:73; CHECK: // %bb.0:74; CHECK-NEXT: ptrue p0.s75; CHECK-NEXT: mov w8, #65280 // =0xff0076; CHECK-NEXT: movi v1.2d, #000000000000000077; CHECK-NEXT: movk w8, #18303, lsl #1678; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.079; CHECK-NEXT: mov z2.s, w880; CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s81; CHECK-NEXT: fcvtzu z1.s, p1/m, z0.s82; CHECK-NEXT: mov z0.s, #65535 // =0xffff83; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s84; CHECK-NEXT: ret85 %x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)86 ret <vscale x 4 x i16> %x87}88 89define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {90; CHECK-LABEL: test_signed_v8f32_v8i16:91; CHECK: // %bb.0:92; CHECK-NEXT: ptrue p0.s93; CHECK-NEXT: mov w8, #65280 // =0xff0094; CHECK-NEXT: movi v2.2d, #000000000000000095; CHECK-NEXT: movk w8, #18303, lsl #1696; CHECK-NEXT: movi v3.2d, #000000000000000097; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, #0.098; CHECK-NEXT: mov z4.s, w899; CHECK-NEXT: fcmge p2.s, p0/z, z0.s, #0.0100; CHECK-NEXT: fcvtzu z2.s, p1/m, z1.s101; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z4.s102; CHECK-NEXT: mov z1.s, #65535 // =0xffff103; CHECK-NEXT: fcvtzu z3.s, p2/m, z0.s104; CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, z4.s105; CHECK-NEXT: sel z0.s, p1, z1.s, z2.s106; CHECK-NEXT: sel z1.s, p0, z1.s, z3.s107; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h108; CHECK-NEXT: ret109 %x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)110 ret <vscale x 8 x i16> %x111}112 113define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {114; CHECK-LABEL: test_signed_v2f32_v2i64:115; CHECK: // %bb.0:116; CHECK-NEXT: ptrue p0.d117; CHECK-NEXT: mov w8, #1602224127 // =0x5f7fffff118; CHECK-NEXT: movi v1.2d, #0000000000000000119; CHECK-NEXT: mov z2.s, w8120; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.0121; CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s122; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.s123; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff124; CHECK-NEXT: mov z0.d, z1.d125; CHECK-NEXT: ret126 %x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)127 ret <vscale x 2 x i64> %x128}129 130define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {131; CHECK-LABEL: test_signed_v4f32_v4i64:132; CHECK: // %bb.0:133; CHECK-NEXT: uunpklo z2.d, z0.s134; CHECK-NEXT: uunpkhi z3.d, z0.s135; CHECK-NEXT: mov w8, #1602224127 // =0x5f7fffff136; CHECK-NEXT: ptrue p0.d137; CHECK-NEXT: movi v0.2d, #0000000000000000138; CHECK-NEXT: movi v1.2d, #0000000000000000139; CHECK-NEXT: mov z4.s, w8140; CHECK-NEXT: fcmge p1.s, p0/z, z2.s, #0.0141; CHECK-NEXT: fcmge p2.s, p0/z, z3.s, #0.0142; CHECK-NEXT: fcvtzu z0.d, p1/m, z2.s143; CHECK-NEXT: fcmgt p1.s, p0/z, z2.s, z4.s144; CHECK-NEXT: fcvtzu z1.d, p2/m, z3.s145; CHECK-NEXT: fcmgt p0.s, p0/z, z3.s, z4.s146; CHECK-NEXT: mov z0.d, p1/m, #-1 // =0xffffffffffffffff147; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff148; CHECK-NEXT: ret149 %x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)150 ret <vscale x 4 x i64> %x151}152 153; Double154 155declare <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double>)156declare <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double>)157declare <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double>)158declare <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f64.nxv4i16(<vscale x 4 x double>)159declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f64.nxv8i16(<vscale x 8 x double>)160declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f64.nxv2i64(<vscale x 2 x double>)161declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f64.nxv4i64(<vscale x 4 x double>)162 163define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {164; CHECK-LABEL: test_signed_v2f64_v2i32:165; CHECK: // %bb.0:166; CHECK-NEXT: ptrue p0.d167; CHECK-NEXT: mov x8, #281474974613504 // =0xffffffe00000168; CHECK-NEXT: movi v1.2d, #0000000000000000169; CHECK-NEXT: movk x8, #16879, lsl #48170; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, #0.0171; CHECK-NEXT: mov z2.d, x8172; CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z2.d173; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.d174; CHECK-NEXT: mov z0.d, #0xffffffff175; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d176; CHECK-NEXT: ret177 %x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)178 ret <vscale x 2 x i32> %x179}180 181define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {182; CHECK-LABEL: test_signed_v4f64_v4i32:183; CHECK: // %bb.0:184; CHECK-NEXT: ptrue p0.d185; CHECK-NEXT: mov x8, #281474974613504 // =0xffffffe00000186; CHECK-NEXT: movi v2.2d, #0000000000000000187; CHECK-NEXT: movk x8, #16879, lsl #48188; CHECK-NEXT: movi v3.2d, #0000000000000000189; CHECK-NEXT: fcmge p1.d, p0/z, z1.d, #0.0190; CHECK-NEXT: mov z4.d, x8191; CHECK-NEXT: fcmge p2.d, p0/z, z0.d, #0.0192; CHECK-NEXT: fcvtzu z2.d, p1/m, z1.d193; CHECK-NEXT: fcmgt p1.d, p0/z, z1.d, z4.d194; CHECK-NEXT: mov z1.d, #0xffffffff195; CHECK-NEXT: fcvtzu z3.d, p2/m, z0.d196; CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z4.d197; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d198; CHECK-NEXT: sel z1.d, p0, z1.d, z3.d199; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s200; CHECK-NEXT: ret201 %x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)202 ret <vscale x 4 x i32> %x203}204 205define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {206; CHECK-LABEL: test_signed_v8f64_v8i32:207; CHECK: // %bb.0:208; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill209; CHECK-NEXT: addvl sp, sp, #-1210; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill211; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG212; CHECK-NEXT: .cfi_offset w29, -16213; CHECK-NEXT: ptrue p0.d214; CHECK-NEXT: mov x8, #281474974613504 // =0xffffffe00000215; CHECK-NEXT: movi v4.2d, #0000000000000000216; CHECK-NEXT: movk x8, #16879, lsl #48217; CHECK-NEXT: movi v5.2d, #0000000000000000218; CHECK-NEXT: movi v6.2d, #0000000000000000219; CHECK-NEXT: fcmge p1.d, p0/z, z1.d, #0.0220; CHECK-NEXT: movi v24.2d, #0000000000000000221; CHECK-NEXT: mov z7.d, x8222; CHECK-NEXT: fcmge p2.d, p0/z, z0.d, #0.0223; CHECK-NEXT: fcmge p3.d, p0/z, z3.d, #0.0224; CHECK-NEXT: fcmge p4.d, p0/z, z2.d, #0.0225; CHECK-NEXT: fcvtzu z4.d, p1/m, z1.d226; CHECK-NEXT: fcvtzu z5.d, p2/m, z0.d227; CHECK-NEXT: fcvtzu z6.d, p3/m, z3.d228; CHECK-NEXT: fcmgt p1.d, p0/z, z1.d, z7.d229; CHECK-NEXT: fcvtzu z24.d, p4/m, z2.d230; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload231; CHECK-NEXT: fcmgt p2.d, p0/z, z0.d, z7.d232; CHECK-NEXT: mov z0.d, #0xffffffff233; CHECK-NEXT: fcmgt p3.d, p0/z, z3.d, z7.d234; CHECK-NEXT: fcmgt p0.d, p0/z, z2.d, z7.d235; CHECK-NEXT: sel z1.d, p1, z0.d, z4.d236; CHECK-NEXT: sel z2.d, p2, z0.d, z5.d237; CHECK-NEXT: sel z3.d, p3, z0.d, z6.d238; CHECK-NEXT: sel z4.d, p0, z0.d, z24.d239; CHECK-NEXT: uzp1 z0.s, z2.s, z1.s240; CHECK-NEXT: uzp1 z1.s, z4.s, z3.s241; CHECK-NEXT: addvl sp, sp, #1242; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload243; CHECK-NEXT: ret244 %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)245 ret <vscale x 8 x i32> %x246}247 248define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {249; CHECK-LABEL: test_signed_v4f64_v4i16:250; CHECK: // %bb.0:251; CHECK-NEXT: ptrue p0.d252; CHECK-NEXT: mov x8, #281337537757184 // =0xffe000000000253; CHECK-NEXT: movi v2.2d, #0000000000000000254; CHECK-NEXT: movk x8, #16623, lsl #48255; CHECK-NEXT: movi v3.2d, #0000000000000000256; CHECK-NEXT: fcmge p1.d, p0/z, z1.d, #0.0257; CHECK-NEXT: mov z4.d, x8258; CHECK-NEXT: fcmge p2.d, p0/z, z0.d, #0.0259; CHECK-NEXT: fcvtzu z2.d, p1/m, z1.d260; CHECK-NEXT: fcmgt p1.d, p0/z, z1.d, z4.d261; CHECK-NEXT: mov z1.d, #65535 // =0xffff262; CHECK-NEXT: fcvtzu z3.d, p2/m, z0.d263; CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z4.d264; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d265; CHECK-NEXT: sel z1.d, p0, z1.d, z3.d266; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s267; CHECK-NEXT: ret268 %x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f64.nxv4i16(<vscale x 4 x double> %f)269 ret <vscale x 4 x i16> %x270}271 272define <vscale x 8 x i16> @test_signed_v8f64_v8i16(<vscale x 8 x double> %f) {273; CHECK-LABEL: test_signed_v8f64_v8i16:274; CHECK: // %bb.0:275; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill276; CHECK-NEXT: addvl sp, sp, #-1277; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill278; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG279; CHECK-NEXT: .cfi_offset w29, -16280; CHECK-NEXT: ptrue p0.d281; CHECK-NEXT: mov x8, #281337537757184 // =0xffe000000000282; CHECK-NEXT: movi v4.2d, #0000000000000000283; CHECK-NEXT: movk x8, #16623, lsl #48284; CHECK-NEXT: movi v5.2d, #0000000000000000285; CHECK-NEXT: movi v6.2d, #0000000000000000286; CHECK-NEXT: fcmge p1.d, p0/z, z3.d, #0.0287; CHECK-NEXT: movi v24.2d, #0000000000000000288; CHECK-NEXT: mov z7.d, x8289; CHECK-NEXT: fcmge p2.d, p0/z, z2.d, #0.0290; CHECK-NEXT: fcmge p3.d, p0/z, z1.d, #0.0291; CHECK-NEXT: fcmge p4.d, p0/z, z0.d, #0.0292; CHECK-NEXT: fcvtzu z4.d, p1/m, z3.d293; CHECK-NEXT: fcvtzu z5.d, p2/m, z2.d294; CHECK-NEXT: fcvtzu z6.d, p3/m, z1.d295; CHECK-NEXT: fcmgt p1.d, p0/z, z3.d, z7.d296; CHECK-NEXT: fcvtzu z24.d, p4/m, z0.d297; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload298; CHECK-NEXT: fcmgt p2.d, p0/z, z2.d, z7.d299; CHECK-NEXT: mov z2.d, #65535 // =0xffff300; CHECK-NEXT: fcmgt p3.d, p0/z, z1.d, z7.d301; CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z7.d302; CHECK-NEXT: sel z0.d, p1, z2.d, z4.d303; CHECK-NEXT: sel z1.d, p2, z2.d, z5.d304; CHECK-NEXT: sel z3.d, p3, z2.d, z6.d305; CHECK-NEXT: sel z2.d, p0, z2.d, z24.d306; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s307; CHECK-NEXT: uzp1 z1.s, z2.s, z3.s308; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h309; CHECK-NEXT: addvl sp, sp, #1310; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload311; CHECK-NEXT: ret312 %x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f64.nxv8i16(<vscale x 8 x double> %f)313 ret <vscale x 8 x i16> %x314}315 316define <vscale x 2 x i64> @test_signed_v2f64_v2i64(<vscale x 2 x double> %f) {317; CHECK-LABEL: test_signed_v2f64_v2i64:318; CHECK: // %bb.0:319; CHECK-NEXT: ptrue p0.d320; CHECK-NEXT: mov x8, #4895412794951729151 // =0x43efffffffffffff321; CHECK-NEXT: movi v1.2d, #0000000000000000322; CHECK-NEXT: mov z2.d, x8323; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, #0.0324; CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z2.d325; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.d326; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff327; CHECK-NEXT: mov z0.d, z1.d328; CHECK-NEXT: ret329 %x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f64.nxv2i64(<vscale x 2 x double> %f)330 ret <vscale x 2 x i64> %x331}332 333define <vscale x 4 x i64> @test_signed_v4f64_v4i64(<vscale x 4 x double> %f) {334; CHECK-LABEL: test_signed_v4f64_v4i64:335; CHECK: // %bb.0:336; CHECK-NEXT: ptrue p0.d337; CHECK-NEXT: mov x8, #4895412794951729151 // =0x43efffffffffffff338; CHECK-NEXT: movi v2.2d, #0000000000000000339; CHECK-NEXT: movi v3.2d, #0000000000000000340; CHECK-NEXT: mov z4.d, x8341; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, #0.0342; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, #0.0343; CHECK-NEXT: fcvtzu z2.d, p1/m, z0.d344; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z4.d345; CHECK-NEXT: fcvtzu z3.d, p2/m, z1.d346; CHECK-NEXT: fcmgt p0.d, p0/z, z1.d, z4.d347; CHECK-NEXT: mov z2.d, p1/m, #-1 // =0xffffffffffffffff348; CHECK-NEXT: mov z3.d, p0/m, #-1 // =0xffffffffffffffff349; CHECK-NEXT: mov z0.d, z2.d350; CHECK-NEXT: mov z1.d, z3.d351; CHECK-NEXT: ret352 %x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f64.nxv4i64(<vscale x 4 x double> %f)353 ret <vscale x 4 x i64> %x354}355 356 357; half358 359declare <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f16.nxv2i32(<vscale x 2 x half>)360declare <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f16.nxv4i32(<vscale x 4 x half>)361declare <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f16.nxv8i32(<vscale x 8 x half>)362declare <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f16.nxv4i16(<vscale x 4 x half>)363declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half>)364declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half>)365declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)366 367define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {368; CHECK-LABEL: test_signed_v2f16_v2i32:369; CHECK: // %bb.0:370; CHECK-NEXT: ptrue p0.d371; CHECK-NEXT: mov w8, #31743 // =0x7bff372; CHECK-NEXT: movi v1.2d, #0000000000000000373; CHECK-NEXT: mov z2.h, w8374; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0375; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h376; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.h377; CHECK-NEXT: mov z0.d, #0xffffffff378; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d379; CHECK-NEXT: ret380 %x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)381 ret <vscale x 2 x i32> %x382}383 384define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {385; CHECK-LABEL: test_signed_v4f16_v4i32:386; CHECK: // %bb.0:387; CHECK-NEXT: ptrue p0.s388; CHECK-NEXT: mov w8, #31743 // =0x7bff389; CHECK-NEXT: movi v1.2d, #0000000000000000390; CHECK-NEXT: mov z2.h, w8391; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0392; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h393; CHECK-NEXT: fcvtzu z1.s, p1/m, z0.h394; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff395; CHECK-NEXT: mov z0.d, z1.d396; CHECK-NEXT: ret397 %x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)398 ret <vscale x 4 x i32> %x399}400 401define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {402; CHECK-LABEL: test_signed_v8f16_v8i32:403; CHECK: // %bb.0:404; CHECK-NEXT: uunpklo z2.s, z0.h405; CHECK-NEXT: uunpkhi z3.s, z0.h406; CHECK-NEXT: mov w8, #31743 // =0x7bff407; CHECK-NEXT: ptrue p0.s408; CHECK-NEXT: movi v0.2d, #0000000000000000409; CHECK-NEXT: movi v1.2d, #0000000000000000410; CHECK-NEXT: mov z4.h, w8411; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, #0.0412; CHECK-NEXT: fcmge p2.h, p0/z, z3.h, #0.0413; CHECK-NEXT: fcvtzu z0.s, p1/m, z2.h414; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z4.h415; CHECK-NEXT: fcvtzu z1.s, p2/m, z3.h416; CHECK-NEXT: fcmgt p0.h, p0/z, z3.h, z4.h417; CHECK-NEXT: mov z0.s, p1/m, #-1 // =0xffffffffffffffff418; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff419; CHECK-NEXT: ret420 %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)421 ret <vscale x 8 x i32> %x422}423 424define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {425; CHECK-LABEL: test_signed_v4f16_v4i16:426; CHECK: // %bb.0:427; CHECK-NEXT: ptrue p0.s428; CHECK-NEXT: mov w8, #31743 // =0x7bff429; CHECK-NEXT: movi v1.2d, #0000000000000000430; CHECK-NEXT: mov z2.h, w8431; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0432; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h433; CHECK-NEXT: fcvtzu z1.s, p1/m, z0.h434; CHECK-NEXT: mov z0.s, #65535 // =0xffff435; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s436; CHECK-NEXT: ret437 %x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f16.nxv4i16(<vscale x 4 x half> %f)438 ret <vscale x 4 x i16> %x439}440 441define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {442; CHECK-LABEL: test_signed_v8f16_v8i16:443; CHECK: // %bb.0:444; CHECK-NEXT: ptrue p0.h445; CHECK-NEXT: mov w8, #31743 // =0x7bff446; CHECK-NEXT: movi v1.2d, #0000000000000000447; CHECK-NEXT: mov z2.h, w8448; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0449; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h450; CHECK-NEXT: fcvtzu z1.h, p1/m, z0.h451; CHECK-NEXT: mov z1.h, p0/m, #-1 // =0xffffffffffffffff452; CHECK-NEXT: mov z0.d, z1.d453; CHECK-NEXT: ret454 %x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)455 ret <vscale x 8 x i16> %x456}457 458define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {459; CHECK-LABEL: test_signed_v2f16_v2i64:460; CHECK: // %bb.0:461; CHECK-NEXT: ptrue p0.d462; CHECK-NEXT: mov w8, #31743 // =0x7bff463; CHECK-NEXT: movi v1.2d, #0000000000000000464; CHECK-NEXT: mov z2.h, w8465; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0466; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h467; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.h468; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff469; CHECK-NEXT: mov z0.d, z1.d470; CHECK-NEXT: ret471 %x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)472 ret <vscale x 2 x i64> %x473}474 475define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {476; CHECK-LABEL: test_signed_v4f16_v4i64:477; CHECK: // %bb.0:478; CHECK-NEXT: uunpklo z2.d, z0.s479; CHECK-NEXT: uunpkhi z3.d, z0.s480; CHECK-NEXT: mov w8, #31743 // =0x7bff481; CHECK-NEXT: ptrue p0.d482; CHECK-NEXT: movi v0.2d, #0000000000000000483; CHECK-NEXT: movi v1.2d, #0000000000000000484; CHECK-NEXT: mov z4.h, w8485; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, #0.0486; CHECK-NEXT: fcmge p2.h, p0/z, z3.h, #0.0487; CHECK-NEXT: fcvtzu z0.d, p1/m, z2.h488; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z4.h489; CHECK-NEXT: fcvtzu z1.d, p2/m, z3.h490; CHECK-NEXT: fcmgt p0.h, p0/z, z3.h, z4.h491; CHECK-NEXT: mov z0.d, p1/m, #-1 // =0xffffffffffffffff492; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff493; CHECK-NEXT: ret494 %x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)495 ret <vscale x 4 x i64> %x496}497 498